Fujitsu MB90895 Series User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
F2MC®-16LX
16 bit Microcontroller
MB90895 series
Hardware Manual
CM44-10127-1E

FUJITSU LIMITED
F2MC®-16LX
16 bit Microcontroller
MB90895 series
Hardware Manual

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Preface
■Purpose of this document and intended reader
We sincerely thank you for your continued use of Fujitsu semiconductor products.
The MB90895 series are proprietary 16-bit single-chip microcontrollers which can be incorporated
into ASICs (application specific ICs) and were developed as general-purpose products in the
F2MC-16LX series.
This manual describes the functions and operation of the MB90895 series and is intended for
engineers who intend to use MB90895 series microcontrollers to develop actual products. Please
read through this manual.
■Trademarks
F2MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of
FUJITSU Ltd.

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■Organization of this document
This manual contains the following 21 chapters and an appendix.
CHAPTER 1 Overview
This chapter describes the features and basic specifications of MB90895 series.
CHAPTER 2 Handling Devices
This chapter describes points to note when using the MB90895 series.
CHAPTER 3 CPU
This chapter explains the function and operation of the CPU.
CHAPTER 4 I/O PORT
This chapter describes the function and operation of the I/O port.
CHAPTER 5 Timebase Timer
This chapter describes the function and operation of the I/O port.
CHAPTER 6 Watchdog Timer
This chapter explains the functions and operation of the watchdog timer.
CHAPTER 7 16-bit I/O Timer
This chapter describes the function and operation of the 16-bit I/O timer.
CHAPTER 8 16-bit Reload Timer
This chapter describes the function and operation of the 16-bit reload timer.
CHAPTER 9 Watch Timer
This chapter explains the functions and operation of the watch timer.
CHAPTER 10 8-/16-bit PPG Timer
This section describes the functions and operations of the 8-/16-bit PPG timer.
CHAPTER 11 Delayed Interrupt Generation Module
This section describes the functions and operations of the delayed interrupt generation
module.
CHAPTER 12 DTP/External Interrupt Circuit
This section describes the functions and operations of the DTP/external interrupt.
CHAPTER 13 8-/10-bit A/D Converter
This section describes the functions and operations of the 8-/10-bit A/D converter.
CHAPTER 14 UART0
This section describes the functions and operations of the UART0.
CHAPTER 15 UART1
This section describes the functions and operations of the UART1.
CHAPTER 16 CAN Controller
This section describes the functions and operations of the CAN controller.
CHAPTER 17 Address Match Detecting Function
This section describes the functions and operations of the address match detecting function.
CHAPTER 18 ROM Mirror Function Selection Module
This section describes the functions and operations of the ROM mirror function selection

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module
CHAPTER 19 512 KBIT FLASH MEMORY
This section describes the functions and operations of the 512 Kbit flash memory.
CHAPTER 20 Dual Operation Flash
This section describes the functions and operations of the dual operation flash.
CHAPTER 21 FLASH SERIAL PROGRAMMING CONNECTION EXAMPLE
This section describes the functions and operations of the flash serial programming
connection example.
APPENDIX
The appendixes include an I/O map, pin function index, interrupt vector index.

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Copyright© 2003 FUJITSU LIMITED All rights reserved
• The contents of this document are subject to change without notice. Customers are advised to consult with
FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device;
FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the
use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or
any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's
intellectual property right or other right by using such information. FUJITSU assumes no liability for any
infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export
under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will
be required for export of those products from Japan.

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CONTENTS
CHAPTER 1 OVERVIEW................................................................................................... 1
1.1 Features of the MB90895 series.......................................................................................................... 2
1.2 Product Lineup for MB90895 Series.................................................................................................... 4
1.3 Block Diagram of MB90895 Series...................................................................................................... 7
1.4 Pin Assignment.................................................................................................................................... 8
1.5 Package Dimensions ........................................................................................................................... 9
1.6 Pin Description................................................................................................................................... 10
1.7 I/O Circuit........................................................................................................................................... 13
CHAPTER 2 HANDLING DEVICES ................................................................................. 15
2.1 Precautions when Handling Devices ................................................................................................. 16
CHAPTER 3 CPU ............................................................................................................. 19
3.1 Memory Space................................................................................................................................... 20
3.1.1 Mapping of and Access to Memory Space ................................................................................... 22
3.1.2 Memory Map................................................................................................................................. 24
3.1.3 Addressing.................................................................................................................................... 25
3.1.4 Linear Addressing......................................................................................................................... 26
3.1.5 Bank Addressing .......................................................................................................................... 27
3.1.6 Allocation of Multi-byte Data in Memory ....................................................................................... 29
3.2 Dedicated Registers .......................................................................................................................... 31
3.2.1 Dedicated Registers and General-purpose Register .................................................................... 33
3.2.2 Accumulator (A)............................................................................................................................ 34
3.2.3 Stack Pointer (USP, SSP) ............................................................................................................ 37
3.2.4 Processor status (PS)................................................................................................................... 40
3.2.5 Program counter (PC) .................................................................................................................. 45
3.2.6 Direct page register (DPR) ........................................................................................................... 46
3.2.7 Bank Register (PCB, DTB, USB, SSB, and ADB) ........................................................................ 47
3.3 General-purpose Register ................................................................................................................. 48
3.4 Prefix Code ........................................................................................................................................ 50
3.4.1 Bank select prefix (PCB, DTB, ADB, and SPB)............................................................................ 51
3.4.2 Common register bank prefix (CMR)............................................................................................ 53
3.4.3 Flag change inhibit prefix (NCC) .................................................................................................. 54
3.4.4 Restrictions on Prefix Code .......................................................................................................... 55
3.5 Interrupt ............................................................................................................................................. 57
3.5.1 Interrupt Factor and Interrupt Vector ............................................................................................ 59
3.5.2 Interrupt Control Registers and Peripherals .................................................................................. 62
3.5.3 Interrupt Control Register (ICR00 to ICR15) ................................................................................ 64
3.5.4 Function of Interrupt Control Register .......................................................................................... 66
3.5.5 Hardware Interrupt........................................................................................................................ 69
3.5.6 Operation of Hardware Interrupt................................................................................................... 72
3.5.7 Procedure for Use of Hardware Interrupt ..................................................................................... 74
3.5.8 Multiple interrupts ......................................................................................................................... 75

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3.5.9 Software interrupt ......................................................................................................................... 77
3.5.10 Interrupts by extended intelligent I/O service (EI2OS).................................................................. 78
3.5.11 EI2OS descriptor (ISD) ................................................................................................................. 80
3.5.12 Each Register of EI2OS Descriptor (ISD) ..................................................................................... 82
3.5.13 Operation of EI2OS....................................................................................................................... 85
3.5.14 Procedure for Use of EI2OS ......................................................................................................... 86
3.5.15 EI2OS Processing Time................................................................................................................ 87
3.5.16 Exception Processing Interrupt..................................................................................................... 89
3.5.17 Time Required to Start Interrupt Processing ................................................................................ 90
3.5.18 Stack Operation for Interrupt Processing ..................................................................................... 92
3.5.19 Program Example of Interrupt Processing.................................................................................... 93
3.6 Reset ................................................................................................................................................. 96
3.6.1 Reset Factors and Oscillation Stabilization Wait Times ............................................................... 98
3.6.2 External Reset Pin ...................................................................................................................... 100
3.6.3 Reset Operation ......................................................................................................................... 101
3.6.4 Reset Factor Bit.......................................................................................................................... 103
3.6.5 State of Each Pin at Reset ......................................................................................................... 106
3.7 Clock................................................................................................................................................ 107
3.7.1 Block Diagram of Clock Generation Section .............................................................................. 110
3.7.2 Register in Clock Generation Section......................................................................................... 112
3.7.3 Clock select register (CKSCR) ................................................................................................... 113
3.7.4 PLL/subclock control register (PSCCR) ..................................................................................... 116
3.7.5 Clock Mode................................................................................................................................. 118
3.7.6 Oscillation Stabilization Wait Time ............................................................................................. 122
3.7.7 Connection of Oscillator and External Clock .............................................................................. 123
3.8 Low-power Consumption Mode ....................................................................................................... 124
3.8.1 Block Diagram of Low-power Consumption Circuit .................................................................... 127
3.8.2 Registers for Setting Low-power Consumption Modes .............................................................. 129
3.8.3 Low-power consumption mode control register (LPMCR).......................................................... 130
3.8.4 CPU Intermittent operation mode ............................................................................................... 133
3.8.5 Standby Mode ............................................................................................................................ 134
3.8.6 State Transition in Standby Mode .............................................................................................. 145
3.8.7 Pin State in Standby Mode, at Reset.......................................................................................... 146
3.8.8 Precautions when Using Low-power Consumption Mode .......................................................... 147
3.9 CPU Mode ....................................................................................................................................... 151
3.9.1 Mode Pins (MD2 to MD0) ................................................................................................................ 152
3.9.2 Mode Data ....................................................................................................................................... 154
3.9.3 Memory Access Mode ..................................................................................................................... 156
3.9.4 Operations for Selecting Memory Access Mode.............................................................................. 157
CHAPTER 4 I/O PORT ................................................................................................... 159
4.1 Overview of I/O Ports....................................................................................................................... 160
4.2 Registers of I/O Port and Assignment of Pins Serving as External Bus .......................................... 161
4.3 Port 1 ............................................................................................................................................... 162
4.3.1 Registers for Port 1 (PDR1, DDR1) ............................................................................................ 164
4.3.2 Operation of Port 1 ..................................................................................................................... 165
4.4 Port2 ................................................................................................................................................ 167

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4.4.1 Registers for Port 2 (PDR2, DDR2)............................................................................................ 170
4.4.2 Operation of Port 2 ..................................................................................................................... 171
4.5 Port 3............................................................................................................................................... 173
4.5.1 Registers for Port 3 (PDR3, DDR3)............................................................................................ 175
4.5.2 Operation of Port 3 ..................................................................................................................... 176
4.6 Port 4............................................................................................................................................... 178
4.6.1 Registers for Port 4 (PDR4, DDR4)............................................................................................ 180
4.6.2 Operation of Port 4 ..................................................................................................................... 181
4.7 Port 5............................................................................................................................................... 183
4.7.1 Registers for Port 5 (PDR5, DDR5, ADER)................................................................................ 186
4.7.2 Operation of Port 5 ..................................................................................................................... 188
4.8 Port input level select register.......................................................................................................... 190
CHAPTER 5 Timebase timer......................................................................................... 191
5.1 Overview of Timebase Timer........................................................................................................... 192
5.2 Block Diagram of Timebase Timer ..................................................................................................194
5.3 Configuration of Timebase Timer .................................................................................................... 196
5.3.1 Timebase timer control register (TBTC) ..................................................................................... 197
5.4 Interrupt of Timebase Timer ............................................................................................................ 199
5.5 Explanation of Operations of Timebase Timer Functions................................................................ 200
5.6 Precautions when Using Timebase Timer....................................................................................... 204
5.7 Program Example of Timebase Timer............................................................................................. 205
CHAPTER 6 Watchdog timer........................................................................................ 207
6.1 Overview of Watchdog Timer .......................................................................................................... 208
6.2 Configuration of Watchdog Timer.................................................................................................... 209
6.3 Watchdog Timer Registers.............................................................................................................. 211
6.3.1 Watchdog timer control register (WDTC) ................................................................................... 212
6.4 Explanation of Operations of Watchdog Timer Functions ............................................................... 214
6.5 Precautions when Using Watchdog Timer....................................................................................... 217
6.6 Program Examples of Watchdog Timer........................................................................................... 218
CHAPTER 7 16-bit I/O timer.......................................................................................... 219
7.1 Overview of 16-bit Input/Output Timer............................................................................................. 220
7.2 Block Diagram of 16-bit Input/Output Timer .................................................................................... 221
7.2.1 Block Diagram of 16-bit Free-run Timer ..................................................................................... 222
7.2.2 Block Diagram of Input Capture .................................................................................................224
7.3 Configuration of 16-bit Input/Output Timer ...................................................................................... 226
7.3.1 Timer counter control status register (TCCS)............................................................................. 229
7.3.2 Timer counter data register (TCDT) ........................................................................................... 231
7.3.3 Input capture control status registers (ICS01, ICS23)................................................................ 233
7.3.4 Input capture data registers (IPCP0 to IPCP3)........................................................................... 235
7.4 Interrupts of 16-bit Input/Output Timer............................................................................................. 236
7.5 Explanation of Operation of 16-bit Free-run Timer.......................................................................... 237
7.6 Explanation of Operation of Input Capture ...................................................................................... 239
7.7 Precautions when Using 16-bit Input/Output Timer......................................................................... 242
7.8 Program Example of 16-bit Input/Output Timer............................................................................... 243

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CHAPTER 8 16-bit reload timer.................................................................................... 245
8.1 Overview of 16-bit Reload Timer ..................................................................................................... 246
8.2 Block Diagram of 16-bit Reload Timer............................................................................................. 249
8.3 Configuration of 16-bit Reload Timer............................................................................................... 252
8.3.1 Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)............................................ 255
8.3.2 Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)............................................ 257
8.3.3 16-bit Timer Registers (TMR0, TMR1) ....................................................................................... 259
8.3.4 16-bit Reload Registers (TMRLR0, TMRLR1) ............................................................................ 260
8.4 Interrupts of 16-bit Reload Timer ..................................................................................................... 261
8.5 Explanation of Operation of 16-bit Reload Timer............................................................................. 262
8.5.1 Operation in Internal Clock Mode ............................................................................................... 264
8.5.2 Operation in Event Count Mode ................................................................................................. 269
8.6 Precautions when Using 16-bit Reload Timer ................................................................................. 272
8.7 Program Example of 16-bit Reload Timer ....................................................................................... 273
CHAPTER 9 Watch timer .............................................................................................. 277
9.1 Overview of Watch Timer ................................................................................................................ 278
9.2 Block Diagram of Watch Timer ........................................................................................................ 280
9.3 Configuration of Watch Timer .......................................................................................................... 282
9.3.1 Watch timer control register (WTC) ............................................................................................ 283
9.4 Watch Timer Interrupt ...................................................................................................................... 285
9.5 Explanation of Operation of Watch Timer........................................................................................ 286
9.6 Program Example of Watch Timer................................................................................................... 288
CHAPTER 10 8/16-bit PPG timer .................................................................................... 289
10.1 Overview of 8-/16-bit PPG Timer..................................................................................................... 290
10.2 Block Diagram of 8-/16-bit PPG Timer ............................................................................................ 293
10.2.1 Block Diagram for 8-/16-bit PPG Timer 0 ................................................................................... 294
10.2.2 Block Diagram of 8-/16-bit PPG Timer 1 .................................................................................... 296
10.3 Configuration of 8-/16-bit PPG Timer .............................................................................................. 299
10.3.1 PPG0 Operation Mode Control Register (PPGC0)..................................................................... 301
10.3.2 PPG1 Operation Mode Control Register (PPGC1)..................................................................... 303
10.3.3 PPG0/1 count clock select register (PPG01).............................................................................. 305
10.3.4 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)........................................................... 307
10.4 Interrupts of 8-/16-bit PPG Timer..................................................................................................... 308
10.5 Explanation of Operation of 8-/16-bit PPG Timer ............................................................................ 310
10.5.1 8-bit PPG output 2-channel independent operation mode ......................................................... 311
10.5.2 16-bit PPG output mode ............................................................................................................. 313
10.5.3 8 + 8-bit PPG output mode ......................................................................................................... 316
10.6 Precautions when Using 8-/16-bit PPG Timer ................................................................................. 319
CHAPTER 11 Delayed interrupt generation module .................................................... 321
11.1 Overview of Delayed Interrupt Generation Module.......................................................................... 322
11.2 Block Diagram of Delayed Interrupt Generation Module ................................................................. 323
11.3 Configuration of Delayed Interrupt Generation Module ................................................................... 324
11.3.1 Delayed interrupt request generate/cancel register (DIRR) ....................................................... 325
11.4 Explanation of Operation of Delayed Interrupt Generation Module ................................................. 326

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11.5 Precautions when Using Delayed Interrupt Generation Module...................................................... 327
11.6 Program Example of Delayed Interrupt Generation Module............................................................ 328
CHAPTER 12 DTP/external interrupt ............................................................................. 329
12.1 Overview of DTP/External Interrupt ................................................................................................. 330
12.2 Block Diagram of DTP/External Interrupt......................................................................................... 331
12.3 Configuration of DTP/External Interrupt........................................................................................... 333
12.3.1 DTP/external interrupt factor register (EIRR) ............................................................................. 334
12.3.2 DTP/external interrupt enable register (ENIR)............................................................................ 335
12.3.3 Detection Level Setting Register (ELVR) (High)......................................................................... 336
12.3.4 Detection Level Setting Register (ELVR) (Low) ......................................................................... 337
12.4 Explanation of Operation of DTP/External Interrupt ........................................................................ 338
12.4.1 External Interrupt Function ......................................................................................................... 341
12.4.2 DTP Function.............................................................................................................................. 342
12.5 Precautions when Using DTP/External Interrupt ............................................................................. 343
12.6 Program Example of DTP/External Interrupt Function .................................................................... 345
CHAPTER 13 8/10-bit A/D converter.............................................................................. 349
13.1 Overview of 8-/10-bit A/D Converter................................................................................................ 350
13.2 Block Diagram of 8-/10-bit A/D Converter ....................................................................................... 351
13.3 Configuration of 8-/10-bit A/D Converter ......................................................................................... 354
13.3.1 A/D Control Status Register (High) (ADCS: H)........................................................................... 356
13.3.2 A/D Control Status Register (Low) (ADCS: L) ............................................................................ 359
13.3.3 A/D Data Register (High) (ADCR: H).......................................................................................... 362
13.3.4 A/D Data Register (Low) (ADCR: L) ........................................................................................... 364
13.3.5 Analog input enable register (ADER) ......................................................................................... 365
13.4 Interrupt of 8-/10-bit A/D Converter ................................................................................................. 367
13.5 Explanation of Operation of 8-/10-bit A/D Converter ....................................................................... 368
13.5.1 Single-shot conversion mode ..................................................................................................... 369
13.5.2 Continuous conversion mode ..................................................................................................... 371
13.5.3 Pause-conversion mode ............................................................................................................. 373
13.5.4 Conversion Using EI2OS Function ............................................................................................. 375
13.5.5 A/D-converted Data Protection Function .................................................................................... 376
13.6 Precautions when Using 8-/10-bit A/D Converter ............................................................................ 379
CHAPTER 14 UART0 ....................................................................................................... 381
14.1 Overview of UART0 ......................................................................................................................... 382
14.2 Block Diagram of UART0................................................................................................................. 384
14.3 Configuration of UART0................................................................................................................... 387
14.3.1 Serial control register 0 (SCR0).................................................................................................. 389
14.3.2 Serial mode register 0 (SMR0) ................................................................................................... 391
14.3.3 Serial status register 0 (SSR0) ................................................................................................... 393
14.3.4 Serial Input Data Register 0 (SIDR0) and Serial Output Data Register 0 (SODR0)................... 395
14.3.5 Communication Prescaler Control Register 0 (CDCR0)............................................................. 397
14.3.6 Serial edge select register 0 (SES0) .......................................................................................... 398
14.4 Interrupt of UART0........................................................................................................................... 399
14.4.1 Generation of Receive Interrupt and Timing of Flag Set ............................................................ 401

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14.4.2 Generation of Transmit Interrupt and Timing of Flag Set ........................................................... 403
14.5 UART0 baud rate............................................................................................................................. 405
14.5.1 Baud rate by dedicated baud rate generator .............................................................................. 407
14.5.2 Baud Rate by Internal Timer (16-bit Reload Timer).................................................................... 410
14.5.3 Baud rate by external clock ........................................................................................................ 412
14.6 Explanation of Operation of UART0 ................................................................................................ 413
14.6.1 Operation in asynchronous mode (operation mode 0 or 1) ........................................................ 415
14.6.2 Operation at clock synchronous mode (operating mode 2) ........................................................ 419
14.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) ........................................... 422
14.6.4 Master/slave type communication function (multi processor mode) ........................................... 424
14.7 Precautions when using UART0...................................................................................................... 427
CHAPTER 15 UART1 ....................................................................................................... 429
15.1 Overview of UART1 ......................................................................................................................... 430
15.2 Block Diagram of UART1................................................................................................................. 432
15.3 Configuration of UART1................................................................................................................... 435
15.3.1 Serial control register 1 (SCR1).................................................................................................. 437
15.3.2 Serial mode register 1 (SMR1) ................................................................................................... 439
15.3.3 Serial status register 1 (SSR1) ................................................................................................... 441
15.3.4 Serial Input Data Register 1 (SIDR1) and Serial Output Data Register 1 (SODR1) ................... 444
15.3.5 Communication Prescaler Control Register 1 (CDCR1)............................................................. 446
15.4 Interrupt of UART1........................................................................................................................... 448
15.4.1 Generation of Receive Interrupt and Timing of Flag Set ............................................................ 450
15.4.2 Generation of Transmit Interrupt and Timing of Flag Set ........................................................... 452
15.5 UART1 Baud Rate ........................................................................................................................... 453
15.5.1 Baud rate by dedicated baud rate generator .............................................................................. 455
15.5.2 Baud Rate by Internal Timer (16-bit Reload Timer) .................................................................... 458
15.5.3 Baud rate by external clock ........................................................................................................ 460
15.6 Explanation of Operation of UART1 ................................................................................................ 461
15.6.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) ....................................................... 463
15.6.2 Operation in Clock Synchronous Mode (Operation Mode 2) ...................................................... 467
15.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) ........................................... 469
15.6.4 Master/Slave Type Communication Function (Multiprocessor Mode) ........................................ 471
15.7 Precautions when Using UART1 ..................................................................................................... 474
15.8 Program Example for UART1 .......................................................................................................... 475
CHAPTER 16 CAN controller .......................................................................................... 477
16.1 Overview of CAN Controller ............................................................................................................. 478
16.2 Block Diagram of CAN Controller .................................................................................................... 479
16.3 Configuration of CAN Controller ...................................................................................................... 482
16.3.1 Control Status Register (High) (CSR: H) .................................................................................... 486
16.3.2 Control Status Register (Low) (CSR: L) ..................................................................................... 488
16.3.3 Last event indication register (LEIR) .......................................................................................... 491
16.3.4 Receive/Transmit Error Counter (RTEC) ....................................................................................493
16.3.5 Bit timing register (BTR) ............................................................................................................. 495
16.3.6 Message buffer validating register (BVALR) .............................................................................. 499
16.3.7 IDE register (IDER) ..................................................................................................................... 501

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16.3.8 Transmit request register (TREQR) ............................................................................................ 503
16.3.9 Transmit RTR register (TRTRR) ................................................................................................. 505
16.3.10 Remote frame receive waiting register (RFWTR) ....................................................................... 507
16.3.11 Transmission cancel register (TCANR) ...................................................................................... 509
16.3.12 Transmit complete register (TCR) .............................................................................................. 511
16.3.13 Transmit complete interrupt enable register (TIER) ................................................................... 513
16.3.14 Receive complete register (RCR) ............................................................................................... 515
16.3.15 Receive RTR register (RRTRR) ................................................................................................. 517
16.3.16 Receive overrun register (ROVRR) ............................................................................................ 519
16.3.17 Receive complete interrupt enable register (RIER) .................................................................... 521
16.3.18 Acceptance mask select register (AMSR) ..................................................................................523
16.3.19 Acceptance Mask Select Register (AMR) .................................................................................. 525
16.3.20 Message Buffers ......................................................................................................................... 527
16.3.21 ID Register (IDRx, x = 7 to 0) ..................................................................................................... 528
16.3.22 DLC Register (DLCR) ................................................................................................................. 531
16.3.23 Data Register (DTR) ................................................................................................................... 532
16.4 Interrupts of CAN Controller ............................................................................................................ 533
16.5 Explanation of Operation of CAN Controller .................................................................................... 535
16.5.1 Transmission .............................................................................................................................. 536
16.5.2 Reception ................................................................................................................................... 539
16.5.3 Procedures for Transmitting and Receiving ............................................................................... 543
16.5.4 Setting Multiple Message Reception .......................................................................................... 550
16.6 Precautions when Using CAN Controller ......................................................................................... 552
16.7 Program Example of CAN Controller ............................................................................................... 553
CHAPTER 17 Address Match Detecting Function ........................................................ 555
17.1 Overview of Address Match Detection Function .............................................................................. 556
17.2 Block Diagram of Address Match Detection Function ..................................................................... 557
17.3 Configuration of Address Match Detection Function ....................................................................... 558
17.3.1 Address detection control register (PACSR) .............................................................................. 559
17.3.2 Detect address setting registers (PADR0, PADR1) .................................................................... 561
17.4 Explanation of Operation of Address Match Detection Function ..................................................... 563
17.4.1 Example of using Address Match Detection Function ................................................................ 564
17.5 Program Example of Address Match Detection Function ................................................................ 569
CHAPTER 18 ROM Mirroring Function Selection Module ........................................... 571
18.1 Overview of ROM Mirroring Function Selection Module.................................................................. 572
18.2 ROM Mirroring Function Selection Register (ROMM) ..................................................................... 574
CHAPTER 19 512 KBIT FLASH MEMORY .................................................................... 575
19.1 Overview of 512 Kbit Flash Memory ............................................................................................... 576
19.2 Registers and Sector/Bank Configuration of Flash Memory ........................................................... 577
19.3 Flash Memory Control Status Register (FMCS) ............................................................................. 579
19.4 Flash Memory Write Control Register (FWR0/1) ............................................................................ 582
19.5 How to Start Automatic Algorithm of Flash Memory ....................................................................... 586
19.6 Reset Vector Addresses in Flash Memory ..................................................................................... 589
19.7 Check the Execution State of Automatic Algorithm ........................................................................ 590

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19.7.1 Data Polling Flag (DQ7) ............................................................................................................ 592
19.7.2 Toggle Bit Flag (DQ6) ................................................................................................................ 594
19.7.3 Timing Limit Over Flag (DQ5) .................................................................................................... 595
19.7.4 Sector Erase Timer Flag (DQ3) ................................................................................................. 596
19.7.5 Toggle Bit 2 Flag (DQ2) ............................................................................................................ 597
19.8 Details of Programming/Erasing Flash Memory ............................................................................. 599
19.8.1 Read/Reset State in Flash Memory ........................................................................................... 600
19.8.2 Data programming to flash memory .......................................................................................... 601
19.8.3 Data Erase from Flash Memory (Chip Erase) ........................................................................... 603
19.8.4 Erasing Any Data in Flash Memory (Sector Erasing) ............................................................... 604
19.8.5 Sector Erase Suspension .......................................................................................................... 606
19.8.6 Sector Erase Resumption .......................................................................................................... 607
CHAPTER 20 DUAL OPERATION FLASH ..................................................................... 609
20.1 Overview of Dual Operation Flash .................................................................................................. 610
20.2 Register for Dual Operation Flash .................................................................................................. 611
20.3 Operation of Dual Operation Flash ................................................................................................. 613
APPENDIX .......................................................................................................................... 615
APPENDIX A Instructions ............................................................................................................................ 616
A.1 Instruction Types............................................................................................................................... 617
A.2 Addressing ........................................................................................................................................ 618
A.3 Direct Addressing.............................................................................................................................. 620
A.4 Indirect Addressing ........................................................................................................................... 627
A.5 Execution Cycle Count...................................................................................................................... 634
A.6 Effective Address Field ..................................................................................................................... 636
A.7 How to Read the Instruction List ....................................................................................................... 638
A.8 F2MC-16LX Instruction List............................................................................................................... 641
A.9 Instruction Map ................................................................................................................................. 655
APPENDIX B Register Index ....................................................................................................................... 677
APPENDIX C Pin Function Index ................................................................................................................ 687
APPENDIX D Interrupt Vector Index............................................................................................................. 689

1
CHAPTER 1
OVERVIEW
This chapter describes the features and basic
specifications of MB90895 series.
1.1 Features of the MB90895 series
1.2 Product Lineup for MB90895 Series
1.3 Block Diagram of MB90895 Series
1.4 Pin Assignment
1.5 Package Dimensions
1.6 Pin Description
1.7 I/O Circuit

2
CHAPTER 1 OVERVIEW
1.1 Features of the MB90895 series
MB90895 series devices are 16-bit micro general-purpose controllers designed for
applications which need high-speed real-time processing. The devices of this series are
high-performance 16-bit CPU micro controllers em-ploying of the dual operation flash
memory and CAN controller on LQFP-48 small package.
The instruction system is based on the architecture of the F2MC family and provides
additional high-level language instructions, extended addressing modes, enhanced
multiply/divide instructions, and enriched bit processing instructions. A 32-bit
accumulator enables long-word data (32 bits) processing.
■Features of the MB90895 series
●Clock
• Built-in PLL clock multiplying circuit
• Machine clock (PLL clock) selectable from 1/2 frequency of oscillation clock or 1 to 4 multiples of
oscillation clock (4 MHz to 16 MHz when oscillation clock is 4 MHz)
• Sub clock operation (8.192 kHz) (MB90F897)
• Minimum instruction execution time: 62.5 ns (4-MHz oscillation clock, 4-multiplied PLL clock)
●16-MB CPU memory space
• Internal 24-bit addressing
●Instruction system optimized for controllers
• Various data types (bit, byte, word, long word)
• 23 types of addressing modes
• Enhanced signed instructions of multiplication/division and RETI
• High-accuracy operations enhanced by 32-bit accumulator
●Instruction system for high-level language (C language)/multitask
• System stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
●Higher execution speed
• 4-byte instruction queue
●Powerful interrupt function
• Powerful interrupt function with 8 levels and 34 factors
●CPU-independent automatic data transfer function
• Extended intelligent I/O service (EI2OS): Maximum 16 channels