Siemens SMP16-SFT251 Parts list manual

SICOMP Industrial Microcomputer
(4)J31069-D2090-U001-A1-7618
Technical Description
Order number: 6AR1930-4AA06-2AA0 April 2003
SMP16-SFT251
Order number: 6AR1304-0EA00-0AA0
Counter board with two 32-bit incremental/pulse counters

SMP16-SFT251
©Siemens AG 2003, All Rights Reserved
2(4)J31069-D2090-U001-A1-7618
Product History of the Technical Description
Revision 1) Record of Changes Date
A0 First edition 03/00
A1 Control Register 1 and 2, Chapter 6.4.3 and 6.4.4 04/03
1) Corresponds to the 4th block of digits of the drawing number in the footer
Explanation of Notation
* An asterisk behind the signal name indicates a low-active signal (e.g., IOR*).
/ A slash between two signal names separates two level-dependent functions of one signal.
Example: C/D* means Command for high level and Data for low level.
x Bits marked with an x in the register descriptions are irrelevant.
– Connections indicated with a dash in a connector assignment table are reserved (i.e., bus or
I/O interface).
Signal Special signals not included in these specifications are indicated in bold print in the signal
assignment tables and then explained (e.g., AMSEOP).
Notes:
SICOMP® is a registered trademark of Siemens AG.
IBM AT® and IBM PC® are registered trademarks of the International Business Machines Corp.
INTEL® is a registered trademark of the INTEL Corp.
MS-DOS®, Windows® and Windows NT® are registered trademarks of Microsoft.
All other designations used in this documentation may be trademarks whose use by third parties for their own purposes may
violate the rights of the owner.
Passing on and reproduction of this document, as well as utilization and communication of its contents is prohibited unless
expressly authorized. Offenders will be liable for damages. All rights reserved, particularly in the event a patent is granted or a
utility model is registered.
No responsibility is assumed for circuits, descriptions and tables contained in this document concerning freedom from rights of
third parties. Information in the technical descriptions specifies products but does not guarantee characteristics. The product
described in this documentation may require licensing. Questions should be directed to your local Siemens office.
Availability and technical modifications subject to change without prior notice. ES43/Kt/WW8.0/VS5.0/A4

SMP16-SFT251
©Siemens AG 2003, All Rights Reserved
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Safety Notes for SICOMP Boards
ESD protection measures
Caution
When handling boards and other components carrying this symbol, always adhere to
ESD protection guidelines (Electrostatic Sensitive Devices).
• Never touch the boards unless required work makes this absolutely necessary.
• When working with the boards, use a conductive and grounded work surface.
• Wear a grounding bracelet.
• Never touch the pins, connections or printed circuits of the boards.
• Never permit the boards or components to be touched by chargeable objects (e.g., synthetic
materials).
• Keep the boards or components at least 10 cm away from CRT units and television sets.
• Leave the boards in their special packaging until they are needed. When registering boards, etc.
do not remove the boards from their packaging or touch them.
• Boards may only be installed or removed when the voltage is off.
Wiring of Bus Backplanes
System-related signal wiring on SICOMP board systems is performed with wrap connections. The
power supply cables are bundled together with cable binders. These cables are equipped with plug-in
or screw connections.
Caution:
All signal wiring (the interrupt signal lines in particular) must be of the appropriate design and kept as
short as possible. When longer interrupt signal lines cannot be avoided, twisted pair wiring must be
used.
Related SICOMP SMP16 Literature
For more information on installing and handling SICOMP boards, see "SICOMP IMC system manual".

SMP16-SFT251
©Siemens AG 2003, All Rights Reserved
4(4)J31069-D2090-U001-A1-7618
Table of Contents
1 Initial Startup 7
1.1 Preparing for Software Configuration 7
1.2 Wiring the I/O 9
2 Features 10
2.1 Characteristics 10
2.2 Front LEDs 11
2.3 Operational Values 12
2.4 Physical Characteristics of the Encoder Signals 13
2.5 Time Requirements for the Input Signals 13
2.5.1 Encoder Signals 13
2.5.2 Frequency and Pulse Width Measurement 14
2.5.3 Special Signals 14
2.6 Time Relationships of the 24 V Interface 15
2.7 Ambient Conditions 16
2.8 Recommended Accessories 16
3 Interfaces 17
3.1 Overview of the Interfaces 17
3.2 Pin Connector X2 to SMP16 Bus 18
3.2.1 Signals for the Daisy Chain 18
3.2.2 Other Special Signals 19
3.3 I/O Connectors X3 and X4 20
3.4 Interface Switches S1 and S2 21
4 Configuration with Software 22
5 Compatibility with SMP-E251 24
6 Programming the Board 25
6.1 Register Overview 25
6.2 Reset Reactions 28
6.3 Function Description 29
6.3.1 Reading the Counter Status 29
6.3.2 Loading the Counters 29
6.3.3 Position Acquisition via Shaft Encoder Edge Evaluation 30
6.3.4 Position Acquisition with Hardware Support 32
6.3.5 Position Acquisition without Hardware Support 33
6.3.6 Frequency and Pulse Width Measurement 35
6.3.7 Overview of the Commands 38

SMP16-SFT251
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6.3.8 Extra Inputs ZS00 to ZS30 (Counting Channel 0) or ZS01 to ZS31 (Counting
Channel 1) 40
6.3.9 The Universal Registers 40
6.3.10 The Clear Functions 41
6.3.11 The Hysteresis Functions 42
6.3.12 Switching the Two Counting Channels in Parallel 43
6.3.13 Interrupts 43
6.4 Description of the Registers 44
6.4.1 Mode Registers, Channel 0 and Channel 1 44
6.4.2 Control Register 0 45
6.4.3 Control Register 1 (16-Bit Register, Addresses x and x+1) 46
6.4.4 Control Register 2 (16-Bit Register, Addresses x+2 and x+3) 47
6.4.5 Interrupt Mask (16-Bit Register, Addresses x+4 and x+5) 49
6.4.6 Interrupt Register, Channel 0 and Channel 1 50
6.4.7 Status Register 0 51
6.4.8 Status Register 1 52
6.4.9 Status Register 2 (16-Bit Register, Addresses x+6 and x+7) 53
6.4.10 Clear Register (16-Bit Register, Addresses x+6 and x+7) 55
6.5 Times 57
6.5.1 Read/Write Accesses 57
6.5.2 Board Commands 57
7 Sample Programs 58
7.1 Position Acquisition with Hardware Support (BG_Mode = "0") 58
7.2 Position Acquisition without Hardware Support (BG_Mode = "1") 60
7.3 Frequency and Pulse Width Measurement without Using the Zero-Marking-
Pulse Input 61

SMP16-SFT251
©Siemens AG 2003, All Rights Reserved
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SMP16-SFT251 Initial Startup
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(4)J31069-D2090-U001-A1-7618 7
1 Initial Startup
The primary steps involved in the initial startup of the board are listed below.
1. Software configuration. See chapters 1.1 and 4 for more information.
Attention:
Chip select channel 0 must be enabled for the board.The other channels can be enabled or
disabled depending on the particular application. The ASBIC channel must be disabled.
2. Wiring I/O devices. See chapter 1.2 or 2.8 for more information.
1.1 Preparing for Software Configuration
The configuration of the board with the SMP16-AKO auto configuration software (see chapter 2.8) can
be performed directly in the target system or in a separate generation system. In addition, the
configuration can be performed in a separate system, but the board can still be configured in the target
system.
In all cases, the board must be installed in an SMP16 bus system with daisy chain connection at the
time of programming.
Configuration in the target system
Requirements on the Target System
Required hardware • SICOMP IMC AT CPU
• SMP16 bus backplane with daisy chain
Required software • Windows 95
• SMP16-AKO V2.0
Configuration in the target system, generation of the configuration in separate
system
Requirements on the Target System Requirements on the Generation
System
Required hardware 1) • SICOMP IMC AT CPU
• SMP16 bus backplane with daisy
chain
• PC-AT (e.g., workplace computer or
laptop)
Required software • RMOS or MS-DOS
• AKO start program
• Windows 95 or Windows NT
• SMP16-AKO V2.0
1) In addition, there must be a way to transfer the generated configuration file (i.e., STARTUP.SKD) to the
target system. Some examples are listed below.
- Serial connection via zero modem cable (is supported by AKO start program)
- Floppy disk drives on both systems
- LAN connection

Initial Startup SMP16-SFT251
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Configuration in a separate generation system
The board is installed in the generation system for configuration and then returned to the target
system afterwards.
Requirements on the Generation System
Required hardware • SICOMP IMC AT CPU
• SMP16 bus backplane with daisy chain
Required software • Windows 95
• SMP16-AKO V2.0
Daisy chaining for configuration via software
With SMP16-SYS403 bus backplanes with 5 or more slots, the daisy change connection is already
implemented electronically.
With the other bus backplanes, the slots of the software-configurable boards must be wired as shown
below.
cba
1
32 Board n
cba
1
Board 3
cba
1
Board 2
cba
1
Board 1
A
CEN (b11)
A
CDONE (b13)
32 32 32
Figure 1.1 Daisy chaining on the SMP16 bus backplane for configuration via software
The ACEN input of the first software configurable board in the chain of configuration remains open as
does the ACDONE output of the last board. All other ACDONE outputs must be connected with the
ACEN input of the next board. See chapter 3.2.1.

SMP16-SFT251 Initial Startup
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1.2 Wiring the I/O
The differential control lines must be twisted in pairs (see chap. 3.3). The single-ended control lines
must be twisted with the related ground.
The shield must be applied (for HF) to both the board and the addressed I/O. To prevent equalizing
currents on the shield, an equipotential bonding conductor should be installed parallel to the signal
line.
Never install your control lines near strong interference (e.g., motors, relays, high-voltage or power
lines, thyristor controllers, power inverters and transmitters).
Also adhere to the information on electromagnetic compatibility contained in the SICOMP IMC system
manual under the chapter on ambient conditions.

Features SMP16-SFT251
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2 Features
2.1 Characteristics
The SMP16-SFT251 is a counter board with two 32-bit counters. Its software is compatible with the
SMP-E251. It should be used instead of the SMP-E251.
The board has the following characteristics.
General
• Two 15-pin, sub D socket strips for connection of the I/O
• Free-convection ventilation
• EEPROM for identification and parameterization of the board
• Automatic configuration with "auto configuration" (see chap. 4)
• 5 V encoder power drawn from bus voltage (via fuse)
Functions per channel
• Position acquisition with connection of a two-track incremental encoder (single, double or
quadruple edge evaluation, max. track frequency of 2 MHz)
• One zero-marking-pulse latch register and 3 extra latch registers (can be triggered by digital
inputs) one of which can also be used as a comparator register
• Three digital, single-ended inputs (24 V) for triggering the extra latch registers or for generating
interrupts
• One digital, single-ended input (24 V) for resetting the counter or for triggering interrupts
• A comparator register can be used to trigger an alarm (interrupt, status bit) when a certain
counter state is reached and/or to reset the counter.
• Both the shaft encoder signals and the digital inputs of channel 0 can be assigned to channel 1.
This makes it possible to run both counters parallel to each other.
• Frequency or pulse width measurement with frequencies up to 4 MHz. Either level or edge-
control can be used to start the counter.
• The counting signals (A track and B track) and the zero marking pulse (N track) can be set with
DIP switches for either 24 V technology or for RS 422.
• The operating modes can be set separately for each channel.
The following block circuit diagram shows the logical organization of the board.

SMP16-SFT251 Features
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Universal register controller
Signal conditioning
Edge evaluation
Universal
register 0 Universal
register 1 Universal register 2
Counter controller
Hardware support,
counter oper. modes,
edge evaluation,
clear control,
load control,
and so on
SMP16-Bus
Address decoding
Generation of the CS signals
and the read/write commands
for the individual registers,
generation of the
command signals
The figure shows only one counting channel.
The diagram for the second channel is identical.
For the sake of clarity, only the most important signals
and buses are included.
The letter "n" following some of the signals stands
for the channel number: n=0 for channel 0 and n=1 for channel 1.
Interrupt
controller
Status register 0 - 2
I/O data bus(0:15)
Address bus
(0:5)
Command
signals
CS signals
ZS0n
ZS1n
ZS2n
ZS3n
A track
B track
N track
ZS0n
ZS1n
ZS2n
ZS3n
A
B
UREF
CNT
U/D*
32
0:15
0:15
0:15
16:31
16:31
16:31 0:15
16:31
Address bus
(0:19)
Command
signals
Data bus
(0:15)
ZS3n
CR1n
CR1n
(for channels 0 and 1)
(for counting channels
0 and 1)
(for channels 0 and 1)
ZS0n
ZS1n
ZS2n
ZS3n
Overflow
CBn
Overflow CBn
IRQ 0..5
CR1n
0:15
16:31
Comparator 1
Signal conditioning
32 bit
counter
Controller register 0 - 2 Bus interface
(ASBIC)
Figure 2.1 Block circuit diagram of the SMP16-SFT251
2.2 Front LEDs
The two front LEDs (L1 and L2) show the direction of rotation of the shaft encoder for channel 0 or
channel 1 during position acquisition.
These LEDs are irrelevant for "frequency and pulse width measurement" mode.
Channel 0:
Direction of Rotation Status - LED L1
Up On
Down Off
Channel 1:
Direction of Rotation Status - LED L2
Up On
Down Off
X3
X4
L1 L2

Features SMP16-SFT251
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2.3 Operational Values
System portion
Voltage supply (from SMP16 bus) +5 V ±5%
Current consumption with nominal voltage (without encoder power) Max. of 400 mA
Counter inputs
Number of channels 2
Counter size 32 bits
Interfaces: encoder inputs A, B, and N (zero marking pulse) 24 V technology, opto-decoupled
(single-ended or differential)
or RS 422
Operational values with 24 V technology:
Differential ±13 V to ±30 V
Differential, max. ratings ±34 V
Single-ended, low level –3 V to +5 V
Single-ended, high level +13 V to +30 V
Single-ended, max. ratings ±34 V
Input current with 24 V technology (Uin = 24 V)
(U
in = 30 V) 11.4 mA (typ.)
15.1 mA (max.)
See RS 422 specifications for operational values with RS 422.
Input frequency for incremental encoders: 2 MHz (max.)
Input frequency with frequency/gate time measurement 4 MHz (max.)
Extra inputs
Number 4 per channel
Interfaces 24 V technology
Input voltage, low level –3 V to +5 V
Input voltage, high level +13 V to +30 V
Input voltage, max. ratings ±34 V
Input current with high level (Uin = 24 V)
(U
in = 30 V) 11.4 mA (typ.)
15.1 mA (max.)
5 V encoder power
Encoder voltage 5 V (typ.)
Depends on the power supply of the
SMP16 system and the voltage drops on
the board (typically 0.2 V)
Total current 720 mA (max.)
Short-circuit immunity Yes (with SMD safety fuse)
Notes on 24 V interface
The 24 V interface offers extra immunity to interference. The physical characteristics of this interface
(high voltage swings with currents > 10 mA) restrict its use with high-speed applications.
For this reason, encoders with the RS 422 interface should be used for encoder applications with track
frequencies > 500 kHz. Otherwise, the encoder signals might not be transferred accurately which
would cause counting errors in the system.

SMP16-SFT251 Features
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2.4 Physical Characteristics of the Encoder Signals
Encoders can be connected to the board with an RS 422 or 24 V interface. The desired physical
characteristics must be selected with the two DIP switches (S1 and S2) on the board. See
chapter 3.4.
Caution
Since setting the wrong interface may destroy the board, make sure that all DIP
switches required for selection of the interface are set correctly.
2.5 Time Requirements for the Input Signals
2.5.1 Encoder Signals
The two track signals (A and B) of the encoder must be displaced by 90°to each other.
A track
B track
N track
(UREF)
t1
t3
t2
t1
t1 t1
t2
Figure 2.2 Time relationships of the encoder signals
t1 A edge to B edge 125 nsec (min.)
t2 Pulse width, A/B track 250 nsec (min.)
t3 Pulse width, N track 125 nsec (min.)

Features SMP16-SFT251
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2.5.2 Frequency and Pulse Width Measurement
With frequency and pulse width measurement, the reference gate signal must be at least twice as long
as the maximum expected cycle duration of the frequency to be measured.
E
xternal frequency
(input A)
Gate signal
(input B) t6
t7 t7
Figure 2.3 Time relationships with frequency and pulse width measurement
t7 Clock pulse high/low time 125 nsec (min.)
t6 Gate time when the external clock pulse is used 2 x t7 (min.)
t6 Gate time when the internal clock pulses are used t8 (min.)
t8 Cycle time of the internal clock pulses:
1.25 MHz
2.5 MHz
2.0 MHz
4.0 MHz
800 nsec
400 nsec
500 nsec
250 nsec
2.5.3 Special Signals
ZS00, ZS10, ZS20, ZS30
ZS01, ZS11, ZS21, ZS31 t4
t5
Figure 2.4 Time relationships of the special signals
t4 High edge to high edge 400 nsec (min.)
t5 Pulse width 250 nsec (min.)

SMP16-SFT251 Features
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2.6 Time Relationships of the 24 V Interface
The following signal runtimes apply to the 24 V interface.
Signal,
external
Signal,
internal
t9 t10
Figure 2.5 Signal runtimes for the 24 V interface
t9 Time from Low →High 500 nsec (typ.)
t10 Time from High →Low 400 nsec (typ.)
These signal runtimes apply to 24 V outputs with push-pull clock pulse technology. Other runtimes
may apply when other technologies are used.

Features SMP16-SFT251
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2.7 Ambient Conditions
Operation Transportation and Storage
Temperature 0°C to 55°C –40°C to +70°C
Relative humidity (RH) 10% to 90% 10% to 90%
Permissible air pressure 450 hPa to 1100 hPa
Permissible temperature fluctuation 10°C/30 min. (without condensation) or 0.5°C/min.
Vibrations
in acc. w. IEC 68-2-6 Test FC,
20 cycles in 3 axes,
approx. 11 min. per cycle
10 Hz to 61 Hz: 0.2 mm
amplitude
61 Hz to 500 Hz: 2 g
5 Hz to 8 Hz: 7.5 mm
amplitude
8 Hz to 500 Hz: 1 g
Shock IEC 68-2-27 Test E/A
3 times per axis
2 directions per axis
total of 18 impacts
15 g/11 msec
IEC 68-2-29
per 1000 impacts at 6 levels
25 g/6 msec
2.8 Recommended Accessories
SMP16-AKO Auto-configuration software for MS-DOS and Windows for setting the SMP16
bus interface
Order number: 6AR1400-0FA10-3AA0
The product includes online help with a detailed description of the function and
handling of the configuration software.
The files (SFT251.BGB and SFT251.BGT) which are required to set the board
are available on the Internet under:
http://www.ad.siemens.de/sicomp/html_76/hotline.htm
SMD safety fuse Order number: R451.750 (the Littlefuse company)
Figure 3.1 shows where the two fuses are located on the board.

SMP16-SFT251 Interfaces
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(4)J31069-D2090-U001-A1-7618 17
3 Interfaces
3.1 Overview of the Interfaces
Pin Design Use
X1 Socket strip, 20-pin Reserved
X2 Multi-point terminal strip, 96-pin SMP16 bus interface
X3 Sub D socket, 15-pin Input, counting channel 0
X4 Sub D socket, 15-pin Input, counting channel 1
S1 DIP switch, 8-pin Switch, 24 V technology ↔RS 422, channel 0
S2 DIP switch, 8-pin Switch, 24 V technology ↔RS 422, channel 1
X3
X
4
X2
S1
S2
OFF
ON
OFF
ON
1
8
1
8
8-fold DIP switch
F1
F2
F1, F2: Safety fuses
Figure 3.1 Overview of the connection and setting elements

Interfaces SMP16-SFT251
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3.2 Pin Connector X2 to SMP16 Bus
The following table shows the bus signals used by the board.
Pin a b c
1 –A16 –
2 –A17 GND
3 –AEN +5 V
4 ––MMIO*
5 MEMCS16* –A12
6 RESET* –A0
7 ––A13
8 MEMR* –A1
9 RESIN* –A14
10 MEMW* –A2
11 –ACEN A15
12 RDYIN –A3
13 BUSEN ACDONE INT0oNMI*
14 DB0 –A4
15 –+5 V
INT1*
16 DB1 GND A5
17 –GND
BS
18 DB2 –A6
19 ––INT2*
20 DB3 –A7
21 IOCS16* –INT3*
22 DB4 DB8 A8
23 –DB9 INT4*
24 DB5 DB10 A9
25 –DB11
INT5*
26 DB6 DB12 A10
27 –DB13
INT0*
28 DB7 DB14 A11
29 –DB15
NMI*
30 IOW* BHEN IOR*
31 –A18 GND
32 +5 V A19 –
3.2.1 Signals for the Daisy Chain
ACEN,
ACDONE Input (b11)
Output, open collector (b13)
The ACEN input signals a board that it has been selected for configuration of
the ASBIC chip. Using the ACDON output, it indicates that it has finished its
own configuration and the next board can be configured. See chapter 1.1.

SMP16-SFT251 Interfaces
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3.2.2 Other Special Signals
AEN Address Enable, input (b3)
Control signal for PC compatible bus accesses, must be connected with AEN
(b3) to the CPU slot for PC-I/O addressing (up to 3FFh).
BS "Board Select," input, TTL level (c17)
When low, this signal deactivates the board. However, the interrupts of the
board still remain active.
Interrupts of the counting channels and extra inputs
INT0*
INT1*
INT2*
INT3*
INT4*
INT5*
Interrupt output, open collector (c27)
Interrupt output, open collector (c15)
Interrupt output, open collector (c19)
Interrupt output, open collector (c21)
Interrupt output, open collector (c23)
Interrupt output, open collector (c25)
INT0oNMI* Interrupt output, open collector (c13)
Interrupt INT0* is located here so that it is compatible with the SMP-E251.
This interrupt is identical to the INT0* signal. Modern applications sometimes
use this pin as NMI*. When, for instance, the SMP16-COM595 bus coupler
and the SMP16-SFT251 are installed in the same slot for this reason, the
INT0* signal must be switched off from this pin. See chapter 6.4.5. INT0* can
always be taken from pin c27.
NMI* "Non Maskable Interrupt," output, open collector (c13)
Characteristics: low: 0.4 V/8 mA
Signalizes a hardware error of the ASBIC chipc or of the board.

Interfaces SMP16-SFT251
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3.3 I/O Connectors X3 and X4
The following table shows the assignment of the 15-pin, sub D socket strips X3 and X4.
Pin Assignment Pin Assignment
1 VCC 9 An
2 VCC 10 GND
3 Bn* 11 ZS1n
4 An* 12 ZS0n
5 Nn 13 ZS3n
6 GND 14 ZS2n
7 Nn* 15 GNDn
8 Bn
n = Channel number (0 or 1)
VCC 5 V encoder power (via 750 mA fine fuse from the system power supply)
GND Ground connection for shaft encoder signals
An Uninverted input of track A of channel n
An* Inverted input of track A of channel n
Bn Uninverted input of track B of channel n
B0* Inverted input of track B of channel n
Nn Uninverted input of track N of channel n
Nn* Inverted input of track N of channel n
ZS0n, ZS1n,
ZS2n, ZS3n Extra inputs for channel n (see chapter 6.3.8 for a description)
GNDn Ground connection for the extra inputs of channel n (summation point)
This ground can be connected to system ground (GND) with switch S1.8.
Note:
The differential control lines (e.g., An and An*) must be twisted in pairs.
When single-ended connection of a shaft encoder with a 24 V interface is to be used, the inverted
inputs (An*, Bn* and Nn*) of each signal (A, B, and N) must be connected to GND. The lines with the
signals (An, Bn and Nn) must be twisted in pairs with the corresponding grounding line.
The lines of the extra inputs must be twisted in pairs with the corresponding grounding line.