Texas Instruments TPS65253 User manual

User’s Guide
TPS65253 Buck Converter Evaluation Module User's
Guide
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Background.............................................................................................................................................................................3
3 Schematic................................................................................................................................................................................4
4 Placement................................................................................................................................................................................5
5 Bench Test Setup Conditions................................................................................................................................................ 8
5.1 Headers Description and Jumper Placement.....................................................................................................................8
5.2 Jumpers..............................................................................................................................................................................9
5.3 Test Points and Placement.................................................................................................................................................9
6 Power-Up Procedure............................................................................................................................................................ 10
7 Bill of Materials......................................................................................................................................................................11
8 Revision History................................................................................................................................................................... 12
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1 Introduction
This document presents the information required to power the TPS65253 PMIC as well as the support
documentation including schematic and bill of materials.
Introduction www.ti.com
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2 Background
The TPS65253 PMIC is designed to provide 3.5-A and 2.5-A continuous outputs with an operational range of 4.5
V to 16 V and an externally set switching frequency ranging from 300 kHz to 1.2 MHz. When the PMIC is not
fully loaded, buck1 can be loaded to 4 A and buck 2 to 3 A.
As there are many possible options to set the converters, Table 2-1 presents the performance specification
summary for the EVM.
Table 2-1. Input Voltage and Output Current Summary
EVM TEST CONDITIONS OUTPUT CURRENT RANGE
TPS65253EVM VIN = 4.5 V to 16 V
fsw = 500 kHz
Buck1, 1.2 V, 3.5 A
Buck2, 3.3 V, 2.5 A
(25°C ambient)
This evaluation module is designed to provide access to the features of the TPS65253. Some modifications
can be made to this module to test performance at different input and output voltages, current and frequency
operation. Please contact TI Field Applications Group for advice on these matters.
www.ti.com Background
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3 Schematic
Figure 3-1 illustrates the TPS65253 EVM schematic.
The resistor and capacitor values have been chosen according to the guidelines presented on the TPS65253 spec available at http://focus.ti.com/docs/
prod/folders/print/TPS65253.html.
Note that for the purpose of gains-phase measurements R9 and R11 (0 Ω on the EVM) need to be replaced by suitable low value resistors as per the
network analyzer setup required. Test points are provided on either end of the resistors to allow for easy measurement. Also, R3, R4, C10, and C12 can
be populated if users desire to reduce overshoot at LX pins due to parasitic L and C resonance.
ROSC
1
FB1
2
COMP1
3
SS1
4
RLIM1
5
EN1
6
BST1
7
VIN1 8
LX1 9
LX1 10
LX2 11
LX2 12
VIN2 13
BST2 14
EN2 15
RLIM2 16
SS2 17
COMP2 18
FB2 19
LOW_P/SDA 20
V7V 21
V3p3
22
V3p3
23
PGOOD
24
PB
25
MR/SCL
26
LH
27
INT
28
PP
29
U1
TPS65253
3.3uF
C22
TP24
V3p3
100K
R24
0
R25
TP25
TP26
TP28
383K
R1
V7V
V3p3
100K
R28
FB1
100pF
DNI
C3a
20K
R3
4.7nF
C3
4.7nF
C4
100K
R5
JP6
4.7nF
C6
47nF
C7
TP8
10uF
C8
25V
VIN
22uF
C9
40.2K R9a
80.6K
R9b
4.7nF
C9a
FB1
1
2
J9
4.7uH
L9
4.7uH
L11
1
2
J11
22uF
C11
40.2K
R11a
32K
R11b
4.7nF
C11a
FB2
47nF
C14
10uF
25V
C13
VIN
1
2
J8
VIN
JP15 4.7nF
C15
TP20
150KR16
4.7nF
C17
100pF
DNI C18a
20K
R18
4.7nF
C18
FB2
10uF
C21
SDA
0
R9
TP9
TP9a
TP9b
0
R11
TP11 TP11b
TP11a
1.8V@2A
1.2V@3A
TP1 TP2 TP3 TP4 TP5
JP20
V3p3
TP23
4.5V
V3p3
V3p3
1
2
3
4
S25 JP25 0.1uF
DNI
C25
1
2
3
4
S26
0.1uF
DNI
C26
JP23
V7V
0
R26 JP26
VOUT2
VOUT1
VIN
Figure 3-1. TPS65253 Schematic
Schematic www.ti.com
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4 Placement
Figure 4-1. Part Placement
Figure 4-2. Top Layer
www.ti.com Placement
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Figure 4-3. Mid-Layer 1
Figure 4-4. Mid-Layer 2
Placement www.ti.com
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Figure 4-5. Bottom Layer
www.ti.com Placement
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5 Bench Test Setup Conditions
5.1 Headers Description and Jumper Placement
Vin:4.5V – 16V
Vout1
Vout2
PGOOD
LOW_P EN2
EN1
Figure 5-1. Headers Description and Jumper Placement
Test points:
Black – GND
White – Each output, feed-back, power good and VIN. All marking on PCB.
Bench Test Setup Conditions www.ti.com
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5.2 Jumpers
Table 5-1. Jumpers
JUMPER
NO. FUNCTION PLACEMENT COMMENT
JP6 BUCK1 enable (EN1) For sequencing do not fit jumper.
To disable converter fit jumper to GND. Fit according to test requirement
JP15 BUCK2 enable (EN2) For sequencing do not fit jumper.
To disable converter fit jumper to GND. Fit according to test requirement
JP20 LOW_P Low power: Power save mode ON/OFF.
If need low power mode test, should connect V3V.
Fit according to test requirement.
During normal operation jumper must be
fitted.
JP24 PGOOD Pulls PGOOD signal to internal 3V3 rail or
grounds pin Fit according to test requirement
5.3 Test Points and Placement
Buck converter outputs are white and have a label for easy location. Close to any of these test points there
are black ground test points to allow for DVM measurement or to use a metal exposed scope probe to reduce
common mode noise measurements. All test points are described in Table 5-2.
Table 5-2. Test Points and Placement
TEST
POINT NAME SIGNAL COLOR COMMENT
TP1, TPS, TP3,
TP4, TP5 GND Ground Black
TP8 VIN Input supply White
TP9, TP9A VOUT1 Buck1 output White
TP9B Input for gain-phase measurement Buck1 White Normally not used
TP11, TP11A VOUT2 Buck2 output White
TP11B Input for gain-phase measurement Buck2 White Normally not used
TP20 Low_P Low Power input White
TP24 PGOOD Power Good
(open drain connected to Buck1 output) White
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6 Power-Up Procedure
1. Define which converters are to be enabled or disabled by connecting the correct jumpers accordingly.
2. Apply a DC voltage to jumper J8. Polarity is clearly marked on the silk-screen.
3. Verify that the relevant converters are powered up by the output voltages. The whole start-up process will
take less than 100 ms. PGOOD will be asserted high 32 ms after all converter outputs have reached 90% of
nominal voltages.
4. Apply loads to the output connectors (J9 and J11).
Power-Up Procedure www.ti.com
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