Analog Devices ADSP-BF535 Blackfin Application guide

a
ADSP-BF535 Blackfin®Processor
Hardware Reference
Revision 3.3, February 2013
Part Number
82-000410-13
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information
© 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, CrossCore, VisualDSP++, and
EZ-KIT Lite are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.

ADSP-BF535 Blackfin Processor Hardware Reference iii
CONTENTS
PREFACE
Purpose of This Manual ............................................................. xliii
Intended Audience ...................................................................... xliii
Manual Contents ......................................................................... xliv
What’s New in This Manual ..................................................... xlviii
Technical Support ..................................................................... xlviii
Supported Processors .................................................................... xlix
Product Information ........................................................................ l
Analog Devices Web Site ............................................................ l
EngineerZone ............................................................................ li
Notation Conventions .................................................................... lii
Register Diagram Conventions ...................................................... liii
INTRODUCTION
ADSP-BF535 Peripherals .............................................................. 1-1
ADSP-BF535 Core Architecture .................................................... 1-2
Memory Architecture .................................................................... 1-5
Internal (On-Chip) Memory .................................................... 1-7
External (Off-Chip) Memory ................................................... 1-8

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iv ADSP-BF535 Blackfin Processor Hardware Reference
PCI ........................................................................................ 1-8
I/O Memory Space ................................................................ 1-10
Event Handling .......................................................................... 1-10
DMA Support ........................................................................... 1-11
External Bus Interface Unit ......................................................... 1-12
PC133 SDRAM Controller ................................................... 1-12
Asynchronous Controller ...................................................... 1-13
PCI Interface .............................................................................. 1-13
PCI Host Function ............................................................... 1-14
PCI Target Function ............................................................. 1-15
USB Port .................................................................................... 1-15
Real-Time Clock ........................................................................ 1-15
Watchdog Timer ......................................................................... 1-16
Timers ....................................................................................... 1-17
Serial Ports (SPORTs) ................................................................. 1-17
Serial Peripheral Interface (SPI) Ports .......................................... 1-19
UART Ports ............................................................................... 1-20
Programmable Flags .................................................................... 1-21
Low Power Operation ................................................................. 1-22
Full On Operating Mode (Maximum Performance) ............... 1-22
Active Operating Mode (Low Power Savings) ......................... 1-22
Sleep Operating Mode (High Power Savings) ......................... 1-23
Deep Sleep Operating Mode (Maximum Power Savings) ........ 1-23
Clock Signals .............................................................................. 1-23

ADSP-BF535 Blackfin Processor Hardware Reference v
Contents
Boot Modes ................................................................................ 1-24
Instruction Set Description ......................................................... 1-24
Development Tools ..................................................................... 1-24
COMPUTATIONAL UNITS
Using Data Formats ...................................................................... 2-3
Binary String ........................................................................... 2-3
Unsigned ................................................................................. 2-4
Signed Numbers: Two’s-Complement ....................................... 2-4
Fractional Representation: 1.15 ................................................ 2-4
Register Files ................................................................................. 2-5
Data Register File .................................................................... 2-6
Accumulator Registers ............................................................ 2-6
Pointer Register File ................................................................ 2-6
DAG Register Set ................................................................... 2-7
Register File Instruction Summary ........................................... 2-8
Data Types .................................................................................. 2-10
Data Formats ........................................................................ 2-11
Endianess .............................................................................. 2-12
ALU Data Types .................................................................... 2-12
Multiplier Data Types ............................................................ 2-13
Shifter Data Types ................................................................. 2-14
Arithmetic Formats Summary ................................................ 2-15
Using Multiplier Integer and Fractional Formats .................... 2-16

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vi ADSP-BF535 Blackfin Processor Hardware Reference
Rounding Multiplier Results ................................................. 2-18
Unbiased Rounding .......................................................... 2-18
Biased Rounding .............................................................. 2-20
Truncation ....................................................................... 2-21
Special Rounding Instructions ............................................... 2-21
Using Computational Status ....................................................... 2-22
Arithmetic Status Register (ASTAT) ............................................ 2-23
Arithmetic Logic Unit (ALU) ...................................................... 2-24
ALU Operations ................................................................... 2-24
Single 16-Bit Operations .................................................. 2-25
Dual 16-Bit Operations .................................................... 2-25
Quad 16-Bit Operations ................................................... 2-25
Single 32-Bit Operations .................................................. 2-27
Dual 32-Bit Operations .................................................... 2-27
ALU Instruction Summary .................................................... 2-28
ALU Data Flow Details ......................................................... 2-28
Dual 16-Bit Cross Options .............................................. 2-30
ALU Status Signals ........................................................... 2-31
ALU Division Support Features ............................................. 2-31
Special SIMD Video ALU Operations .................................. 2-32
Multiply Accumulators (Multipliers) ........................................... 2-32
Multiplier Operation ............................................................. 2-33
Placing Multiplier Results in Multiplier Accumulator
Registers ........................................................................ 2-34
Rounding or Saturating Multiplier Results ........................ 2-34

ADSP-BF535 Blackfin Processor Hardware Reference vii
Contents
Saturating Multiplier Results on Overflow ............................ 2-35
Multiplier Instruction Summary ............................................ 2-35
Multiplier Instruction Options .......................................... 2-35
Multiplier Data Flow Details ................................................. 2-38
Multiply Without Accumulate ............................................... 2-40
Special 32-Bit Integer MAC Instruction ................................. 2-42
Dual MAC Operations .......................................................... 2-43
Barrel Shifter (Shifter) ................................................................. 2-44
Shifter Operations ................................................................. 2-44
Two Operand Shifts .......................................................... 2-45
Immediate Shifts ........................................................... 2-45
Register Shifts ............................................................... 2-46
Three Operand Shifts ........................................................ 2-46
Immediate Shifts ........................................................... 2-46
Register Shifts ............................................................... 2-47
Bit Test, Set, Clear, Toggle ................................................ 2-48
Field Extract and Field Deposit ......................................... 2-48
Shifter Instruction Summary .................................................. 2-48
OPERATING MODES AND STATES
User Mode .................................................................................... 3-3
Protected Resources and Instructions ....................................... 3-4
Protected Memory ................................................................... 3-5

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viii ADSP-BF535 Blackfin Processor Hardware Reference
Entering User Mode ................................................................ 3-5
Example Code to Enter User Mode Upon Reset ................... 3-5
Return Instructions That Invoke User Mode ....................... 3-5
Supervisor Mode .......................................................................... 3-6
Non-OS Environments ........................................................... 3-7
Example Code to Stay in Supervisor Mode Coming Out of
Reset ............................................................................... 3-8
Emulation Mode .......................................................................... 3-9
Idle State ...................................................................................... 3-9
Example Code for Transition to Idle State .............................. 3-10
Reset State .................................................................................. 3-10
System Reset and Power-up Configuration .................................. 3-12
Hardware Reset ..................................................................... 3-13
System Reset Configuration Register (SYSCR) ....................... 3-14
Software Resets and Watchdog Timer .................................... 3-14
Software Reset Register (SWRST) ......................................... 3-16
Core Only Software Reset ..................................................... 3-17
Booting Methods ........................................................................ 3-17
PROGRAM SEQUENCER
Sequencer Related Registers ......................................................... 4-3
Sequencer Status Register (SEQSTAT) ..................................... 4-4
Zero-Overhead Loop Registers (LC, LT, LB) ............................ 4-5
System Configuration Register (SYSCFG) ............................... 4-6
Instruction Pipeline ...................................................................... 4-7

ADSP-BF535 Blackfin Processor Hardware Reference ix
Contents
Branches and Sequencing .............................................................. 4-9
Direct Short and Long Jumps ................................................ 4-11
Direct Call ........................................................................... 4-11
Indirect Branch and Call ........................................................ 4-11
PC-Relative Indirect Branch and Call ..................................... 4-12
Condition Code Flag ............................................................. 4-12
Conditional Branches ........................................................ 4-13
Conditional Register Move ................................................ 4-13
Branch Prediction .................................................................. 4-14
Loops and Sequencing ................................................................. 4-15
Events and Sequencing ................................................................ 4-17
System Interrupt Processing ................................................... 4-20
System Peripheral Interrupts .................................................. 4-22
System Interrupt Wakeup-Enable Register (SIC_IWR) ........... 4-24
System Interrupt Status Register (SIC_ISR) ........................... 4-25
System Interrupt Mask Register (SIC_IMASK) ...................... 4-27
System Interrupt Assignment Registers (SIC_IARx) ................ 4-29
Event Controller Registers ........................................................... 4-31
Core Interrupt Mask Register (IMASK) ................................. 4-32
Core Interrupt Latch Register (ILAT) ..................................... 4-32
Core Interrupts Pending Register (IPEND) ............................ 4-33
Global Enabling/Disabling of Interrupts ...................................... 4-34

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x ADSP-BF535 Blackfin Processor Hardware Reference
Event Vector Table ...................................................................... 4-35
Emulation ............................................................................. 4-36
Reset .................................................................................... 4-36
NMI (Non-Maskable Interrupt) ............................................ 4-38
Exceptions ............................................................................ 4-38
Exceptions While Executing an Exception Handler ................ 4-43
Hardware Error Interrupt ........................................................... 4-44
Core Timer ........................................................................... 4-46
General-Purpose Interrupts (IVG7-IVG15) ............................ 4-46
Servicing Interrupts .................................................................... 4-46
Interrupts With and Without Nesting ......................................... 4-48
Example Prolog Code for Nested Interrupt Service Routine .... 4-51
Example Epilog Code for Nested Interrupt Service Routine .... 4-51
Logging of Nested Interrupt Requests .................................... 4-52
Self-Nesting Mode ................................................................ 4-53
Exception Handling .............................................................. 4-54
Deferring Exception Processing ......................................... 4-55
Example Code for an Exception Handler ........................... 4-55
Example Code for an Exception Routine ........................... 4-57
Executing RTX, RTN, or RTE in a Lower Priority Event ... 4-57
Recommendation for Allocating the System Stack ............. 4-58
Latency in Servicing Events ................................................... 4-58

ADSP-BF535 Blackfin Processor Hardware Reference xi
Contents
DATA ADDRESS GENERATORS
Addressing With DAGs ................................................................. 5-4
Frame and Stack Pointers ......................................................... 5-5
Addressing Circular Buffers ..................................................... 5-6
Addressing With Bit-Reversed Addresses .................................. 5-9
Indexed Addressing With Index and Pointer Registers .................... 5-9
Auto-Increment and Auto-Decrement Addressing ................... 5-10
Pre-Modify Stack Pointer Addressing ..................................... 5-11
Indexed Addressing With Immediate Offset ........................... 5-11
Post-Modify Addressing ........................................................ 5-11
Modifying DAG and Pointer Registers ......................................... 5-12
Memory Address Alignment ....................................................... 5-13
DAG Instruction Summary ......................................................... 5-16
MEMORY
Terminology ................................................................................. 6-1
Memory Architecture .................................................................... 6-5
Internal Memory ..................................................................... 6-9
Overview of L1 Instruction SRAM .................................... 6-10
Overview of L1 Data SRAM ............................................. 6-10
Overview of Scratchpad Data SRAM ................................. 6-11
Overview of On-Chip L2 Memory .................................... 6-11
Level 1 Memory .................................................................... 6-12
Data Memory Control Register (DMEM_CONTROL) .......... 6-12

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xii ADSP-BF535 Blackfin Processor Hardware Reference
Instruction Memory Control Register (IMEM_CONTROL) . 6-12
L1 Instruction Memory ......................................................... 6-14
L1 Instruction SRAM ....................................................... 6-14
L1 Instruction Cache ............................................................ 6-17
Cache Lines ...................................................................... 6-17
Cache Hits and Misses .................................................. 6-19
Cache Line Fills ............................................................ 6-20
Line Fill Buffer ............................................................. 6-21
Non-Cacheable Accesses ............................................... 6-22
Cache Line Replacement ............................................... 6-22
Instruction Cache Management ............................................. 6-24
Instruction Cache Locking ................................................ 6-24
Instruction Cache Invalidation .......................................... 6-25
Instruction Test Registers .................................................. 6-26
Instruction Test Command Register (ITEST_COMMAND) .. 6-27
Instruction Test Data 1 Register (ITEST_DATA1) ................. 6-28
Instruction Test Data 0 Register (ITEST_DATA0) ................. 6-29
Example Code for Direct Invalidation ................................... 6-30
L1 Data Memory .................................................................. 6-37
L1 Data SRAM ................................................................ 6-38
L1 Data Cache ................................................................. 6-40
Example of Mapping Cacheable Address Space into Data
Banks ........................................................................ 6-41
Data Cache Access ........................................................ 6-45

ADSP-BF535 Blackfin Processor Hardware Reference xiii
Contents
Cache Write Method ..................................................... 6-46
Data Cache Control Instructions ................................... 6-47
Data Test Registers ...................................................................... 6-47
Data Test Command Register (DTEST_COMMAND) .......... 6-49
Data Test Data 1 Register (DTEST_DATA1) ......................... 6-49
Data Test Data 0 Register (DTEST_DATA0) ......................... 6-50
On-Chip Level 2 (L2) Memory ................................................... 6-52
On-Chip L2 Bank Access ....................................................... 6-52
Latency ................................................................................. 6-53
Off-Chip L2 Memory ............................................................ 6-55
Memory Protection and Properties .............................................. 6-56
Memory Management Unit ................................................... 6-56
Memory Pages ....................................................................... 6-58
Memory Page Attributes .................................................... 6-58
Page Descriptor Table ............................................................ 6-60
CPLB Management ............................................................... 6-61
MMU Application ................................................................. 6-62
Examples of Protected Memory Regions ................................. 6-63
DCPLB Data Registers (DCPLB_DATAx) ............................. 6-65
ICPLB Data Registers (ICPLB_DATAx) ................................ 6-67
DCPLB Address Registers (DCPLB_ADDRx) ........................ 6-69
ICPLB Address Registers (ICPLB_ADDRx) ........................... 6-71
DCPLB and ICPLB Status Registers (DCPLB_STATUS,
ICPLB_STATUS) ............................................................... 6-72
DCPLB Status Register (DCPLB_STATUS) .......................... 6-73

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xiv ADSP-BF535 Blackfin Processor Hardware Reference
ICPLB Status Register (ICPLB_STATUS) ............................. 6-74
DCPLB and ICPLB Fault Address Registers
(DCPLB_FAULT_ADDR, ICPLB_FAULT-ADDR) ............ 6-74
DCPLB Fault Address Register (DCPLB_FAULT_ADDR) .... 6-75
ICPLB Fault Address Register (ICPLB_FAULT_ADDR) ........ 6-76
Memory Transaction Model ........................................................ 6-76
Load/Store Operation ................................................................. 6-77
Interlocked Pipeline .............................................................. 6-78
Ordering of Loads and Stores ................................................ 6-79
Synchronizing Instructions .................................................... 6-80
Speculative Load Execution ................................................... 6-81
Conditional Load Behavior ................................................... 6-82
Working With Memory .............................................................. 6-83
Alignment ............................................................................. 6-83
Atomic Operations ................................................................ 6-83
Memory-Mapped Registers .................................................... 6-84
Core MMR Programming Code Example .......................... 6-85
CHIP BUS HIERARCHY
Internal Interfaces ......................................................................... 7-1
ADSP-BF535 Internal Clocks ....................................................... 7-2
Core Overview ............................................................................. 7-3
System Overview .......................................................................... 7-5
System Bus Interface Unit (SBIU) ........................................... 7-5
On-Chip L2 SRAM Memory Interface .................................... 7-7

ADSP-BF535 Blackfin Processor Hardware Reference xv
Contents
System Interfaces .......................................................................... 7-7
Peripheral Bus (PAB) ............................................................... 7-8
PAB Arbitration .................................................................. 7-8
PAB Performance ................................................................ 7-8
PAB Agents (Masters, Slaves) ............................................... 7-9
DMA Bus (DAB) .................................................................. 7-10
DAB Arbitration ............................................................... 7-10
DAB Performance ............................................................. 7-11
DAB Bus Agents (Masters) ................................................ 7-14
External Access Bus (EAB) ..................................................... 7-14
EAB Arbitration ................................................................ 7-15
EAB Performance .............................................................. 7-15
EAB Bus Agents (Masters, Slaves) ...................................... 7-17
External Mastered Bus (EMB) ................................................ 7-18
EMB Arbitration ............................................................... 7-18
EMB Performance ............................................................. 7-18
EMB Bus Agents (Masters, Slaves, Bridges) ........................ 7-18
Resources Accessible From EMB ........................................ 7-19
DYNAMIC POWER MANAGEMENT
Clocking ....................................................................................... 8-1
Phase Locked Loop and Clock Control .................................... 8-2
PLL Overview ..................................................................... 8-2
PLL Clock Multiplier Ratios .................................................... 8-3
Core Clock/System Clock Ratio Control ............................ 8-5

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xvi ADSP-BF535 Blackfin Processor Hardware Reference
PLL Memory-Mapped Registers (MMRs) ................................ 8-7
PLL Control Register (PLL_CTL) ....................................... 8-7
PLL Status Register (PLL_STAT) ........................................ 8-9
PLL Lock Count Register (PLL_LOCKCNT) ................... 8-10
Dynamic Power Management Controller ..................................... 8-11
Operating Modes .................................................................. 8-12
Full On Mode .................................................................. 8-12
Active Mode ..................................................................... 8-12
Sleep Mode ...................................................................... 8-13
Deep Sleep Mode ............................................................. 8-14
Operating Mode Transitions .................................................. 8-14
Programming Operating Mode Transitions ........................ 8-17
PLL Programming Sequence ......................................... 8-17
PLL Programming Sequence Continues ......................... 8-19
Examples ...................................................................... 8-20
Peripheral Clocking ............................................................... 8-22
Peripheral Clock Enable Register (PLL_IOCK) ................. 8-22
Dynamic Supply Voltage Control .......................................... 8-23
PCI Power Savings ............................................................ 8-24
Changing Voltage ............................................................. 8-24
External Voltage Regulator Example .................................. 8-25
Power Saving Sequence ................................................. 8-25
High Performance Sequence .......................................... 8-26

ADSP-BF535 Blackfin Processor Hardware Reference xvii
Contents
DIRECT MEMORY ACCESS
Descriptor Based DMA ................................................................. 9-3
DMA Descriptor Block Structure ............................................. 9-4
DMA Configuration Word ...................................................... 9-6
Setting Up Descriptor Based DMA .......................................... 9-8
Descriptor-Based DMA Operation ......................................... 9-10
Autobuffer Based DMA ............................................................... 9-15
Setting Up Autobuffer Based DMA ........................................ 9-15
DMA Control Registers .............................................................. 9-16
Peripheral DMA Configuration Register ................................ 9-16
Peripheral DMA Transfer Count Register ............................... 9-19
Peripheral DMA Start Address Registers ................................. 9-21
Peripheral DMA Next Descriptor Pointer Register .................. 9-23
DMA Descriptor Base Pointer Register (DMA_DBP) ............. 9-24
Peripheral DMA Descriptor Ready Register ............................ 9-25
Peripheral DMA Current Descriptor Pointer Register ............. 9-26
Peripheral DMA IRQ Status Register ..................................... 9-28
Memory DMA (MemDMA) ........................................................ 9-31
MemDMA Control Registers ....................................................... 9-32
Destination Memory DMA Configuration Register
(MDD_DCFG) .................................................................. 9-33
Destination Memory DMA Transfer Count Register
(MDD_DCT) .................................................................... 9-34
Destination Memory DMA Start Address Registers
(MDD_DSAH, MDD_DSAL) ........................................... 9-35

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xviii ADSP-BF535 Blackfin Processor Hardware Reference
Destination Memory DMA Next Descriptor Pointer
Register (MDD_DND) ...................................................... 9-36
Destination Memory DMA Descriptor Ready Register
(MDD_DDR) ................................................................... 9-36
Destination Memory DMA Current Descriptor Pointer
Register (MDD_DCP) ....................................................... 9-37
Destination Memory DMA Interrupt Register (MDD_DI) .... 9-38
Source Memory DMA Configuration Register
(MDS_DCFG) .................................................................. 9-39
Source Memory DMA Transfer Count Register
(MDD_DCT) .................................................................... 9-40
Source Memory DMA Start Address Registers
(MDS_DSAH, MDS_DSAL) ............................................. 9-41
Source Memory DMA Next Descriptor Pointer Register
(MDS_DND) .................................................................... 9-42
Source Memory DMA Descriptor Ready Register
(MDS_DDR) .................................................................... 9-42
Source Memory DMA Current Descriptor Pointer Register
(MDS_DCP) ..................................................................... 9-43
Source Memory DMA Interrupt Register (MDS_DI) ............. 9-43
Performance/Throughput for MemDMA ............................... 9-44
DMA Abort Conditions .............................................................. 9-44
DMA Bus Error Conditions ........................................................ 9-45
Data Misalignment ............................................................... 9-46
Illegal Memory Access ........................................................... 9-46

ADSP-BF535 Blackfin Processor Hardware Reference xix
Contents
SPI COMPATIBLE PORT CONTROLLERS
Interface Signals .......................................................................... 10-4
Serial Peripheral Interface Clock Signal (SCK) ....................... 10-4
Serial Peripheral Interface Slave Select Input Signal ................ 10-5
Master Out Slave In (MOSI) ................................................. 10-5
Master In Slave Out (MISO) ................................................. 10-5
Interrupt Behavior ................................................................. 10-6
SPI Registers ............................................................................... 10-7
Non-DMA Registers .............................................................. 10-7
SPIx Baud Rate Register (SPIx_BAUD) ............................. 10-7
SPIx Control Register (SPIx_CTL) .................................... 10-8
SPIx Flag Register (SPIx_FLG) ........................................ 10-10
Slave Select Inputs ....................................................... 10-13
Multiple Slave SPI Systems .......................................... 10-14
SPIx Status Register (SPIx_ST) ........................................ 10-15
SPIx Transmit Data Buffer Register (SPIx_TDBR) ........... 10-17
SPIx Receive Data Buffer Register (SPIx_RDBR) ............. 10-18
SPIx RDBR Shadow Register (SPIx_SHADOW) ............. 10-18
DMA Registers .................................................................... 10-19
SPIx DMA Current Descriptor Pointer Register
(SPIx_CURR_PTR) ........................................................ 10-20
SPIx DMA Configuration Register (SPIx_CONFIG) ....... 10-21
SPIx DMA Start Address High Register
(SPIx_START_ADDR_HI) and SPIx DMA Start
Address Low Register (SPIx_START_ADDR_LO) ........ 10-22

Contents
xx ADSP-BF535 Blackfin Processor Hardware Reference
SPIx DMA Count Register (SPIx_COUNT) ................... 10-23
SPIx DMA Next Descriptor Pointer Register
(SPIx_NEXT_DESCR) ............................................... 10-24
SPIx DMA Descriptor Ready Register
(SPIx_DESCR_RDY) .................................................. 10-25
SPIx DMA Interrupt Register (SPIx_DMA_INT) ........... 10-26
Register Functions .............................................................. 10-26
SPI Transfer Formats ................................................................ 10-28
SPI General Operation ............................................................. 10-30
Clock Signals ...................................................................... 10-31
Master Mode Operation ...................................................... 10-32
Transfer Initiation From Master (Transfer Modes) ................ 10-33
Slave Mode Operation .................................................... 10-34
Slave Ready for a Transfer ............................................... 10-35
Error Signals and Flags ............................................................. 10-35
Mode Fault Error (MODF) ................................................. 10-36
Transmission Error (TXE) ................................................... 10-37
Reception Error (RBSY) ...................................................... 10-37
Transmit Collision Error (TXCOL) ..................................... 10-37
Beginning and Ending an SPI Transfer ...................................... 10-38
SERIAL PORT CONTROLLERS
SPORT Operation ...................................................................... 11-7
SPORT Disable .......................................................................... 11-7
Setting SPORT Modes ................................................................ 11-8