EPC EPC90147 User manual

Development Board
EPC90147
Quick Start Guide
100 V Half-bridge with Gate Drive, Using EPC23102
Revision 1.0

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DESCRIPTION
The EPC90147 development board is a 100 V maximum device voltage,
22|A maximum output current, half bridge featuring the EPC23102
Integrated ePower™ FET. The purpose of this development board is
to simplify the evaluation process of the EPC23102 by including all the
critical components on a single board that can be easily connected into
the majority of existing converter topologies.
The EPC90147 development board measures 2” x 2” and contains one
EPC23102 integrated ePower™ Stage in a half bridge conguration.
The board also contains all critical components and the layout supports
optimal switching performance. There are also various probe points to
facilitate simple waveform measurement and eciency calculation.
A block diagram of the circuit is given in gure 1.
For more information on the FET associated with this board, please
refer to its datasheets available on EPC’s website: EPC23102 datasheet.
The datasheet should be read in conjunction with this quick start guide.
Table 1: Performance Summary (TA= 25°C) EPC90147
Symbol Parameter Conditions Min Nominal Max Units
VDD Gate Drive Input
Supply Range 7.5 12 V
VIN Bus Input Voltage
Range(1) 80 V
IOUT Switch Node Output
Current (2) 22 A
VPWM
PWM Logic Input
Voltage Threshold (3)
Input ‘High’
Input ‘Low’ 3.5 05.5 1.5 V V
Minimum ‘High’ State
Input Pulse Width
VPWM rise and
fall time < 10ns 50 ns
Minimum ‘Low’ State
Input Pulse Width (4)
VPWM rise and
fall time < 10ns 200 ns
(1) Maximum input voltage depends on inductive loading, maximum switch node ringing
must be kept under 100 V for EPC23102.
(2) Maximum current depends on die temperature – actual maximum current is aected by
switching frequency, bus voltage and thermal cooling.
(3) When using the on board logic buers, refer to the EPC23102 datasheet when bypass-
ing the logic buers.
(4) Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Figure 1: Block diagram of EPC90147 development board
Delay
match
level
shift
150 k Logic
+
UVLO
+
XLO
Level
shift
Output
driver
Enable
logic
V
Cntl
EN
L
1
LS
IN
HS
IN
VDrv
VDrv
RnEV
VDD
PWM
GND
C
IN
C
OUT
V
IN
PGND
SW
Phase
GND
GND
V
DD
V
IN
V
IN
V
Boot
R
Boot
R
Boot
R
DRV
R
DRV
Sync
boot
C
Boot
C
VDD
C
Drv
GND
Switch node
DC output
Logic and
dead-time
adjust
Output
driver
EN
Logic
supply
U
1
V
DD
EPC23102
EPC90147 development board
Back viewFront view

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Figure 3: Denition of dead-time between the upper-FET gate signal (DTQup)
and the lower-FET gate signal (DTQlow)
Figure 4: The required resistance values for R620 or R625 as a
function of desired dead-time
Figure 2: Input mode selection on J630
(a) (c)(b)
QUICK START PROCEDURE
The EPC90147 development board is easy to set up as a buck or boost
converter to evaluate the performance of the two EPC23102 ePowerTM FET.
This board includes a logic PWM input signal polarity changer used to ensure
positive PWM polarity for the switching device when congured in either
the buck or boost modes, and can accommodate both single and dual PWM
inputs. Furthermore, the board includes a dead-time generating circuit that
adds a delay from when the gate signal of one FET is commanded to turn
o, to when the gate signal of the other FET is commanded to turn on. In the
default conguration, this dead time circuit ensures that both the high and
low side FETs will not be turned on at the same time thus preventing a shoot-
through condition. The dead-time and/or polarity changing circuits can be
utilized or bypassed for added versatility.
Single/dual PWM signal input settings
There are two PWM signal input ports on the board, PWM1 and PWM2.
Both input ports are used as inputs in dual-input mode where PWM1
connects to the upper FET and PWM2 connects to the lower FET.
The PWM1 input port is used as the input in single-input mode where
the circuit will generate the required complementary PWM for the FETs.
The input mode is set by choosing the appropriate jumper positions for
J630 (mode selection) as shown in gure 2(a) for a single-input buck
converter (blue jumper across pins 1 & 2 of J630), (b) for a single-input
boost converter (blue jumpers across pins 3 & 4 of J630), and (c) for a dual-
input operation (blue jumpers across pins 5 & 6 of J630).
Note: In dual mode there is no shoot-through protection as both gate
signals can be set high at the same time.
Dead-time settings
Dead-time is dened as the time between when one FET turns o and the
other FET turns on, and for this board is referenced to the input of the gate
driver. The dead-time can be set to a specic value where resistor R620
delays the turn on of the upper FET and resistor R625 delays the turn on of
the lower FET as illustrated in gure 3.
The required resistance for the desired dead-time setting can be read o
the graph in gure 4. An example for 10 ns dead-time setting shows that
a 120 Ω resistor is needed.
Note: This is the default deadtime and resistor value installed. A minimum
dead-time of is 5 ns and maximum of 15 ns is recommended.
Bypass settings
Both the polarity changer and the deadtime circuits can be bypassed using
the jumper settings on J640 (Bypass), for direct access to the gate driver
input. There are three bypass options: 1) No bypass, 2) Dead-time bypass,
3) Full bypass. The jumper positions for J640 for all three bypass options are
shown in gure 5.
PWM1
Single input
Buck
Single input
Boost Dual input
PWM2
R(Ω) = 13.5 ∙ DT(ns) − 14
Resistance (Ω)
Dead-time (ns)
190
180
170
160
150
140
130
120
110
100
90
80
70
60
505 6 7 8 9 10 11 12 13 14 15
Figure 5: Bypass mode Jumper settings for J640
(a) (c)(b)
Deadtime
v
t
0
50% 50% 50% 50%
DTQup
DTQlow
Deadtime
Lower FET
turn on delay
Lower FET turn on delay
Upper FET
turn on delay
Upper FET turn on delay
No bypass Bypass deadtime Full Bypass

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In no-bypass mode, gure 5(a) (red jumper across pins 5 & 6 of
J640), both the on-board polarity and dead-time circuits are fully
utilized. In dead-time bypass mode, gure 5(b) (red jumpers
across pins 3 & 4 of J640), only the on-board polarity changer
circuit is utilized, eectively bypassing the dead-time circuit.
In full bypass mode, Figure 5(c) (red jumper across pins 1 & 2 of
J640), the inputs to the gate driver are directly connected to the
PWM1 and PWM2 pins and the on-board polarity and dead-time
circuits are not utilized.
Buck converter conguration
To operate the board as a buck converter, either a single or dual
PWM inputs can be chosen using the appropriate jumper settings
on J630 (mode).
To select Single Input Buck Mode, the bypass jumper J640 must be
set to the no-bypass mode, the buck mode J630 must be selected
as shown in gure 6(a).
To select Dual Input Buck Mode, the bypass jumper J640 may be
congured to any of the valid settings, the dual-input mode J630
must be selected as shown in gure 6(b).
Note: It is important to provide the correct PWM signals that
includes dead-time and polarity when operating in bypass mode.
Once the input source, dead-time settings and bypass cong-
urations have be chosen and set, then the boards can be operated.
1. With power o, connect the input power supply bus to VIN and
ground / return to GND.
2. With power o, connect the switch node (SW) of the half bridge
to your circuit as required (half bridge conguration). Or use the
provided pads for inductor (L1) and output capacitors (Cout), as
shown in gure 6.
3. With power o, connect the gate drive supply to VDD (J1, Pin-1)
and ground return to GND (J1, Pin-2 indicated on the bottom
side of the board).
4. With power o, connect the input PWM control signal to PWM1
and/or PWM2 according to the input mode setting chosen and
ground return to any of GND J2 pins indicated on the bottom
side of the board.
5. Turn on the gate drive supply – make sure the supply is set
between 7.5 V and 12 V.
6. Turn on the controller / PWM input source.
7. Making sure the initial input supply voltage is 0 V, turn on the
power and slowly increase the voltage to the required value
(do not exceed the absolute maximum voltage). Probe switch-
node to see switching operation.
8. Once operational, adjust the PWM control, bus voltage, and load
within the operating range and observe the output switching
behavior, eciency, and other parameters.
9. For shutdown, please follow steps in reverse.
Bypass mode warnings
• It is important to provide the correct PWM signals that includes dead-
time and polarity for either buck or boost operation when making use
of bypass modes.
• When operating in full bypass mode, the input signal specications
revert to that of the EPC23102. Refer to the EPC23102 datasheet for
details.
VDD supply
(Note polarity)
Output Capacitor
Buck Inductor
PWM1
(default)
Jumper positions for
single-input buck
Optional anti-
parallel diodes
DC load
Switch-node
output
Must be in
No-bypass
position
+
+
+
Output Capacitor
Buck Inductor
Optional anti-
parallel diodes
VDD supply
(Note polarity)
VMain
supply
(Note
polarity)
VMain
supply
(Note
polarity)
PWM1
Upper
FET
PWM2
Lower
FET DC load
All valid
positions
permitted
+
+
+
+
Jumper positions for
dual-input buck
12 VDC
80 VDCmax
80 VDCmax
12 VDC
(a)
(b)
Figure 6: (a) Single-PWM input buck converter (b) Dual-PWM input buck converter
congurations showing the supply, anti-parallel diodes, output capacitor,
inductor, PWM, and load connections with corresponding jumper positions.

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Boost Converter conguration
Warning: Never operate the boost converter mode without a
load, as the output voltage can increase beyond the maximum
ratings.
To operate the board as a boost converter, either a single or dual
PWM inputs can be chosen using the appropriate jumper settings
on J630 (mode).
To select Single Input Boost Mode, the bypass jumper J640 must
be set to the no-bypass mode, the boost mode J630 must be
selected as shown in gure.7(a).
To select Dual Input Boost Mode, the bypass jumper J640 may be
congured to any of the valid settings, the dual-input mode J630
must be selected as shown in gure 7(b).
Note: It is important to provide the correct PWM signals that
includes dead-time and polarity when operating in bypass mode.
Once the input source, dead-time settings and bypass congura-
tions have be chosen and set, then the boards can be operated.
1. The inductor (L1) and input capacitors (labeled as Cout) can
either be soldered onto the board, as shown in gure 7, or
provided o board. Anti-parallel diodes can also be installed
using the additional pads on the right side of the EPC23102 FETs.
2. With power o, connect the input power supply bus to VOUT
and ground / return to GND, or externally across the capacitor
if the inductor L1 and Cout are provided externally. Connect the
output voltage (labeled as VIN) to your circuit as required, e.g.,
resistive load.
3. With power o, connect the gate drive supply to VDD (J1, Pin-1)
and ground return to GND (J1, Pin-2 indicated on the bottom
side of the board).
4. With power o, connect the input PWM control signal to PWM1
and/or PWM2 according to the input mode setting chosen and
ground return to any of GND J2 pins indicated on the bottom
side of the board.
5. Turn on the gate drive supply – make sure the supply is between
7.5 V and 12 V.
6. Turn on the controller / PWM input source.
7. Making sure the output is not open circuit, and the input
supply voltage is initially 0 V, turn on the power and slowly
increase the voltage to the required value (do not exceed
the absolute maximum voltage). Probe switch-node to see
switching operation.
8. Once operational, adjust the PWM control, bus voltage, and load
within the operating range and observe the output switching
behavior, eciency, and other parameters. Observe device
temperature for operational limits.
9. For shutdown, please follow steps in reverse.
VDD supply
(Note polarity)
Input Capacitor
Boost Inductor
PWM1
(default)
Optional anti-
parallel diodes
Must be in
No-bypass
position
+
+
12 VDC
80 VDCmax
DC load
+
VMain supply
(Note polarity)
80 VDCmax
DC load
Input Capacitor
Boost Inductor
Optional anti-
parallel diodes
12 VDC
VDD supply
(Note polarity)
PWM1
Upper
FET
PWM2
Lower
FET
All valid
positions
permitted
+
+
+
+
VMain supply
(Note polarity)
Jumper positions for
single-input boost
Jumper positions for
dual-input boost
(a)
(b)
Figure 7: (a) Single-PWM input boost converter (b) Dual-PWM input boost
converter congurations showing the supply, inductor, anti-parallel diodes, input
capacitor, PWM, and load connections with corresponding jumper settings.

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MEASUREMENT CONSIDERATIONS
Measurement connections are shown in gure 8.
When measuring the switch node voltage containing
high-frequency content, care must be taken to
provide an accurate high-speed measurement.
An optional two pin header (J33) is provided for
switch-node measurement.
Dierential probe is recommended for measuring the
high-side bootstrap voltage (J1). IsoVu probes from
Tektronix has mating MMCX connector.
For regular passive voltage probes (e.g. TPP1000)
measuring switch node using MMCX connector,
probe adaptor is available. PN: 206-0663-xx
NOTE. For information about measurement techniques,
the EPC website oers: “AN023 Accurately Measuring
High Speed GaN Transistors” and the How to GaN
educational videoseries,including: HTG09- Measurement
Ground oscilloscope probe
Switch-node
oscilloscope probe
V
+
+
Bootstrap
voltage MMCX
(HIGH VOLTAGE!)
Voltage measurement:
Input voltage for Buck,
Output voltage for Boost
(HIGH VOLTAGE!)
Voltage measurement:
Input voltage for Boost,
Output voltage for Buck
(HIGH VOLTAGE!)
HIGH VOLTAGE
HIGH VOLTAGE
HIGH VOLTAGE
V
Ground oscilloscope probe
Switch-node
oscilloscope probe

Figure 8: Measurement points (a) front side, (b) Back side
(a)
(b)

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Components to remove prior
to Heat-spreader attach
Spacers for heat-spreader
attach
20 mm 9.2 mm
Heat-spreader
Insulator
PCB
assembly
SMD spacer (x3)
eGaN FETs (x2)
TIM
M2 screws (x3)
16.7 mm
THERMAL CONSIDERATIONS
The EPC90147 board is equipped with three mechanical
spacers that can be used to easily attach a heat-spreader or
heatsink as shown in gure 9(a), and only requires a thermal
interface material (TIM), a custom shape heat-spreader/
heatsink, and screws. Prior to attaching a heat-spreader, any
component exceeding 1 mm in thickness under the heat-
spreader area will need to be removed from the board as
shown in gure 9 (b).
Figure 9: Details for attaching a heatsink to the development board.
(a) 3D perspective, (b) top view details, (c) Assembled view with heat-
spreader attached.
(a)
(b)
(c)

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39.0
14.0
5.2
20.0
A
9.2
17.0 8.0
3.6
11.0
28.0
5.2
20.0 9.2
29.2
11.0
3.1
9.0
14.0
16.7
7.5
22.0
3.1
1.3
7.5
23.0
16.7
Ø4.6 (x3)
Ø4.0
M2 screw at heat
countersunk,
Scale 8:1
Units: mm
Part thickness: 1.5 mm
Units: mm
Ø2.2 thru 45°C
>
39.0
EFFICIENTPOWER CONVERSION
EFFICIENTPOWER CONVERSION
Figure 10: Heat-spreader details
Figure 11: Insulator sheet details with opening for the
TIM with location of the FETs
The design of the heat-spreader is shown in gure 10 and can
be made using aluminum or tellurium copper for higher
performance.
The heat-spreader is held in place using countersunk screws
that fasten to the mechanical spacers which will accept M2 x
0.4 mm thread screws such as McMasterCarr 91294A002.
When assembling the heatsink, it may be necessary to add a
thin insulation layer to prevent the heat-spreader from short
circuiting with components that have exposed conductors
such as capacitors and resistors, as shown in gure 11. Note
that the heat-spreader is ground connected by the lower
most mounting post. A rectangular opening in the insulator
must be provided to allow the TIM to be placed over the FETs
to be cooled with a minimum clearance of 1 mm on each side
of the rectangle encompassing the FETs. The TIM will then
be similar in size or slightly smaller than the opening in the
insulator shown by the red dashed outline in gure 11.
EPC recommends Laird P/N: A14692-30, Tgard™ K52 with
thickness of 0.051 mm the for the insulating material.
A TIM is added to improve the interface thermal conductance
between the FETs and the attached heat exchanger. The
choice of TIM needs to consider the following characteristics:
• Mechanical compliance – During the attachment of the
heat spreader, the TIM underneath is compressed from
its original thickness to the vertical gap distance between
the spacers and the FETs. This volume compression exerts
a force on the FETs. A maximum compression of 2:1 is
recommended for maximum thermal performance and to
constrain the mechanical force which maximizes thermal
mechanical reliability.
• Electrical insulation – The backside of the eGaN FET is a
silicon substrate that is connected to source and thus the
upper FET in a half-bridge conguration is connected to the
switch-node. To prevent short-circuiting the switch-node
to the grounded thermal solution, the TIM must be of high
dielectric strength to provide adequate electrical insulation
in addition to its thermal properties.
• Thermal performance – The choice of thermal interface
material will aect the thermal performance of the thermal
solution. Higher thermal conductivity materials is preferred
to provide higher thermal conductance at the interface.
EPC recommends the following thermal interface materials:
• t-Global P/N: TG-A1780 X 0.5 mm (highest conductivity of 17.8 W/m·K)
• t-Global P/N: TG-A6200 X 0.5 mm (moderate conductivity of 6.2 W/m·K)
• Bergquist P/N: GP5000-0.02 (~0.5 mm with conductivity of 5 W/m·K)
• Bergquist P/N: GPTGP7000ULM-0.020 (conductivity of 7 W/m·K)
NOTE. The EPC90147 development board does not have any current or thermal protection on board. For more information
regarding the thermal performance of EPC eGaN FETs, please consult:
D. Reusch and J. Glaser, DC-DC Converter Handbook, a supplement to GaN Transistors for Ecient Power Conversion,
First Edition, Power Conversion Publications, 2015.

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EXPERIMENTAL VALIDATION
The performance of EPC90147 was tested under the operating
conditions given in table 2 unless otherwise specied.
A heat-spreader per gures 10 and 11 with t-Global TG-A1780
thermal interface material (TIM) and a heatsink from Wakeeld
Vette 567-24AB using the same TIM was added to the board prior
to testing at high current.
Additional input and output capacitance are added to suppress
input and output voltage ripple at high output current as shown
in Table 2.
ELECTRICAL PERFORMANCE
Measure Waveforms
Table 2: Test conditions
Parameter Max Units
Regulated Input voltage 48 V
Regulated Output voltage 12 V
Switching frequency (fS)
500
1000
1500
kHz
Inductor (mounted on motherboard) 2.2 μH[1]
Additional Input capacitance (min.) 23.5 μF[2]
Additional Output capacitance (min.) 70.5 μF[3]
Maximum case temperature 110 °C
Dead time 10 ns
RBoot (R60) and RDRV (R78) 3.3 Ω
[1] 2.2 μH inductor from Vishay, P/N IHTH1125KZEB2R2M5A.
[2] Capacitors used:
4.7 μF, 100 V, x5 (P/N: GMC32X7R475K100NT)
[3] Capacitors used:
4.7 μF, 100 V, x5 (P/N: GMC32X7R475K100NT)
47 μF, 80 V, x1 (P/N: 80SXV47M)
Figure 12: Measured inductor current and switch node waveforms when operating from
48 V at 500 kHz and delivering 0 A into a 12 V load
10 V/div
10 ns/div
Inductor
current
Switch
node
5 A/div
10 V/div
500 ns/div

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Measure Waveforms (continued0
Figure 13: Measured inductor current and switch node waveforms when operating from
48 V at 500 kHz and delivering 10 A into a 12 V load
Figure 14: Measured inductor current and switch node waveforms when operating from
48 V at 500 kHz and delivering 15 A into a 12 V load
5 A/div
10 V/div
500 ns/div
10 V/div
10 ns/div
Inductor
current
Switch
node
10 V/div
10 ns/div
Inductor
current
Switch
node
5 A/div
10 V/div
500 ns/div