
QUICK START GUIDE Demonstration System EPC9041
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DESCRIPTION
These development boards are in a monolithic half-bridge topology with
on-board gate drives, featuring the EPC2105 eGaNIC (Enhancement-mode
Gallium Nitride Integrated Circuit). The purpose of these development
boards is to simplify the evaluation process of these monolithically
integrated eGaN FETs by including all the critical components on a single
board that can be easily connected into any existing converter.
The development board is 2” x 2”and contains one eGaNIC in half-bridge
conguration using theTexas Instruments LM5113 gate driver, supply and
bypass capacitors. The board contains all critical components and layout
for optimal switching performance and has additional area to add buck
output lter components on board. There are also various probe points
to facilitate simple waveform measurement and eciency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2105 eGaNIC, please refer to the
datasheet available from EPC at www.epc-co.com. The datasheet should
be read in conjunction with this quick start guide.
SETUP AND OPERATION
The development boards are easy to set up to evaluate the performance
of the eGaNIC. The board allows the on-board placement of buck output
lter components. Refer to Figure 2 for proper connect and measurement
setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and
ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4)
to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and
ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM
(J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between
7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the
absolute maximum voltages).
7. Turn on the controller / PWM input source and probe switching node
to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within
the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must
be taken to avoid long ground leads. Measure the switch node (OUT) by placing
the oscilloscope probe tip through the large via on the switch node (designed for
this purpose) and grounding the probe directly across the GND terminals provided.
See Figure 3 for proper scope probe technique.
Table 1: Performance Summary (TA= 25°C) EPC9041
Symbol Parameter Conditions Min Max Units
VDD Gate Drive Input Supply Range 7 12 V
VIN Bus Input Voltage Range
50*
V
VOUT Switch Node Output Voltage
50*
V
IOUT Switch Node Output Current
20** A
VPWM PWM Logic InputVoltage Threshold Input‘High’
3.5 6 V
Input‘Low’
0 1.5 V
Minimum‘High’State Input Pulse
Width VPWM rise and fall
time < 10ns
50 ns
Minimum‘Low’State Input Pulse
Width VPWM rise and fall
time < 10ns
100# ns
*Maximum input voltage depends on inductive loading.
** Maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus
voltage and thermal cooling. Symmetrical eGaN intended for 50% duty cycle or low step-down ratio applications.
# Limited by time needed to‘refresh’high side bootstrap supply voltage.
VERSION
*
(For Eciency
Measurement)
(Note Polarity)
_
IN
(For Eciency
Measurement)
Pads for Buck
Output Filter
OUT
SW
PGND
VOUT
V
A
IIN
_
_
_V
50V
EPC9041 DEVELOPMENTBOARD
Figure 2: Proper Connection and Measurement Setup
Figure 1: Block Diagram of Development Board
VDD
VIN
PWM
Input
OUT
VSW
Gate Drive Supply
Pads for Buck Output Filter
Monolithic
Half Bridge
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver