EPC EPC9144 User manual

Development Board
EPC9144
Quick Start Guide
EPC2216
15 V High Current Pulsed Laser Diode Driver
Revision 1.0

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DESCRIPTION
The EPC9144 development board is primarily intended to drive laser
diodes with high current pulses with total pulse widths as short as 1.2 ns
and currents of up to 28 A. The board is designed around the EPC2216
enhancement mode (eGaN®) eld eect transistor (FET). The EPC2216
is an AEC-Q101 automotive qualied 15 V FET capable of current pulses
up to 28 A. The EPC9144 ships with the EPC9989 interposer board. The
EPC9989 is a collection of break-away 5 mm x 5 mm square interposer
PCBs with footprints for dierent lasers, RF connectors, and a collection
of other footprints designed for experimentation with dierent loads.
The use of the interposers allows many dierent lasers or other loads to be
mounted while still being able to use the EPC9144. Laser diodes or other
loads are not included, and must be supplied by the user.
The EPC9144 comprises a ground-referenced EPC2216 eGaN FET driven
by a Texas Instruments LMG1020 gate driver. The printed circuit board
is designed to minimize the power loop inductance while maintaining
mounting exibility for the laser diode or other load. It includes multiple
on-board passive probes for voltages, and is equipped with MMCX con-
nections for input and sensing. In addition, the board includes a narrow
pulse generator capable of sub-nanosecond operation, or the user can
simply feed the gate drive directly via removal of a resistor. As shipped,
the board is designed to operate from 3.3 V logic, but is equipped with
both a logic level translator and a dierential receiver to accommodate
dierent use cases. Finally, the board can also be used for other applica-
tions requiring a ground-referenced eGaN FET, e.g. Class E ampliers or
similar. A complete block diagram of the circuit is given in gure 1, and a
detailed schematic in gure 4.
For more information on the EPC2216 eGaN FETs, please refer to the data-
sheet available from EPC at www.epc-co.com. The datasheet should be
read in conjunction with this quick start guide.
SETUP AND OPERATION
Development board EPC9144 is easy to set up to evaluate the perfor-
mance of the EPC2216 eGaN FET. Refer to Figure 2 for proper connect and
measurement setup and follow the procedure below:
1. Review laser safety considerations. Observe all necessary laser safety
requirements including the use of personal protection equipment
(PPE) as required. Refer to qualied safety personnel as necessary.
2. With power o, install laser diode U2 or other load. The use of one of
the interposers from the included EPC9989 may be used to mount the
laser or other load, and this is discussed in the section LASER DIODE
AND LOAD CONSIDERATIONS for further information.
3. With power o, connect the input power supply bus to +VBUS (J1) and
ground / return to –VBUS (J1) or GND.
4. With power o, connect the logic supply (7-12 V VDC) to +VLogic (J2)
and ground return to –VLogic (J2) or GND.
5. With power o, connect the signal pulse generator to the input J5. J5
is terminated with 50 Ω on the EPC9144, and is designed for a 3.3 V
logic input as shipped. This can be changed as discussed in this guide.
6. Connect the remaining measurement MMCX outputs to an oscil-
loscope, using 50 Ω cables and with the scope inputs set to 50 Ω
impedance. See section MEASUREMENT CONSIDERATIONS for more
information, including the attenuation values for each output.
Table 1: Performance Summary (TA= 25°C) EPC9144
Symbol Parameter Conditions Min Nom Max Units
VLogic
Gate drive and
logic supply 6 12 V
VBUS
Bus input voltage
range 0
12* V
ZIN Input impedance J5 input 50 Ω
VINPUT Input pulse range 0
5 V
TPin Input pulse width 1 ns
7. Turn on the logic supply voltage to a value within the specication.
8. Turn on the bus voltage to a value within the specication.
9. Turn on the pulse source and observe switching operation via the
outputs and any additional desired probing. Laser diode output
may be observed with an appropriate electro-optical receiver.
10. Once operational, adjust the bus voltage, input pulse width, and
pulse repetition frequency (PRF) as desired within the operating
range and observe the system behavior.
11. For shutdown, please follow steps in reverse.
NOTE: When measuring the high frequency content switch node, care must be
taken to avoid long ground leads. Measure the switch node by placing the
oscilloscope probe tip through the large via on the switch node (designed for this
purpose) and grounding the probe directly across the GND terminal provided.
See EPC measurement applications note.
SAFETY WARNING: This board is capable of driving laser diodes to generate high
peak power optical pulses. Such pulses are capable of creating permanent vision
damage. User must follow proper laser safety procedures to prevent vision damage.
Figure 1: Block diagram of EPC9144 development board
CAP (J6)
VOUT (J7)
Q1
VGS
(J10)
VGS
(J9)
Input (J5)
V7in +
+
–
Dclmp
U2
VBUS
–
Narrow pulse
generator
(optional)
LDO

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Figure 2: Connection and measurement setup
OPERATING PRINCIPLE
THE EPC9144 is intended as both a demonstration board and a exible
development platform. It is functional out of the box, but is designed
to be easily modied to accommodate a broad range of applications.
It is highly recommended that the user read the entire guide, but
especially the section MODIFICATIONS, in order to get maximum
value from the EPC9144.
The EPC9144 is shipped as a rectangular pulse laser diode driver. Please
refer to the block diagram (Fig. 2) and the schematics (Figures 7 & 8).
It has several possible modications (section MODIFICATIONS), but only
the basic operation will be covered in this section. The EPC9144 basic
operating principle is to act as a current gate to allow current from the
voltage bus to ow through the laser diode or other load when the FET
Q1 is turned on, and stop the load current when the Q1 is turned o.
The speed of the driver and FET means that turn-on and turn-o can be
accomplished as fast as 500 ps and 250 ps, respectively, even for load
currents of approximately 10 A.
The FET Q1 is controlled via an input pulse that is delivered to MMCX
connector J5, which is terminated on the demo board with 50 Ω. J5 is
followed by a logic level translator. As shipped, the level translator is set
for 3.3 V logic levels, but the EPC9144 may be modied to accommodate
other logic levels (See MODIFICATIONS for further details).
After the level translator, the input pulse goes through a narrow pulse
generator circuit. The input pulse should be set > 10 ns longer than the
desired output pulse. As shipped, the pulse width is set to approximately
5 ns, but it may be adjusted to values in the range of 1.2 ns to 20 ns via
trimpot P1, with the lower limit determined by the LMG1020 gate driver IC.
Please note that it is possible to reduce the adjust the input pulse to a
value below the minimum pulse width capability of the LMG1020 gate
driver. In this case, the output will fail to function properly, and the P1
adjustment must be increased. Finally, in the case where one wishes to
control the pulse width externally via the input pulse, the narrow pulse
generator may be bypassed as discussed in the section MODIFICATIONS.
When the input goes high, the gate driver turns on Q1, allowing current
ow through the laser diode or load U2. After the narrow pulse generator
output goes low, Q1 turns o. If there is current remaining in the power
loop inductance, diode-connected EPC2036 FET Q2 can conduct and
help prevent overvoltage of the laser and FET.
The voltage bus for the laser diode or other load is bypassed via the
capacitor bank {C22, C23, C24, C25}. This capacitor bank is part of the
main power loop inductance, and the layout is designed to minimize
the eect of resulting parasitic inductance. The capacitor bank is fed
through a relatively small resistance formed by {R10, R11, R12, R13}.
The resistance served to limit the laser or load current continuous value
in the case of long pulses, and also serves to damp parasitic resonance
of the power loop.
Measurements of key waveforms can be made through the MMCX test
points provided. These test points can provide waveform measurements
with equivalent bandwidths > 3 GHz. As a result, they have requirements
and properties that dier from most conventional oscilloscope
probes. More details on the usage of these test points is provided in
section MEASUREMENT CONSIDERATIONS.
LASER DIODE OR LOAD CONSIDERATIONS
The EPC9144 can be used as is to mount a laser diode or other load.
Figure 3 highlights the output pad locations. However, many laser
suppliers have dierent mounting footprints, making it dicult to
optimize the performance of the driver and still maintain the desired
exibility. The use of an interposer PCB provides a solution to this
problem with a small added performance penalty in the form of an
additional 50 pH to 100 pH power loop inductance. The EPC9144 ships
with the EPC9989 interposer PCB, shown in Fig. 4. The EPC9989 has
an assortment of 5 mm square interposer PCBs that can be snapped
o the board. These interposers have various footprints on the top
side that can accommodate several surface mount laser diodes, an
MMCX connector, and several patterns designed to accommodate a
wide variety of possible loads. These interposers mount between the
EPC9144 and the laser diode or other load. The EPC9989 is updated
as new lasers or loads become available, so Fig. 4 may not show the
latest board.
V7in VBUS
Note
Polarity
+
Signal Generator
+
Laser
diode
or load
Pulse width
adjust
V7
IN
V
BUS
Note polarity
Signal generator Oscilloscope
(50 Ωinputs)
– + + –
Figure 3: Output terminals of the EPC9144
Laser anode
Laser cathode
(FET drain)
GND (for alternate
applications)

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Figure 4: EPC9989 interposer. Note that this board is revised as needed to accommodate
new lasers and other loads as needed, so the picture may not show the latest revision.
Figure 5: Laser diode mounting on output terminals with interposer
Figure 5 shows an example of an Excelitas SMD laser diode mounted
with one of the interposers.
Finally, a ground pad is made available for those who wish to use the
board for alternative applications.
The recommended procedure for the use of the interposer is the following:
1. Apply solder paste to the U2 pads on the EPC9144 PCB.
2. Apply solder paste to the appropriate pads on the top side of the
interposer.
3. Carefully place the desired interposer with the bottom side facing the
top side of the EPC9144 on the U2 footprint.
4. Place the laser diode or desired load on the interposer.
5. Reow the entire assembly with the recommended temperature
prole for the solder used. The use of a reow oven that can meet the
recommended soldering specications is highly recommended. Other
reow methods may also be used based on the experience of the user.
The power loop inductance, including that of the laser diode, is a primary
factor that determines the shape of the laser pulse. Considerable eort
has been made to minimize power loop inductance while maximizing
the choice of laser diode and its orientation. The discharge caps, laser
diode or other load, and the eGaN FET must all be mounted in close
proximity to minimize inductance. As a result, the user must take care not
to damage any components when mounting the laser or changing other
components in the power loop.
The EPC9144 is capable of driving laser diodes with current pulses
can result in peak powers of several tens of watts of optical power.
Laser diodes for lidar applications may be designed with this in mind, but
thermal limitations of the laser package mean that pulse widths, duty
cycles, and pulse repetition frequency limitations must be observed.
Read laser diode data sheets carefully and follow any manufacturers’
recommendations.
MEASUREMENT CONSIDERATIONS
MMCX jacks are provided to measure several voltages in the circuit,
including gate drive input, Q1 gate voltage, Q1 drain voltage, charge
voltage of the energy storage cap. All measurement points are designed
to be terminated in 50 Ω, hence when viewing waveforms, the
oscilloscope inputs should be set to a 50 Ω input. Ideally, unused inputs
should be also terminated with a 50 Ω load to prevent the probes from
creating additional resonances. The Q1 drain voltage and the discharge
cap sense voltage have on-board terminations to greatly reduce this
eect, and in practice, the remaining resonances are small enough to
ignore in most applications. It is recommended that the user verify this
for their own requirements.
All sense measurement MMCXs, except for the shunt measurement,
use the transmission line probe principle to obtain waveform delity at
sub-ns time scales. They have been veried to produce near-identical
Bottom
Left
Breakaway
V-grooves
SMD lasers MMCX Alternate loads
Gate driver
eGaN FET
Current
shunt
Discharge
capacitors
Laser diode
or load EPC9989 interposer Recharging resistors
EPC9126
results to a Tektronix P9158 3 GHz transmission line probe. As a result
of their design, they have a built-in attenuation factor. The impedance
of the probes at the measurement node is relatively small (~1kΩ).
The user should keep this in mind if accustomed to more conventional
oscilloscope probes.
The current shunt J4 is not used at this time. A future revision may
include this functionality.
Table 2 summarizes the properties of the MMCX test points for ease
of reference.

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MODIFICATIONS
Narrow pulse generator
Many signal generators cannot produce an accurate, short pulse. The
EPC9144 includes circuitry to obtain narrow output pulses, following
a method given in Section 8.2.2.2 of the Texas Instruments LMG1020
data sheet. This method is based on the Jim Williams circuit in [REF].
This is controlled through trimmer potentiometer P1. The pulse range is
approximately ~1.2 ns to ~20 ns.The minimum width is determined from
the point at which the gate drive pulses to Q1 begin to drop out. This
boundary is determined by the LMG1020 gate driver, and may vary with
temperature or other factors. The input pulse with to the narrow pulse
generator should be at least 10 ns longer than the desired pulse width
for reliable operation. The user should consult with Texas Instruments
(Figures 7 & 8) if operating near the IC specication boundaries.
For greater exibility, e.g. when the user would like to use variable
pulse width, the user may disable the narrow pulse generator by
simply removing R27 (Fig. 6). Once done, the input to the gate drive
IC will follow the input pulse from the user’s pulse source. This allows
variable pulse generation and very high frequency operation given the
appropriate user-generated input.
Pulse sources
The EPC9144 comes with out-of-the-box support for 3.3 V logic
levels input to J5. The input includes a logic level translator U4 to
accommodate lower voltage logic, which is often used for high speed
designs. To accommodate lower voltage logic levels, simply change R18
(Fig. 6), which sets the voltage at U4 pin 5, and thereby determines the
input logic level.
For very high speed systems, dierential signaling protocols
such as LVDS or CML are commonly used. To accommodate this,
the EPC9144 has a exible dierential receiver U3, whose inputs
is available via J3. In order to make use of the dierential input
capability, the jumper on J8 must be moved from the SE position
to the DIFF position. This will disable the J5 input and enable the
J3 dierential input (Fig 6.). U3 is congured for a 100 Ω dierential
Table 2: Key properties of the MMCX test points for ease of reference
Designator PCB label Description Attenuation
factor
J6 CAP
Bus capacitor
voltage (VCHARGE on
schematic)
41 V/V
J4 SHUNT Shunt voltage Not used
Not used Q1 drain voltage
41 V/V
J7 VOUT Q1 drain voltage 41 V/V
J9 VGDIN Gate drive input 20 V/V
J10 VGS Q1 gate voltage 20 V/V
impedance with a 0.85 V DC bias oset, which should accommodate
typical LVDS transmitters. These parameters can be modied as
needed to accommodate various dierential signaling schemes.
This application note is useful to congure U3 for dierent needs.
Clamping diodes
The EPC9144 shipped congured as a dual edge control driver.
When the FET Q1 is turned o, energy stored in the stray power loop
inductance can cause a Q1 drain voltage spike to exceed the device
ratings. In order to reduce the voltage spike, a diode-connected
EPC2036 FET Q2 is used to help clamp the drain node. There are
also provisions for up to two other clamping diodes D1 and D2.
While diodes Q2, D1 and D2 can provide some protection to FET Q1
and laser U2, they have parasitic inductance and capacitance that
can reduce performance at the very fastest speeds. Hence, only Q2
is populated, and it is left to the user to determine whether they are
benecial for any particular application. D1, D2, and Q2 locations are
on the bottom side of the EPC9144 PCB.
NOTE. The EPC9144 demonstration board does not have any thermal
protection on board.
Location of
R27 J3 input (DIFF) J5 input (SE) Location of R27
Figure 6: Remove R27 to disable the onboard narrow pulse generator and
drive the gate drive from the pulse source.