Epson S1C31D50 User manual

Rev. 2.00
CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
S1C31D50/D51
Technical Manual

©
SEIKO EPSON CORPORATION 2020, All rights reserved.
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PREFACE
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 2.00)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C31D50/D51. This
document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in
the “Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the SYSPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the SYSPROT.PROT[15:0] bits
(reserved):Reserved bit. Do not alter from the initial value.
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.
Low power mode
This manual describes the low power modes as HALT mode and SLEEP mode. These terms refer to sleep
mode and deep sleep mode in the Cortex®-M0+ processor, respectively.

CONTENTS
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– Contents –
Preface......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram ..................................................................................... 1-4
1.3.2 Pin Descriptions ..................................................................................................... 1-8
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWGA) ............................................................................................... 2-1
2.1.1 Overview................................................................................................................. 2-1
2.1.2 Pins......................................................................................................................... 2-1
2.1.3 VD1 Regulator Operation Mode .............................................................................. 2-2
2.1.4 VD1 Regulator Voltage Mode .................................................................................. 2-2
2.2 System Reset Controller (SRC)....................................................................................... 2-3
2.2.1 Overview................................................................................................................. 2-3
2.2.2 Input Pin ................................................................................................................. 2-4
2.2.3 Reset Sources ........................................................................................................ 2-4
2.2.4 Initialization Conditions (Reset Groups) ................................................................. 2-5
2.3 Clock Generator (CLG).................................................................................................... 2-5
2.3.1 Overview................................................................................................................. 2-5
2.3.2 Input/Output Pins ................................................................................................... 2-6
2.3.3 Clock Sources ........................................................................................................ 2-6
2.3.4 Operations.............................................................................................................. 2-9
2.4 Operating Mode ............................................................................................................. 2-13
2.4.1 Initial Boot Sequence ............................................................................................ 2-13
2.4.2 Transition between Operating Modes ................................................................... 2-13
2.5 Interrupts........................................................................................................................ 2-15
2.6 Control Registers ........................................................................................................... 2-15
PWGA Control Register........................................................................................................ 2-15
CLG System Clock Control Register.................................................................................... 2-16
CLG Oscillation Control Register ......................................................................................... 2-17
CLG IOSC Control Register.................................................................................................. 2-18
CLG OSC1 Control Register................................................................................................. 2-18
CLG OSC3 Control Register................................................................................................. 2-19
CLG Interrupt Flag Register.................................................................................................. 2-21
CLG Interrupt Enable Register ............................................................................................. 2-21
CLG FOUT Control Register................................................................................................. 2-22
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core........................................................................................................................ 3-1
3.3 Debugger ........................................................................................................................ 3-1
3.3.1 List of Debugger Input/Output Pins ....................................................................... 3-1
3.3.2 External Connection ............................................................................................... 3-1
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-2
4.3 Flash Memory ................................................................................................................. 4-2

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4.3.1 Flash Memory Pin................................................................................................... 4-2
4.3.2 Flash Bus Access Cycle Setting............................................................................. 4-2
4.3.3 Flash Programming ................................................................................................ 4-2
4.4 RAM ................................................................................................................................ 4-3
4.5 Peripheral Circuit Control Registers................................................................................ 4-3
4.5.1 System-Protect Function ....................................................................................... 4-9
4.6 Instruction Cache............................................................................................................ 4-9
4.7 Memory Mapped Access Area For External Flash Memory .......................................... 4-10
4.8 Control Registers ........................................................................................................... 4-10
System Protect Register....................................................................................................... 4-10
CACHE Control Register ...................................................................................................... 4-10
FLASHC Flash Read Cycle Register .................................................................................... 4-10
5 Interrupt.........................................................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Offset Address (VTOR)....................................................................... 5-3
5.2.2 Priority of Interrupts................................................................................................ 5-3
5.3 Peripheral Circuit Interrupt Control ................................................................................. 5-3
5.4 NMI.................................................................................................................................. 5-4
6 DMA Controller (DMAC)...............................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 Operations ...................................................................................................................... 6-2
6.2.1 Initialization............................................................................................................. 6-2
6.3 Priority............................................................................................................................. 6-2
6.4 Data Structure................................................................................................................. 6-2
6.4.1 Transfer Source End Pointer................................................................................... 6-3
6.4.2 Transfer Destination End Pointer............................................................................ 6-3
6.4.3 Control Data ........................................................................................................... 6-4
6.5 DMA Transfer Mode ........................................................................................................ 6-5
6.5.1 Basic Transfer......................................................................................................... 6-5
6.5.2 Auto-Request Transfer ........................................................................................... 6-5
6.5.3 Ping-Pong Transfer................................................................................................. 6-6
6.5.4 Memory Scatter-Gather Transfer............................................................................ 6-7
6.5.5 Peripheral Scatter-Gather Transfer......................................................................... 6-8
6.6 DMA Transfer Cycle ........................................................................................................ 6-9
6.7 Interrupts......................................................................................................................... 6-9
6.8 Control Registers ........................................................................................................... 6-10
DMAC Status Register ......................................................................................................... 6-10
DMAC Configuration Register .............................................................................................. 6-10
DMAC Control Data Base Pointer Register.......................................................................... 6-11
DMAC Alternate Control Data Base Pointer Register .......................................................... 6-11
DMAC Software Request Register ....................................................................................... 6-11
DMAC Request Mask Set Register ...................................................................................... 6-11
DMAC Request Mask Clear Register ................................................................................... 6-12
DMAC Enable Set Register .................................................................................................. 6-12
DMAC Enable Clear Register ............................................................................................... 6-12
DMAC Primary-Alternate Set Register ................................................................................. 6-12
DMAC Primary-Alternate Clear Register .............................................................................. 6-13
DMAC Priority Set Register .................................................................................................. 6-13
DMAC Priority Clear Register ............................................................................................... 6-13
DMAC Error Interrupt Flag Register ..................................................................................... 6-13
DMAC Transfer Completion Interrupt Flag Register............................................................. 6-14

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DMAC Transfer Completion Interrupt Enable Set Register .................................................. 6-14
DMAC Transfer Completion Interrupt Enable Clear Register ............................................... 6-14
DMAC Error Interrupt Enable Set Register........................................................................... 6-14
DMAC Error Interrupt Enable Clear Register........................................................................ 6-15
7 I/O Ports (PPORT).........................................................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 I/O Cell Structure and Functions..................................................................................... 7-2
7.2.1 Schmitt Input.......................................................................................................... 7-2
7.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell ........................................................ 7-3
7.2.3 Pull-Up/Pull-Down.................................................................................................. 7-3
7.2.4 CMOS Output and High Impedance State............................................................. 7-3
7.3 Clock Settings................................................................................................................. 7-3
7.3.1 PPORT Operating Clock......................................................................................... 7-3
7.3.2 Clock Supply in SLEEP Mode ................................................................................ 7-3
7.3.3 Clock Supply During Debugging............................................................................ 7-4
7.4 Operations ...................................................................................................................... 7-4
7.4.1 Initialization............................................................................................................. 7-4
7.4.2 Port Input/Output Control ...................................................................................... 7-5
7.5 Interrupts......................................................................................................................... 7-6
7.6 Control Registers ............................................................................................................ 7-7
PxPort Data Register ............................................................................................................ 7-7
PxPort Enable Register......................................................................................................... 7-7
PxPort Pull-up/down Control Register ................................................................................. 7-8
PxPort Interrupt Flag Register .............................................................................................. 7-8
PxPort Interrupt Control Register ......................................................................................... 7-8
PxPort Chattering Filter Enable Register.............................................................................. 7-9
PxPort Mode Select Register ............................................................................................... 7-9
PxPort Function Select Register........................................................................................... 7-9
P Port Clock Control Register .............................................................................................. 7-10
P Port Interrupt Flag Group Register.................................................................................... 7-11
7.7 Control Register and Port Function Configuration of this IC ......................................... 7-12
7.7.1 P0 Port Group ....................................................................................................... 7-12
7.7.2 P1 Port Group ....................................................................................................... 7-14
7.7.3 P2 Port Group ....................................................................................................... 7-17
7.7.4 P3 Port Group ....................................................................................................... 7-19
7.7.5 P4 Port Group ....................................................................................................... 7-21
7.7.6 P5 Port Group ....................................................................................................... 7-24
7.7.7 P6 Port Group ....................................................................................................... 7-26
7.7.8 P7 Port Group ....................................................................................................... 7-28
7.7.9 P8 Port Group ....................................................................................................... 7-31
7.7.10 P9 Port Group ..................................................................................................... 7-33
7.7.11 Pa Port Group ..................................................................................................... 7-35
7.7.12 Pd Port Group ..................................................................................................... 7-37
7.7.13 Common Registers between Port Groups .......................................................... 7-39
8 Universal Port Multiplexer (UPMUX)...........................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Peripheral Circuit I/O Function Assignment.................................................................... 8-1
8.3 Control Registers ............................................................................................................ 8-2
Pxy–xz Universal Port Multiplexer Setting Register............................................................... 8-2
9 Watchdog Timer (WDT2)..............................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Clock Settings................................................................................................................. 9-1

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9.2.1 WDT2 Operating Clock .......................................................................................... 9-1
9.2.2 Clock Supply in DEBUG Mode............................................................................... 9-1
9.3 Operations ...................................................................................................................... 9-2
9.3.1 WDT2 Control......................................................................................................... 9-2
9.3.2 Operations in HALT and SLEEP Modes ................................................................. 9-3
9.4 Control Registers ............................................................................................................ 9-3
WDT2 Clock Control Register ............................................................................................... 9-3
WDT2 Control Register.......................................................................................................... 9-4
WDT2 Counter Compare Match Register.............................................................................. 9-4
10 Real-Time Clock (RTCA) ...........................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Output Pin and External Connection ........................................................................... 10-1
10.2.1 Output Pin ........................................................................................................... 10-1
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 RTCA Operating Clock........................................................................................ 10-2
10.3.2 Theoretical Regulation Function.......................................................................... 10-2
10.4 Operations ................................................................................................................... 10-3
10.4.1 RTCA Control ..................................................................................................... 10-3
10.4.2 Real-Time Clock Counter Operations ................................................................. 10-4
10.4.3 Stopwatch Control .............................................................................................. 10-4
10.4.4 Stopwatch Count-up Pattern .............................................................................. 10-4
10.5 Interrupts...................................................................................................................... 10-5
10.6 Control Registers ......................................................................................................... 10-6
RTCA Control Register (Low Byte) ....................................................................................... 10-6
RTCA Control Register (High Byte)....................................................................................... 10-7
RTCA Second Alarm Register .............................................................................................. 10-7
RTCA Hour/Minute Alarm Register....................................................................................... 10-8
RTCA Stopwatch Control Register....................................................................................... 10-8
RTCA Second/1Hz Register ................................................................................................. 10-9
RTCA Hour/Minute Register................................................................................................ 10-10
RTCA Month/Day Register .................................................................................................. 10-11
RTCA Year/Week Register ................................................................................................... 10-11
RTCA Interrupt Flag Register .............................................................................................. 10-12
RTCA Interrupt Enable Register .......................................................................................... 10-13
11 Supply Voltage Detector (SVD3)...............................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input Pins and External Connection ............................................................................ 11-2
11.2.1 Input Pins ............................................................................................................ 11-2
11.2.2 External Connection ............................................................................................ 11-2
11.3 Clock Settings.............................................................................................................. 11-2
11.3.1 SVD3 Operating Clock ........................................................................................ 11-2
11.3.2 Clock Supply in SLEEP Mode ............................................................................. 11-2
11.3.3 Clock Supply in DEBUG Mode............................................................................ 11-3
11.4 Operations ................................................................................................................... 11-3
11.4.1 SVD3 Control....................................................................................................... 11-3
11.4.2 SVD3 Operations................................................................................................. 11-4
11.5 SVD3 Interrupt and Reset ............................................................................................ 11-4
11.5.1 SVD3 Interrupt..................................................................................................... 11-4
11.5.2 SVD3 Reset ......................................................................................................... 11-5
11.6 Control Registers ......................................................................................................... 11-5
SVD3 Clock Control Register ............................................................................................... 11-5
SVD3 Control Register.......................................................................................................... 11-6
SVD3 Status and Interrupt Flag Register ............................................................................. 11-7

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SVD3 Interrupt Enable Register............................................................................................ 11-8
12 16-bit Timers (T16).....................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input Pin....................................................................................................................... 12-1
12.3 Clock Settings.............................................................................................................. 12-2
12.3.1 T16 Operating Clock ........................................................................................... 12-2
12.3.2 Clock Supply in SLEEP Mode ............................................................................. 12-2
12.3.3 Clock Supply During Debugging......................................................................... 12-2
12.3.4 Event Counter Clock ........................................................................................... 12-2
12.4 Operations ................................................................................................................... 12-2
12.4.1 Initialization.......................................................................................................... 12-2
12.4.2 Counter Underflow .............................................................................................. 12-3
12.4.3 Operations in Repeat Mode ................................................................................ 12-3
12.4.4 Operations in One-shot Mode............................................................................. 12-3
12.4.5 Counter Value Read ............................................................................................ 12-4
12.5 Interrupt........................................................................................................................ 12-4
12.6 Control Registers ......................................................................................................... 12-4
T16 Ch.nClock Control Register.......................................................................................... 12-4
T16 Ch.nMode Register ...................................................................................................... 12-5
T16 Ch.nControl Register.................................................................................................... 12-5
T16 Ch.nReload Data Register............................................................................................ 12-6
T16 Ch.nCounter Data Register .......................................................................................... 12-6
T16 Ch.nInterrupt Flag Register .......................................................................................... 12-6
T16 Ch.nInterrupt Enable Register ...................................................................................... 12-7
13 UART (UART3)............................................................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins ..................................................................................... 13-2
13.2.2 External Connections .......................................................................................... 13-2
13.2.3 Input Pin Pull-Up Function .................................................................................. 13-2
13.2.4 Output Pin Open-Drain Output Function ........................................................... 13-2
13.2.5 Input/Output Signal Inverting Function ............................................................... 13-2
13.3 Clock Settings.............................................................................................................. 13-2
13.3.1 UART3 Operating Clock...................................................................................... 13-2
13.3.2 Clock Supply in SLEEP Mode ............................................................................. 13-3
13.3.3 Clock Supply During Debugging......................................................................... 13-3
13.3.4 Baud Rate Generator .......................................................................................... 13-3
13.4 Data Format ................................................................................................................. 13-3
13.5 Operations ................................................................................................................... 13-4
13.5.1 Initialization.......................................................................................................... 13-4
13.5.2 Data Transmission ............................................................................................... 13-5
13.5.3 Data Reception.................................................................................................... 13-6
13.5.4 IrDA Interface ...................................................................................................... 13-7
13.5.5 Carrier Modulation............................................................................................... 13-8
13.6 Receive Errors.............................................................................................................. 13-9
13.6.1 Framing Error....................................................................................................... 13-9
13.6.2 Parity Error........................................................................................................... 13-9
13.6.3 Overrun Error....................................................................................................... 13-9
13.7 Interrupts..................................................................................................................... 13-10
13.8 DMA Transfer Requests .............................................................................................. 13-10
13.9 Control Registers ........................................................................................................ 13-11
UART3 Ch.nClock Control Register ................................................................................... 13-11

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UART3 Ch.nMode Register ................................................................................................ 13-11
UART3 Ch.nBaud–Rate Register........................................................................................ 13-13
UART3 Ch.nControl Register.............................................................................................. 13-13
UART3 Ch.nTransmit Data Register ................................................................................... 13-14
UART3 Ch.nReceive Data Register .................................................................................... 13-14
UART3 Ch.nStatus and Interrupt Flag Register ................................................................. 13-14
UART3 Ch.nInterrupt Enable Register................................................................................ 13-15
UART3 Ch.nTransmit Buffer Empty DMA Request Enable Register .................................. 13-16
UART3 Ch.nReceive Buffer One Byte Full DMA Request Enable Register........................ 13-16
UART3 Ch.nCarrier Waveform Register ............................................................................. 13-16
14 Synchronous Serial Interface (SPIA)........................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins and External Connections .............................................................. 14-2
14.2.1 List of Input/Output Pins ..................................................................................... 14-2
14.2.2 External Connections .......................................................................................... 14-2
14.2.3 Pin Functions in Master Mode and Slave Mode ................................................. 14-3
14.2.4 Input Pin Pull-Up/Pull-Down Function ............................................................... 14-3
14.3 Clock Settings.............................................................................................................. 14-3
14.3.1 SPIA Operating Clock ......................................................................................... 14-3
14.3.2 Clock Supply During Debugging......................................................................... 14-4
14.3.3 SPI Clock (SPICLKn) Phase and Polarity ............................................................ 14-4
14.4 Data Format ................................................................................................................. 14-5
14.5 Operations ................................................................................................................... 14-5
14.5.1 Initialization.......................................................................................................... 14-5
14.5.2 Data Transmission in Master Mode..................................................................... 14-6
14.5.3 Data Reception in Master Mode ......................................................................... 14-8
14.5.4 Terminating Data Transfer in Master Mode ........................................................ 14-10
14.5.5 Data Transfer in Slave Mode .............................................................................. 14-10
14.5.6 Terminating Data Transfer in Slave Mode........................................................... 14-11
14.6 Interrupts..................................................................................................................... 14-12
14.7 DMA Transfer Requests .............................................................................................. 14-13
14.8 Control Registers ........................................................................................................ 14-13
SPIA Ch.nMode Register.................................................................................................... 14-13
SPIA Ch.nControl Register ................................................................................................. 14-14
SPIA Ch.nTransmit Data Register....................................................................................... 14-15
SPIA Ch.nReceive Data Register........................................................................................ 14-15
SPIA Ch.nInterrupt Flag Register ....................................................................................... 14-15
SPIA Ch.nInterrupt Enable Register ................................................................................... 14-16
SPIA Ch.nTransmit Buffer Empty DMA Request Enable Register...................................... 14-16
SPIA Ch.nReceive Buffer Full DMA Request Enable Register ........................................... 14-16
15 Quad Synchronous Serial Interface (QSPI) .............................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins and External Connections .............................................................. 15-2
15.2.1 List of Input/Output Pins ..................................................................................... 15-2
15.2.2 External Connections .......................................................................................... 15-2
15.2.3 Pin Functions in Master Mode and Slave Mode ................................................. 15-6
15.2.4 Input Pin Pull-Up/Pull-Down Function ............................................................... 15-6
15.3 Clock Settings.............................................................................................................. 15-6
15.3.1 QSPI Operating Clock ......................................................................................... 15-6
15.3.2 Clock Supply During Debugging......................................................................... 15-7
15.3.3 QSPI Clock (QSPICLKn) Phase and Polarity....................................................... 15-7
15.4 Data Format ................................................................................................................. 15-8
15.5 Operations ................................................................................................................... 15-9

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15.5.1 Register Access Mode ........................................................................................ 15-9
15.5.2 Memory Mapped Access Mode ......................................................................... 15-10
15.5.3 Initialization......................................................................................................... 15-11
15.5.4 Data Transmission in Master Mode.................................................................... 15-12
15.5.5 Data Reception in Register Access Master Mode ............................................. 15-14
15.5.6 Data Reception in Memory Mapped Access Mode ........................................... 15-17
15.5.7 Terminating Memory Mapped Access Operations............................................. 15-25
15.5.8 Terminating Data Transfer in Master Mode ........................................................ 15-25
15.5.9 Data Transfer in Slave Mode .............................................................................. 15-26
15.5.10 Terminating Data Transfer in Slave Mode......................................................... 15-27
15.6 Interrupts..................................................................................................................... 15-27
15.7 DMA Transfer Requests .............................................................................................. 15-28
15.8 Control Registers ........................................................................................................ 15-29
QSPI Ch.nMode Register ................................................................................................... 15-29
QSPI Ch.nControl Register................................................................................................. 15-31
QSPI Ch.nTransmit Data Register ...................................................................................... 15-32
QSPI Ch.nReceive Data Register ....................................................................................... 15-32
QSPI Ch.nInterrupt Flag Register....................................................................................... 15-32
QSPI Ch.nInterrupt Enable Register................................................................................... 15-33
QSPI Ch.nTransmit Buffer Empty DMA Request Enable Register ..................................... 15-33
QSPI Ch.nReceive Buffer Full DMA Request Enable Register........................................... 15-34
QSPI Ch.n FIFO Data Ready DMA Request Enable Register ............................................. 15-34
QSPI Ch.nMemory Mapped Access Configuration Register 1 .......................................... 15-34
QSPI Ch.nRemapping Start Address High Register .......................................................... 15-35
QSPI Ch.nMemory Mapped Access Configuration Register 2 .......................................... 15-35
QSPI Ch.nMode Byte Register........................................................................................... 15-37
16 I2C (I2C).......................................................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Input/Output Pins and External Connections .............................................................. 16-2
16.2.1 List of Input/Output Pins ..................................................................................... 16-2
16.2.2 External Connections .......................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-3
16.3.1 I2C Operating Clock............................................................................................ 16-3
16.3.2 Clock Supply During Debugging......................................................................... 16-3
16.3.3 Baud Rate Generator .......................................................................................... 16-3
16.4 Operations ................................................................................................................... 16-4
16.4.1 Initialization.......................................................................................................... 16-4
16.4.2 Data Transmission in Master Mode..................................................................... 16-5
16.4.3 Data Reception in Master Mode ......................................................................... 16-7
16.4.4 10-bit Addressing in Master Mode..................................................................... 16-10
16.4.5 Data Transmission in Slave Mode ...................................................................... 16-11
16.4.6 Data Reception in Slave Mode........................................................................... 16-13
16.4.7 Slave Operations in 10-bit Address Mode ......................................................... 16-15
16.4.8 Automatic Bus Clearing Operation..................................................................... 16-15
16.4.9 Error Detection ................................................................................................... 16-16
16.5 Interrupts..................................................................................................................... 16-17
16.6 DMA Transfer Requests .............................................................................................. 16-18
16.7 Control Registers ........................................................................................................ 16-18
I2C Ch.nClock Control Register ......................................................................................... 16-18
I2C Ch.nMode Register ...................................................................................................... 16-19
I2C Ch.nBaud-Rate Register.............................................................................................. 16-19
I2C Ch.nOwn Address Register.......................................................................................... 16-20
I2C Ch.nControl Register ................................................................................................... 16-20
I2C Ch.nTransmit Data Register ......................................................................................... 16-21

CONTENTS
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation ix
(Rev. 2.00)
I2C Ch.nReceive Data Register.......................................................................................... 16-21
I2C Ch.nStatus and Interrupt Flag Register ....................................................................... 16-22
I2C Ch.nInterrupt Enable Register...................................................................................... 16-23
I2C Ch.nTransmit Buffer Empty DMA Request Enable Register ........................................ 16-24
I2C Ch.nReceive Buffer Full DMA Request Enable Register.............................................. 16-24
17 16-bit PWM Timers (T16B) ........................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Input/Output Pins......................................................................................................... 17-2
17.3 Clock Settings.............................................................................................................. 17-3
17.3.1 T16B Operating Clock......................................................................................... 17-3
17.3.2 Clock Supply in SLEEP Mode ............................................................................. 17-3
17.3.3 Clock Supply During Debugging......................................................................... 17-3
17.3.4 Event Counter Clock ........................................................................................... 17-3
17.4 Operations ................................................................................................................... 17-4
17.4.1 Initialization.......................................................................................................... 17-4
17.4.2 Counter Block Operations................................................................................... 17-5
17.4.3 Comparator/Capture Block Operations .............................................................. 17-8
17.4.4 TOUT Output Control ......................................................................................... 17-17
17.5 Interrupt....................................................................................................................... 17-23
17.6 DMA Transfer Requests .............................................................................................. 17-23
17.7 Control Registers ........................................................................................................ 17-23
T16B Ch.nClock Control Register ...................................................................................... 17-23
T16B Ch.nCounter Control Register................................................................................... 17-24
T16B Ch.nMax Counter Data Register............................................................................... 17-25
T16B Ch.nTimer Counter Data Register............................................................................. 17-25
T16B Ch.nCounter Status Register .................................................................................... 17-26
T16B Ch.nInterrupt Flag Register....................................................................................... 17-27
T16B Ch.nInterrupt Enable Register................................................................................... 17-28
T16B Ch.nComparator/Capture mControl Register .......................................................... 17-29
T16B Ch.nCompare/Capture mData Register................................................................... 17-31
T16B Ch.nCounter Max/Zero DMA Request Enable Register ........................................... 17-32
T16B Ch.nCompare/Capture mDMA Request Enable Register........................................ 17-32
18 IR Remote Controller (REMC3) ................................................................................18-1
18.1 Overview ...................................................................................................................... 18-1
18.2 Output Pins and External Connections........................................................................ 18-1
18.2.1 List of Output Pins............................................................................................... 18-1
18.2.2 External Connections .......................................................................................... 18-2
18.3 Clock Settings.............................................................................................................. 18-2
18.3.1 REMC3 Operating Clock ..................................................................................... 18-2
18.3.2 Clock Supply in SLEEP Mode ............................................................................. 18-2
18.3.3 Clock Supply During Debugging......................................................................... 18-2
18.4 Operations ................................................................................................................... 18-2
18.4.1 Initialization.......................................................................................................... 18-2
18.4.2 Data Transmission Procedures............................................................................ 18-3
18.4.3 REMO Output Waveform..................................................................................... 18-3
18.4.4 Continuous Data Transmission and Compare Buffers ........................................ 18-5
18.5 Interrupts...................................................................................................................... 18-6
18.6 Application Example: Driving EL Lamp........................................................................ 18-7
18.7 Control Registers ......................................................................................................... 18-7
REMC3 Clock Control Register............................................................................................ 18-7
REMC3 Data Bit Counter Control Register .......................................................................... 18-8
REMC3 Data Bit Counter Register ....................................................................................... 18-9
REMC3 Data Bit Active Pulse Length Register ................................................................... 18-10

CONTENTS
xSeiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
REMC3 Data Bit Length Register........................................................................................ 18-10
REMC3 Status and Interrupt Flag Register ......................................................................... 18-10
REMC3 Interrupt Enable Register ....................................................................................... 18-11
REMC3 Carrier Waveform Register..................................................................................... 18-11
REMC3 Carrier Modulation Control Register ...................................................................... 18-11
19 12-bit A/D Converter (ADC12A)................................................................................19-1
19.1 Overview ...................................................................................................................... 19-1
19.2 Input Pins and External Connections........................................................................... 19-2
19.2.1 List of Input Pins.................................................................................................. 19-2
19.2.2 External Connections .......................................................................................... 19-2
19.3 Clock Settings.............................................................................................................. 19-2
19.3.1 ADC12A Operating Clock.................................................................................... 19-2
19.3.2 Sampling Time..................................................................................................... 19-2
19.4 Operations ................................................................................................................... 19-3
19.4.1 Initialization.......................................................................................................... 19-3
19.4.2 Conversion Start Trigger Source ......................................................................... 19-3
19.4.3 Conversion Mode and Analog Input Pin Settings ............................................... 19-4
19.4.4 A/D Conversion Operations and Control Procedures ......................................... 19-4
19.5 Interrupts...................................................................................................................... 19-6
19.6 DMA Transfer Requests ............................................................................................... 19-6
19.7 Control Registers ......................................................................................................... 19-7
ADC12A Ch.nControl Register ............................................................................................ 19-7
ADC12A Ch.nTrigger/Analog Input Select Register ............................................................ 19-8
ADC12A Ch.nConfiguration Register .................................................................................. 19-9
ADC12A Ch.nInterrupt Flag Register ................................................................................. 19-10
ADC12A Ch.nInterrupt Enable Register ............................................................................. 19-10
ADC12A Ch.nDMA Request Enable Register m................................................................. 19-11
ADC12A Ch.nResult Register............................................................................................. 19-11
20 R/F Converter (RFC) ..................................................................................................20-1
20.1 Overview ...................................................................................................................... 20-1
20.2 Input/Output Pins and External Connections .............................................................. 20-2
20.2.1 List of Input/Output Pins ..................................................................................... 20-2
20.2.2 External Connections .......................................................................................... 20-2
20.3 Clock Settings.............................................................................................................. 20-3
20.3.1 RFC Operating Clock .......................................................................................... 20-3
20.3.2 Clock Supply in SLEEP Mode ............................................................................. 20-3
20.3.3 Clock Supply in DEBUG Mode............................................................................ 20-3
20.4 Operations ................................................................................................................... 20-3
20.4.1 Initialization.......................................................................................................... 20-3
20.4.2 Operating Modes................................................................................................. 20-4
20.4.3 RFC Counters...................................................................................................... 20-4
20.4.4 Converting Operations and Control Procedure................................................... 20-5
20.4.5 CR Oscillation Frequency Monitoring Function................................................... 20-7
20.5 Interrupts...................................................................................................................... 20-7
20.6 Control Registers ......................................................................................................... 20-8
RFC Ch.nClock Control Register......................................................................................... 20-8
RFC Ch.nControl Register................................................................................................... 20-8
RFC Ch.nOscillation Trigger Register.................................................................................. 20-9
RFC Ch.nMeasurement Counter Low and High Registers................................................. 20-10
RFC Ch.nTime Base Counter Low and High Registers...................................................... 20-10
RFC Ch.nInterrupt Flag Register ........................................................................................ 20-11
RFC Ch.nInterrupt Enable Register .................................................................................... 20-11

CONTENTS
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation xi
(Rev. 2.00)
21 HW Processor (HWP) and Sound Output ................................................................21-1
21.1 Overview ...................................................................................................................... 21-1
21.2 Output Pins and External Connections........................................................................ 21-3
21.2.1 List of Output Pins............................................................................................... 21-3
21.2.2 External Connections .......................................................................................... 21-3
21.3 Clock Settings.............................................................................................................. 21-4
21.3.1 HWP Operating Clock ......................................................................................... 21-4
21.3.2 Clock Supply in SLEEP Mode ............................................................................. 21-4
21.3.3 Clock Supply in DEBUG Mode............................................................................ 21-4
21.4 Operations ................................................................................................................... 21-4
21.4.1 Sound Play Function ........................................................................................... 21-4
21.4.2 Memory Check Function .................................................................................... 21-13
21.5 Interrupts..................................................................................................................... 21-17
21.6 HWP Internal Registers............................................................................................... 21-18
21.6.1 Sound Play Function Registers .......................................................................... 21-18
Function ID Register............................................................................................................ 21-18
Interrupt Mask Register ....................................................................................................... 21-18
ROM Address Register........................................................................................................ 21-19
ROM Size Register .............................................................................................................. 21-19
Key Code Register............................................................................................................... 21-19
Ch.nCommand Register..................................................................................................... 21-20
Ch.n Sentence Number Setting Register ............................................................................ 21-20
Ch.nVolume Control Register ............................................................................................. 21-20
Ch.nRepeat Control Register ............................................................................................. 21-21
Ch.0 Playback Speed Conversion Register ........................................................................ 21-21
Ch.nState Monitor Register................................................................................................ 21-22
Error Status Register ........................................................................................................... 21-22
Operating Status Register ................................................................................................... 21-22
Version Number Register..................................................................................................... 21-22
21.6.2 Memory Check Function Register...................................................................... 21-23
Function ID Register............................................................................................................ 21-23
Interrupt Mask Register ....................................................................................................... 21-23
Memory Address Register................................................................................................... 21-23
Memory Size Register ......................................................................................................... 21-24
Initial Value Setting Register ................................................................................................ 21-24
Command Register ............................................................................................................. 21-24
State Monitor Register......................................................................................................... 21-24
Error Status Register ........................................................................................................... 21-25
Operating Status Register ................................................................................................... 21-25
Calculation Result Register ................................................................................................. 21-25
Version Number Register..................................................................................................... 21-25
21.7 Control Registers ........................................................................................................ 21-26
HWP Control Register ......................................................................................................... 21-26
HWP Interrupt Flag Register................................................................................................ 21-26
HWP Interrupt Enable Register ........................................................................................... 21-26
HWP Command Trigger Register ........................................................................................ 21-26
SDAC Clock Control Register.............................................................................................. 21-27
SDAC Control Register........................................................................................................ 21-27
SDAC Mode Register .......................................................................................................... 21-28
SDAC Data Register ............................................................................................................ 21-28
SDAC Interrupt Flag Register .............................................................................................. 21-28
SDAC Interrupt Enable Register.......................................................................................... 21-29
22 Electrical Characteristics .........................................................................................22-1
22.1 Absolute Maximum Ratings ......................................................................................... 22-1
22.2 Recommended Operating Conditions ......................................................................... 22-1

CONTENTS
xii Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
22.3 Current Consumption................................................................................................... 22-2
22.4 System Reset Controller (SRC) Characteristics........................................................... 22-4
22.5 Clock Generator (CLG) Characteristics........................................................................ 22-5
22.6 Flash Memory Characteristics ..................................................................................... 22-8
22.7 Input/Output Port (PPORT) Characteristics ................................................................. 22-8
22.8 Supply Voltage Detector (SVD3) Characteristics ......................................................... 22-9
22.9 UART (UART3) Characteristics ................................................................................... 22-11
22.10 Synchronous Serial Interface (SPIA) Characteristics ................................................ 22-11
22.11 Quad Synchronous Serial Interface (QSPI) Characteristics...................................... 22-13
22.12 I2C (I2C) Characteristics............................................................................................ 22-13
22.13 12-bit A/D Converter (ADC12A) Characteristics ....................................................... 22-14
22.14 R/F Converter (RFC) Characteristics......................................................................... 22-15
23 Basic External Connection Diagram .......................................................................23-1
24 Package......................................................................................................................24-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x0020 0000 System Register (SYS)............................................. AP-A-1
0x0020 0020 Power Generator (PWGA) ........................................ AP-A-1
0x0020 0040–0x0020 0050 Clock Generator (CLG)............................................. AP-A-1
0x0020 0080 Cache Controller (CACHE)....................................... AP-A-2
0x0020 00a0–0x0020 00a4 Watchdog Timer (WDT2).......................................... AP-A-2
0x0020 00c0–0x0020 00d2 Real-time Clock (RTCA) ........................................... AP-A-3
0x0020 0100–0x0020 0106 Supply Voltage Detector (SVD3) .............................. AP-A-4
0x0020 0160–0x0020 016c 16-bit Timer (T16) Ch.0 ............................................ AP-A-5
0x0020 01b0 Flash Controller (FLASHC) ....................................... AP-A-5
0x0020 0200–0x0020 02e2 I/O Ports (PPORT) .................................................... AP-A-6
0x0020 0300–0x0020 031e Universal Port Multiplexer (UPMUX) ....................... AP-A-28
0x0020 0380–0x0020 0394 UART (UART3) Ch.0................................................ AP-A-30
0x0020 03a0–0x0020 03ac 16-bit Timer (T16) Ch.1 ........................................... AP-A-31
0x0020 03b0–0x0020 03be Synchronous Serial Interface (SPIA) Ch.0............... AP-A-32
0x0020 03c0–0x0020 03d6 I2C (I2C) Ch.0 .......................................................... AP-A-32
0x0020 0400–0x0020 042c 16-bit PWM Timer (T16B) Ch.0............................... AP-A-34
0x0020 0440–0x0020 046c 16-bit PWM Timer (T16B) Ch.1............................... AP-A-36
0x0020 0480–0x0020 048c 16-bit Timer (T16) Ch.3 ........................................... AP-A-38
0x0020 04a0–0x0020 04ac 16-bit Timer (T16) Ch.4 ........................................... AP-A-39
0x0020 04c0–0x0020 04cc 16-bit Timer (T16) Ch.5 ........................................... AP-A-39
0x0020 04d0–0x0020 04de Synchronous Serial Interface (SPIA) Ch.2............... AP-A-40
0x0020 0600–0x0020 0614 UART (UART3) Ch.1................................................ AP-A-41
0x0020 0620–0x0020 0634 UART (UART3) Ch.2................................................ AP-A-42
0x0020 0660–0x0020 066c 16-bit Timer (T16) Ch.6 ........................................... AP-A-43
0x0020 0670–0x0020 067e Synchronous Serial Interface (SPIA) Ch.1............... AP-A-44
0x0020 0680–0x0020 068c 16-bit Timer (T16) Ch.2 ........................................... AP-A-45
0x0020 0690–0x0020 06a8 Quad Synchronous Serial Interface (QSPI) Ch.0 .... AP-A-45
0x0020 06c0–0x0020 06d6 I2C (I2C) Ch.1 .......................................................... AP-A-46
0x0020 06e0–0x0020 06f6 I2C (I2C) Ch.2 .......................................................... AP-A-48
0x0020 0720–0x0020 0732 IR Remote Controller (REMC3) ............................... AP-A-49
0x0020 0780–0x0020 078c 16-bit Timer (T16) Ch.7 ........................................... AP-A-50
0x0020 07a0–0x0020 07bc 12-bit A/D Converter (ADC12A) Ch.0...................... AP-A-50
0x0020 0840–0x0020 0850 R/F Converter (RFC) Ch.0 ....................................... AP-A-51
0x0020 0860–0x0020 086a Sound DAC (SDAC)................................................. AP-A-52
0x0020 08a0–0x0020 08a8 HW Processor (HWP).............................................. AP-A-53
0x0020 1000–0x0020 2014 DMA Controller (DMAC).......................................... AP-A-53

CONTENTS
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation xiii
(Rev. 2.00)
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions ............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Revision History

1 OVERVIEW
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 1-1
(Rev. 2.00)
1 Overview
1.1 Features
The S1C31D50/D51 is a 32-bit Arm®Cortex®-M0+ MCU, which integrates a specific hardware block called the
HW Processor. The HW Processor can perform 2-channel Voice/Audio playback, Voice Speed Conversion, and
Self Memory Check without using any CPU resource. With the HW Processor, a low memory footprint and multi-
language support are achievable because of its integrated high-compression algorithm for voice and audio. The
S1C31D50/D51 is suitable for home electronics, white goods, and battery-based products, which require a voice
and audio playback function. Furthermore, the S1C31D51 can realize a voice and audio playback function with a
buzzer and a small number of external components without using an external audio amplifier.
Table 1.1.1 Features
S1C31D50/D51 lineup 48-pin package 64-pin package 80-pin package 100-pin package
CPU
CPU core Arm®32-bit RISC CPU core Cortex®-M0+
Other Serial-wire debug ports (SW-DP) and a micro trace buffer (MTB) included
Embedded Flash memory
Capacity 192K bytes (for both instructions and data)
Erase/program count 1,000 times (min.) *When being programmed by the dedicated flash loader
Other On-board programming function
Flash programming voltage can be generated internally.
Embedded RAMs
General-purpose RAM S1C31D50: 8K bytes
S1C31D51: 10K bytes
Voice RAM S1C31D50: 14K bytes (Usable as a general-purpose RAM when the HW processor is inactive.)
S1C31D51: 12K bytes (Usable as a general-purpose RAM when the HW processor is inactive.)
Instruction cache 512 bytes
HW processor (HWP)
Sound play function
Sound algorithm EPSON high quality and high compression algorithm (EOV: EPSON Original Sound Format)
Playback channels 2 channels with mixing supported (e.g. Ch.0: voice, Ch.1: BGM)
Sampling frequency 15.625 kHz
Bitrate 16/24/32/40 kbps
Voice speed conversion 75% to 125% (5% steps)
Sound output Speaker output (S1C31D50/D51) and buzzer output (S1C31D51)
Memory check function
Embedded RAM check Read/write check, March-C
Embedded Flash check Checksum, CRC
External QSPI-Flash check Checksum, CRC
Sound DAC (SDAC)
Sampling frequency 15.625 kHz
Serial interfaces
UART (UART3) 3 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Infrared communication carrier modulation output function
Synchronous serial interface (SPIA) 3 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
Quad synchronous serial interface
(QSPI)
1 channel
Supports single, dual, and quad transfer modes.
Low CPU overhead memory mapped access mode that can directly read data from the exter-
nal flash memory with XIP (eXecute-In-Place) mode.
I2C (I2C) 3 channels
Baud-rate generator included
DMA controller (DMAC)
Number of channels 4 channels
Data transfer path Memory to memory, memory to peripheral, and peripheral to memory
Transfer mode Basic, ping-pong, scatter-gather
DMA trigger source UART3, SPIA, QSPI, I2C, T16B, ADC12A, and software
Clock generator (CLG)
System clock source 4 sources (IOSC/OSC1/OSC3/EXOSC)
System clock frequency
(operating frequency)
VD1 voltage mode = mode0: 16 MHz (max.)
VD1 voltage mode = mode1: 1.8 MHz (max.)

1 OVERVIEW
1-2 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
S1C31D50/D51 lineup 48-pin package 64-pin package 80-pin package 100-pin package
Clock generator (CLG)
IOSC oscillator circuit
(boot clock source)
VD1 voltage mode = mode0: 8/2/1 MHz (typ.) software selectable
VD1 voltage mode = mode1: 1.8/0.9 MHz (typ.) software selectable
10 µs (typ.) starting time (time from cancelation of SLEEP state to vector table read by the CPU)
OSC1 oscillator circuit 32.768 kHz (typ.) crystal oscillator
32kHz (typ.) embedded oscillator
Oscillation stop detection circuit included
OSC3 oscillator circuit 16 MHz (max.) crystal/ceramic oscillator
16/8/4 MHz (typ.) embedded oscillator
EXOSC clock input 16 MHz (max.) square or sine wave input
Other Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
I/O port (PPORT)
Number of general-purpose I/O ports 39 bits (max.) 55 bits (max.) 71 bits (max.) 91 bits (max.)
Pins are shared with the peripheral I/O.
Number of input interrupt ports 35 bits (max.) 51 bits (max.) 66 bits (max.) 85 bits (max.)
Number of ports that support universal
port multiplexer (UPMUX)
16 bits 24 bits 27 bits 32 bits
A peripheral circuit I/O function selected via software can be assigned to each port.
Timers
Watchdog timer (WDT2) Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
Real-time clock (RTCA) 128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
16-bit timer (T16) 8 channels
Generates the SPIA and QSPI master clocks, and the ADC12A operating clock/trigger signal.
16-bit PWM timer (T16B) 2 channels
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 4 ports/channel
Supply voltage detector (SVD3)
Number of channels 1 channel
Detection voltage VDD or an external voltage (2 external detection ports are available.)
Detection level VDD: 28 levels (1.8 to 5.0 V)/external voltage: 32 levels (1.2 to 5.0 V)
Other Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
12-bit A/D converter (ADC12A)
Conversion method Successive approximation type
Resolution 12 bits
Number of conversion channels 1 channel
Number of analog signal inputs 5 ports/channel 7 ports/channel 8 ports/channel 8 ports/channel
R/F converter (RFC)
Conversion method CR oscillation type with 24-bit counters
Number of conversion channels 1 channel (Up to two sensors can be connected.)
Supported sensors DC-bias resistive sensors
IR remote controller (REMC3)
Number of transmitter channels 1 channel
Other EL lamp drive waveform can be generated (by the hardware) for an application example.
Output inversion function
Reset
#RESET pin Reset when the reset pin is set to low.
Power-on reset Reset at power on.
Brown-out reset Reset when the power supply voltage drops (when VDD ≤ 1.45 V (typ.) is detected).
Watchdog timer reset Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Supply voltage detector reset Reset when the supply voltage detector detects the set voltage level (can be enabled/disabled
using a register).
Interrupt
Non-maskable interrupt 6 systems (Reset, NMI, HardFault, SVCall, PendSV, SysTic)
Programmable interrupt External interrupt: 3 systems
Internal interrupt: 27 systems
Power supply voltage
VDD operating voltage 1.8 to 5.5 V *If VDD > 3.6 V, the VD1 voltage mode must be set to mode0.
VDD operating voltage for Flash
programming
2.4 to 5.5 V (when VPP is supplied externally)
2.7 to 5.5 V (when VPP is generated internally)
QSPI-Flash interface power voltage 3.0 to 3.6 V (voltage different from VDD can be supplied.)
Operating temperature
Operating temperature range -40 to 85 °C

1 OVERVIEW
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 1-3
(Rev. 2.00)
S1C31D50/D51 lineup 48-pin package 64-pin package 80-pin package 100-pin package
Current consumption (Typ. value)
SLEEP mode *10.46 µA
IOSC = OFF, OSC1 = OFF, OSC3 = OFF
0.95 µA
IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF, RTCA = ON
HALT mode *21.8 µA
IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF
RUN mode 250 µA/MHz
VD1 voltage mode = mode0, CPU = IOSC
155 µA/MHz
VD1 voltage mode = mode1, CPU = IOSC
Shipping form
Package *3TQFP12-48PIN
(P-TQFP048-0707-0.50,
7 ×7 mm, t = 1.2 mm,
0.5 mm pitch)
QFP13-64PIN
(P-LQFP064-1010-0.50,
10 ×10 mm, t = 1.7 mm,
0.5 mm pitch)
TQFP14-80PIN
(P-TQFP080-1212-0.50,
12 ×12 mm, t = 1.2 mm,
0.5 mm pitch)
QFP15-100PIN
(P-LQFP100-1414-0.50,
14 ×14 mm, t = 1.7 mm,
0.5 mm pitch)
*1 SLEEP mode refers to deep sleep mode in the Cortex®-M0+ processor.
*2 HALT mode refers to sleep mode in the Cortex®-M0+ processor.
*3 Shown in parentheses are JEITA package names.
1.2 Block Diagram
CPU core, interrpt controller, and debuger
(Cortex®-M0+)
HW processor
(HWP)
System clock
Interrupt signal
DMA request signal
SWCLK
SWD
Cache controller
Cache RAM
512 bytes
RAM
8K bytes (D50)
10K bytes (D51)
RAM
14K bytes (D50)
12K bytes (D51)
MTB
16-bit peripheral bus
32-bit AHB bus
IOSC
oscillator
EXOSC
input circuit
Clock generator
(CLG)
Power generator
(PWGA)
VDD
VSS
VD1
RTC1S
SDA0–2
SCL0–2
EXSVD0–1
P0*
P1*
P2*
P3*
P4*
P5*
P6*
P7*
P8*
P9*
PA*
PD*
FOUT
OSC1
OSC2
OSC3
OSC4
EXOSC
OSC3
oscillator
OSC1
oscillator
I/O port 01
(PPORT)
I/O port 23
(PPORT)
I/O port others
(PPORT)
Watchdog timer
(WDT2)
Real-time clock
(RTCA)
I2C
(I2C)
3 Ch.
Supply voltage
detector
(SVD3)
1 Ch.
16-bit timer
(T16)
8 Ch.
TOUT00–03
TOUT10–13
CAP00–03
CAP10–13
EXCL00–03
EXCL10–13
16-bit PWM timer
(T16B)
2 Ch.
VDDQSPI
QSDIO00–03
QSPICLK0
#QSPISS0
VPP
Flash memory
192K bytes
Quad
synchronous
serial interface
(QSPI)
1 Ch.
SDI0–2
SDO0–2
SPICLK0–2
#SPISS0–2
Synchronous
serial interface
(SPIA)
3 Ch.
USIN0–2
USOUT0–2
UART
(UART3)
3 Ch.
DMA controller
REMO
CLPLS
IR remote
controller
(REMC3)
1 Ch.
SDACOUT_P
SDACOUT_N
Sound DAC
(SDAC)
1 Ch.
#ADTRG0
ADIN0*
VREFA0
12-bit A/D
converter
(ADC12A)
1 Ch.
Power-on reset
(POR)
System reset controller
(SRC)
#RESET
Brown-out reset
(BOR)
R/F converter
(RFC)
1 Ch.
RFIN0
REF0
SENA0
SENB0
RFCLKO0
*The pin configuration depends on the package. For detailed information, refer to Section 1.3, “Pins.”
Figure 1.2.1 S1C31D50/D51 Block Diagram

1 OVERVIEW
1-4 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
1.3 Pins
1.3.1 Pin Configuration Diagram
TQFP12-48PIN
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
P30 P31 P32
VPP
P90 P91 P92 P93 P94 P95
VDDQSPI
PA3
P30/RFCLKO0/UPMUX
P31/REMO/UPMUX
P32/CLPLS/UPMUX
VPP
P90/QSPICLK0
P91/QSDIO00 P92/QSDIO01 P93/QSDIO02 P94/QSDIO03
P95/#QSPISS0
VDDQSPI
PA3/FOUT
VSS
VD1 PD3 PD2 P51 P50 P23 P22 P21 P20 P62 P61
VSS
VD1 PD3/OSC4 PD2/OSC3 SDACOUT_N/P51 SDACOUT_P/P50 P23/RFIN0/UPMUX P22/REF0/UPMUX
P21/SENA0/UPMUX P20/SENB0/UPMUX
P62/EXSVD1 P61/EXSVD0
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
P46
P45
P40
P17
P16
P15
P14
P13
P06
P05
P04
P03
P46/RTC1S
P45/#ADTRG0
P40/VREFA0
P17/UPMUX/ADIN00
P16/UPMUX/ADIN01
P15/UPMUX/ADIN02
P14/UPMUX/ADIN03
P13/UPMUX/ADIN04
P06/UPMUX
P05/UPMUX
P04/UPMUX
P03/UPMUX
Pin name
#RESET
VDD
OSC1
OSC2
P83
P84
P85
P72
P73
PD0
PD1
TEST
Port function
or signal
assignment
#RESET
VDD
OSC1
OSC2
P83/EXOSC
P84/EXCL00
P85/EXCL01
P72/EXCL10
P73/EXCL11
SWCLK/PD0
SWD/PD1
TEST
Figure 1.3.1.1 S1C31D50/D51 Pin Configuration Diagram (TQFP12-48PIN)

1 OVERVIEW
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 1-5
(Rev. 2.00)
QFP13-64PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P30 P31 P32 P33 P34
VPP
P90 P91 P92 P93 P94 P95
VDDQSPI
PA1 PA2 PA3
P30/RFCLKO0/UPMUX
P31/REMO/UPMUX
P32/CLPLS/UPMUX
P33/UPMUX P34/UPMUX
VPP
P90/QSPICLK0
P91/QSDIO00 P92/QSDIO01 P93/QSDIO02 P94/QSDIO03
P95/#QSPISS0
VDDQSPI
PA1 PA2
PA3/FOUT
VSS
VD1 PD3 PD2 P51 P50 P27 P26 P25 P24 P23 P22 P21 P20 P62 P61
VSS
VD1 PD3/OSC4 PD2/OSC3 SDACOUT_N/P51 SDACOUT_P/P50 P27/UPMUX P26/UPMUX P25/UPMUX P24/UPMUX P23/RFIN0/UPMUX P22/REF0/UPMUX
P21/SENA0/UPMUX P20/SENB0/UPMUX
P62/EXSVD1 P61/EXSVD0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P46
P45
P44
P43
P40
P17
P16
P15
P14
P13
P12
P11
P06
P05
P04
P03
P46/RTC1S
P45/#ADTRG0
P44
P43
P40/VREFA0
P17/UPMUX/ADIN00
P16/UPMUX/ADIN01
P15/UPMUX/ADIN02
P14/UPMUX/ADIN03
P13/UPMUX/ADIN04
P12/UPMUX/ADIN05
P11/UPMUX/ADIN06
P06/UPMUX
P05/UPMUX
P04/UPMUX
P03/UPMUX
Pin name
#RESET
VDD
OSC1
OSC2
P81
P82
P83
P84
P85
P70
P71
P72
P73
PD0
PD1
TEST
Port function
or signal
assignment
#RESET
VDD
OSC1
OSC2
P81
P82
P83/EXOSC
P84/EXCL00
P85/EXCL01
P70
P71
P72/EXCL10
P73/EXCL11
SWCLK/PD0
SWD/PD1
TEST
Figure 1.3.1.2 S1C31D50/D51 Pin Configuration Diagram (QFP13-64PIN)