Epson S1C31D50 User manual

Rev. 2.00
CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
S1C31D50/D51
Technical Manual

©
SEIKO EPSON CORPORATION 2020, All rights reserved.
Evaluation board/kit and Development tool important notice
1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or development
purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished products.
2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product.
The user should use it properly and in a safe manner. Seiko Epson dose not assume any responsibility or liability of any kind
of damage and/or fire coursed by the use of it. The user should cease to use it when any abnormal issue occurs even during
proper and safe use.
3. The part used for this evaluation board/kit or development tool may be changed without any notice.
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical prod-
ucts. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation
or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. When exporting the products or technology described in this material, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to
export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or
manufacture of weapon of mass destruction or for other military purposes.
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.

PREFACE
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 2.00)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C31D50/D51. This
document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in
the “Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the SYSPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the SYSPROT.PROT[15:0] bits
(reserved):Reserved bit. Do not alter from the initial value.
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.
Low power mode
This manual describes the low power modes as HALT mode and SLEEP mode. These terms refer to sleep
mode and deep sleep mode in the Cortex®-M0+ processor, respectively.

CONTENTS
ii Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
– Contents –
Preface......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram ..................................................................................... 1-4
1.3.2 Pin Descriptions ..................................................................................................... 1-8
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWGA) ............................................................................................... 2-1
2.1.1 Overview................................................................................................................. 2-1
2.1.2 Pins......................................................................................................................... 2-1
2.1.3 VD1 Regulator Operation Mode .............................................................................. 2-2
2.1.4 VD1 Regulator Voltage Mode .................................................................................. 2-2
2.2 System Reset Controller (SRC)....................................................................................... 2-3
2.2.1 Overview................................................................................................................. 2-3
2.2.2 Input Pin ................................................................................................................. 2-4
2.2.3 Reset Sources ........................................................................................................ 2-4
2.2.4 Initialization Conditions (Reset Groups) ................................................................. 2-5
2.3 Clock Generator (CLG).................................................................................................... 2-5
2.3.1 Overview................................................................................................................. 2-5
2.3.2 Input/Output Pins ................................................................................................... 2-6
2.3.3 Clock Sources ........................................................................................................ 2-6
2.3.4 Operations.............................................................................................................. 2-9
2.4 Operating Mode ............................................................................................................. 2-13
2.4.1 Initial Boot Sequence ............................................................................................ 2-13
2.4.2 Transition between Operating Modes ................................................................... 2-13
2.5 Interrupts........................................................................................................................ 2-15
2.6 Control Registers ........................................................................................................... 2-15
PWGA Control Register........................................................................................................ 2-15
CLG System Clock Control Register.................................................................................... 2-16
CLG Oscillation Control Register ......................................................................................... 2-17
CLG IOSC Control Register.................................................................................................. 2-18
CLG OSC1 Control Register................................................................................................. 2-18
CLG OSC3 Control Register................................................................................................. 2-19
CLG Interrupt Flag Register.................................................................................................. 2-21
CLG Interrupt Enable Register ............................................................................................. 2-21
CLG FOUT Control Register................................................................................................. 2-22
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core........................................................................................................................ 3-1
3.3 Debugger ........................................................................................................................ 3-1
3.3.1 List of Debugger Input/Output Pins ....................................................................... 3-1
3.3.2 External Connection ............................................................................................... 3-1
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-2
4.3 Flash Memory ................................................................................................................. 4-2

CONTENTS
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation iii
(Rev. 2.00)
4.3.1 Flash Memory Pin................................................................................................... 4-2
4.3.2 Flash Bus Access Cycle Setting............................................................................. 4-2
4.3.3 Flash Programming ................................................................................................ 4-2
4.4 RAM ................................................................................................................................ 4-3
4.5 Peripheral Circuit Control Registers................................................................................ 4-3
4.5.1 System-Protect Function ....................................................................................... 4-9
4.6 Instruction Cache............................................................................................................ 4-9
4.7 Memory Mapped Access Area For External Flash Memory .......................................... 4-10
4.8 Control Registers ........................................................................................................... 4-10
System Protect Register....................................................................................................... 4-10
CACHE Control Register ...................................................................................................... 4-10
FLASHC Flash Read Cycle Register .................................................................................... 4-10
5 Interrupt.........................................................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Offset Address (VTOR)....................................................................... 5-3
5.2.2 Priority of Interrupts................................................................................................ 5-3
5.3 Peripheral Circuit Interrupt Control ................................................................................. 5-3
5.4 NMI.................................................................................................................................. 5-4
6 DMA Controller (DMAC)...............................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 Operations ...................................................................................................................... 6-2
6.2.1 Initialization............................................................................................................. 6-2
6.3 Priority............................................................................................................................. 6-2
6.4 Data Structure................................................................................................................. 6-2
6.4.1 Transfer Source End Pointer................................................................................... 6-3
6.4.2 Transfer Destination End Pointer............................................................................ 6-3
6.4.3 Control Data ........................................................................................................... 6-4
6.5 DMA Transfer Mode ........................................................................................................ 6-5
6.5.1 Basic Transfer......................................................................................................... 6-5
6.5.2 Auto-Request Transfer ........................................................................................... 6-5
6.5.3 Ping-Pong Transfer................................................................................................. 6-6
6.5.4 Memory Scatter-Gather Transfer............................................................................ 6-7
6.5.5 Peripheral Scatter-Gather Transfer......................................................................... 6-8
6.6 DMA Transfer Cycle ........................................................................................................ 6-9
6.7 Interrupts......................................................................................................................... 6-9
6.8 Control Registers ........................................................................................................... 6-10
DMAC Status Register ......................................................................................................... 6-10
DMAC Configuration Register .............................................................................................. 6-10
DMAC Control Data Base Pointer Register.......................................................................... 6-11
DMAC Alternate Control Data Base Pointer Register .......................................................... 6-11
DMAC Software Request Register ....................................................................................... 6-11
DMAC Request Mask Set Register ...................................................................................... 6-11
DMAC Request Mask Clear Register ................................................................................... 6-12
DMAC Enable Set Register .................................................................................................. 6-12
DMAC Enable Clear Register ............................................................................................... 6-12
DMAC Primary-Alternate Set Register ................................................................................. 6-12
DMAC Primary-Alternate Clear Register .............................................................................. 6-13
DMAC Priority Set Register .................................................................................................. 6-13
DMAC Priority Clear Register ............................................................................................... 6-13
DMAC Error Interrupt Flag Register ..................................................................................... 6-13
DMAC Transfer Completion Interrupt Flag Register............................................................. 6-14

CONTENTS
iv Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
DMAC Transfer Completion Interrupt Enable Set Register .................................................. 6-14
DMAC Transfer Completion Interrupt Enable Clear Register ............................................... 6-14
DMAC Error Interrupt Enable Set Register........................................................................... 6-14
DMAC Error Interrupt Enable Clear Register........................................................................ 6-15
7 I/O Ports (PPORT).........................................................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 I/O Cell Structure and Functions..................................................................................... 7-2
7.2.1 Schmitt Input.......................................................................................................... 7-2
7.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell ........................................................ 7-3
7.2.3 Pull-Up/Pull-Down.................................................................................................. 7-3
7.2.4 CMOS Output and High Impedance State............................................................. 7-3
7.3 Clock Settings................................................................................................................. 7-3
7.3.1 PPORT Operating Clock......................................................................................... 7-3
7.3.2 Clock Supply in SLEEP Mode ................................................................................ 7-3
7.3.3 Clock Supply During Debugging............................................................................ 7-4
7.4 Operations ...................................................................................................................... 7-4
7.4.1 Initialization............................................................................................................. 7-4
7.4.2 Port Input/Output Control ...................................................................................... 7-5
7.5 Interrupts......................................................................................................................... 7-6
7.6 Control Registers ............................................................................................................ 7-7
PxPort Data Register ............................................................................................................ 7-7
PxPort Enable Register......................................................................................................... 7-7
PxPort Pull-up/down Control Register ................................................................................. 7-8
PxPort Interrupt Flag Register .............................................................................................. 7-8
PxPort Interrupt Control Register ......................................................................................... 7-8
PxPort Chattering Filter Enable Register.............................................................................. 7-9
PxPort Mode Select Register ............................................................................................... 7-9
PxPort Function Select Register........................................................................................... 7-9
P Port Clock Control Register .............................................................................................. 7-10
P Port Interrupt Flag Group Register.................................................................................... 7-11
7.7 Control Register and Port Function Configuration of this IC ......................................... 7-12
7.7.1 P0 Port Group ....................................................................................................... 7-12
7.7.2 P1 Port Group ....................................................................................................... 7-14
7.7.3 P2 Port Group ....................................................................................................... 7-17
7.7.4 P3 Port Group ....................................................................................................... 7-19
7.7.5 P4 Port Group ....................................................................................................... 7-21
7.7.6 P5 Port Group ....................................................................................................... 7-24
7.7.7 P6 Port Group ....................................................................................................... 7-26
7.7.8 P7 Port Group ....................................................................................................... 7-28
7.7.9 P8 Port Group ....................................................................................................... 7-31
7.7.10 P9 Port Group ..................................................................................................... 7-33
7.7.11 Pa Port Group ..................................................................................................... 7-35
7.7.12 Pd Port Group ..................................................................................................... 7-37
7.7.13 Common Registers between Port Groups .......................................................... 7-39
8 Universal Port Multiplexer (UPMUX)...........................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Peripheral Circuit I/O Function Assignment.................................................................... 8-1
8.3 Control Registers ............................................................................................................ 8-2
Pxy–xz Universal Port Multiplexer Setting Register............................................................... 8-2
9 Watchdog Timer (WDT2)..............................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Clock Settings................................................................................................................. 9-1

CONTENTS
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation v
(Rev. 2.00)
9.2.1 WDT2 Operating Clock .......................................................................................... 9-1
9.2.2 Clock Supply in DEBUG Mode............................................................................... 9-1
9.3 Operations ...................................................................................................................... 9-2
9.3.1 WDT2 Control......................................................................................................... 9-2
9.3.2 Operations in HALT and SLEEP Modes ................................................................. 9-3
9.4 Control Registers ............................................................................................................ 9-3
WDT2 Clock Control Register ............................................................................................... 9-3
WDT2 Control Register.......................................................................................................... 9-4
WDT2 Counter Compare Match Register.............................................................................. 9-4
10 Real-Time Clock (RTCA) ...........................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Output Pin and External Connection ........................................................................... 10-1
10.2.1 Output Pin ........................................................................................................... 10-1
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 RTCA Operating Clock........................................................................................ 10-2
10.3.2 Theoretical Regulation Function.......................................................................... 10-2
10.4 Operations ................................................................................................................... 10-3
10.4.1 RTCA Control ..................................................................................................... 10-3
10.4.2 Real-Time Clock Counter Operations ................................................................. 10-4
10.4.3 Stopwatch Control .............................................................................................. 10-4
10.4.4 Stopwatch Count-up Pattern .............................................................................. 10-4
10.5 Interrupts...................................................................................................................... 10-5
10.6 Control Registers ......................................................................................................... 10-6
RTCA Control Register (Low Byte) ....................................................................................... 10-6
RTCA Control Register (High Byte)....................................................................................... 10-7
RTCA Second Alarm Register .............................................................................................. 10-7
RTCA Hour/Minute Alarm Register....................................................................................... 10-8
RTCA Stopwatch Control Register....................................................................................... 10-8
RTCA Second/1Hz Register ................................................................................................. 10-9
RTCA Hour/Minute Register................................................................................................ 10-10
RTCA Month/Day Register .................................................................................................. 10-11
RTCA Year/Week Register ................................................................................................... 10-11
RTCA Interrupt Flag Register .............................................................................................. 10-12
RTCA Interrupt Enable Register .......................................................................................... 10-13
11 Supply Voltage Detector (SVD3)...............................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input Pins and External Connection ............................................................................ 11-2
11.2.1 Input Pins ............................................................................................................ 11-2
11.2.2 External Connection ............................................................................................ 11-2
11.3 Clock Settings.............................................................................................................. 11-2
11.3.1 SVD3 Operating Clock ........................................................................................ 11-2
11.3.2 Clock Supply in SLEEP Mode ............................................................................. 11-2
11.3.3 Clock Supply in DEBUG Mode............................................................................ 11-3
11.4 Operations ................................................................................................................... 11-3
11.4.1 SVD3 Control....................................................................................................... 11-3
11.4.2 SVD3 Operations................................................................................................. 11-4
11.5 SVD3 Interrupt and Reset ............................................................................................ 11-4
11.5.1 SVD3 Interrupt..................................................................................................... 11-4
11.5.2 SVD3 Reset ......................................................................................................... 11-5
11.6 Control Registers ......................................................................................................... 11-5
SVD3 Clock Control Register ............................................................................................... 11-5
SVD3 Control Register.......................................................................................................... 11-6
SVD3 Status and Interrupt Flag Register ............................................................................. 11-7

CONTENTS
vi Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
SVD3 Interrupt Enable Register............................................................................................ 11-8
12 16-bit Timers (T16).....................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input Pin....................................................................................................................... 12-1
12.3 Clock Settings.............................................................................................................. 12-2
12.3.1 T16 Operating Clock ........................................................................................... 12-2
12.3.2 Clock Supply in SLEEP Mode ............................................................................. 12-2
12.3.3 Clock Supply During Debugging......................................................................... 12-2
12.3.4 Event Counter Clock ........................................................................................... 12-2
12.4 Operations ................................................................................................................... 12-2
12.4.1 Initialization.......................................................................................................... 12-2
12.4.2 Counter Underflow .............................................................................................. 12-3
12.4.3 Operations in Repeat Mode ................................................................................ 12-3
12.4.4 Operations in One-shot Mode............................................................................. 12-3
12.4.5 Counter Value Read ............................................................................................ 12-4
12.5 Interrupt........................................................................................................................ 12-4
12.6 Control Registers ......................................................................................................... 12-4
T16 Ch.nClock Control Register.......................................................................................... 12-4
T16 Ch.nMode Register ...................................................................................................... 12-5
T16 Ch.nControl Register.................................................................................................... 12-5
T16 Ch.nReload Data Register............................................................................................ 12-6
T16 Ch.nCounter Data Register .......................................................................................... 12-6
T16 Ch.nInterrupt Flag Register .......................................................................................... 12-6
T16 Ch.nInterrupt Enable Register ...................................................................................... 12-7
13 UART (UART3)............................................................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins ..................................................................................... 13-2
13.2.2 External Connections .......................................................................................... 13-2
13.2.3 Input Pin Pull-Up Function .................................................................................. 13-2
13.2.4 Output Pin Open-Drain Output Function ........................................................... 13-2
13.2.5 Input/Output Signal Inverting Function ............................................................... 13-2
13.3 Clock Settings.............................................................................................................. 13-2
13.3.1 UART3 Operating Clock...................................................................................... 13-2
13.3.2 Clock Supply in SLEEP Mode ............................................................................. 13-3
13.3.3 Clock Supply During Debugging......................................................................... 13-3
13.3.4 Baud Rate Generator .......................................................................................... 13-3
13.4 Data Format ................................................................................................................. 13-3
13.5 Operations ................................................................................................................... 13-4
13.5.1 Initialization.......................................................................................................... 13-4
13.5.2 Data Transmission ............................................................................................... 13-5
13.5.3 Data Reception.................................................................................................... 13-6
13.5.4 IrDA Interface ...................................................................................................... 13-7
13.5.5 Carrier Modulation............................................................................................... 13-8
13.6 Receive Errors.............................................................................................................. 13-9
13.6.1 Framing Error....................................................................................................... 13-9
13.6.2 Parity Error........................................................................................................... 13-9
13.6.3 Overrun Error....................................................................................................... 13-9
13.7 Interrupts..................................................................................................................... 13-10
13.8 DMA Transfer Requests .............................................................................................. 13-10
13.9 Control Registers ........................................................................................................ 13-11
UART3 Ch.nClock Control Register ................................................................................... 13-11

CONTENTS
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation vii
(Rev. 2.00)
UART3 Ch.nMode Register ................................................................................................ 13-11
UART3 Ch.nBaud–Rate Register........................................................................................ 13-13
UART3 Ch.nControl Register.............................................................................................. 13-13
UART3 Ch.nTransmit Data Register ................................................................................... 13-14
UART3 Ch.nReceive Data Register .................................................................................... 13-14
UART3 Ch.nStatus and Interrupt Flag Register ................................................................. 13-14
UART3 Ch.nInterrupt Enable Register................................................................................ 13-15
UART3 Ch.nTransmit Buffer Empty DMA Request Enable Register .................................. 13-16
UART3 Ch.nReceive Buffer One Byte Full DMA Request Enable Register........................ 13-16
UART3 Ch.nCarrier Waveform Register ............................................................................. 13-16
14 Synchronous Serial Interface (SPIA)........................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins and External Connections .............................................................. 14-2
14.2.1 List of Input/Output Pins ..................................................................................... 14-2
14.2.2 External Connections .......................................................................................... 14-2
14.2.3 Pin Functions in Master Mode and Slave Mode ................................................. 14-3
14.2.4 Input Pin Pull-Up/Pull-Down Function ............................................................... 14-3
14.3 Clock Settings.............................................................................................................. 14-3
14.3.1 SPIA Operating Clock ......................................................................................... 14-3
14.3.2 Clock Supply During Debugging......................................................................... 14-4
14.3.3 SPI Clock (SPICLKn) Phase and Polarity ............................................................ 14-4
14.4 Data Format ................................................................................................................. 14-5
14.5 Operations ................................................................................................................... 14-5
14.5.1 Initialization.......................................................................................................... 14-5
14.5.2 Data Transmission in Master Mode..................................................................... 14-6
14.5.3 Data Reception in Master Mode ......................................................................... 14-8
14.5.4 Terminating Data Transfer in Master Mode ........................................................ 14-10
14.5.5 Data Transfer in Slave Mode .............................................................................. 14-10
14.5.6 Terminating Data Transfer in Slave Mode........................................................... 14-11
14.6 Interrupts..................................................................................................................... 14-12
14.7 DMA Transfer Requests .............................................................................................. 14-13
14.8 Control Registers ........................................................................................................ 14-13
SPIA Ch.nMode Register.................................................................................................... 14-13
SPIA Ch.nControl Register ................................................................................................. 14-14
SPIA Ch.nTransmit Data Register....................................................................................... 14-15
SPIA Ch.nReceive Data Register........................................................................................ 14-15
SPIA Ch.nInterrupt Flag Register ....................................................................................... 14-15
SPIA Ch.nInterrupt Enable Register ................................................................................... 14-16
SPIA Ch.nTransmit Buffer Empty DMA Request Enable Register...................................... 14-16
SPIA Ch.nReceive Buffer Full DMA Request Enable Register ........................................... 14-16
15 Quad Synchronous Serial Interface (QSPI) .............................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins and External Connections .............................................................. 15-2
15.2.1 List of Input/Output Pins ..................................................................................... 15-2
15.2.2 External Connections .......................................................................................... 15-2
15.2.3 Pin Functions in Master Mode and Slave Mode ................................................. 15-6
15.2.4 Input Pin Pull-Up/Pull-Down Function ............................................................... 15-6
15.3 Clock Settings.............................................................................................................. 15-6
15.3.1 QSPI Operating Clock ......................................................................................... 15-6
15.3.2 Clock Supply During Debugging......................................................................... 15-7
15.3.3 QSPI Clock (QSPICLKn) Phase and Polarity....................................................... 15-7
15.4 Data Format ................................................................................................................. 15-8
15.5 Operations ................................................................................................................... 15-9

CONTENTS
viii Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
15.5.1 Register Access Mode ........................................................................................ 15-9
15.5.2 Memory Mapped Access Mode ......................................................................... 15-10
15.5.3 Initialization......................................................................................................... 15-11
15.5.4 Data Transmission in Master Mode.................................................................... 15-12
15.5.5 Data Reception in Register Access Master Mode ............................................. 15-14
15.5.6 Data Reception in Memory Mapped Access Mode ........................................... 15-17
15.5.7 Terminating Memory Mapped Access Operations............................................. 15-25
15.5.8 Terminating Data Transfer in Master Mode ........................................................ 15-25
15.5.9 Data Transfer in Slave Mode .............................................................................. 15-26
15.5.10 Terminating Data Transfer in Slave Mode......................................................... 15-27
15.6 Interrupts..................................................................................................................... 15-27
15.7 DMA Transfer Requests .............................................................................................. 15-28
15.8 Control Registers ........................................................................................................ 15-29
QSPI Ch.nMode Register ................................................................................................... 15-29
QSPI Ch.nControl Register................................................................................................. 15-31
QSPI Ch.nTransmit Data Register ...................................................................................... 15-32
QSPI Ch.nReceive Data Register ....................................................................................... 15-32
QSPI Ch.nInterrupt Flag Register....................................................................................... 15-32
QSPI Ch.nInterrupt Enable Register................................................................................... 15-33
QSPI Ch.nTransmit Buffer Empty DMA Request Enable Register ..................................... 15-33
QSPI Ch.nReceive Buffer Full DMA Request Enable Register........................................... 15-34
QSPI Ch.n FIFO Data Ready DMA Request Enable Register ............................................. 15-34
QSPI Ch.nMemory Mapped Access Configuration Register 1 .......................................... 15-34
QSPI Ch.nRemapping Start Address High Register .......................................................... 15-35
QSPI Ch.nMemory Mapped Access Configuration Register 2 .......................................... 15-35
QSPI Ch.nMode Byte Register........................................................................................... 15-37
16 I2C (I2C).......................................................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Input/Output Pins and External Connections .............................................................. 16-2
16.2.1 List of Input/Output Pins ..................................................................................... 16-2
16.2.2 External Connections .......................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-3
16.3.1 I2C Operating Clock............................................................................................ 16-3
16.3.2 Clock Supply During Debugging......................................................................... 16-3
16.3.3 Baud Rate Generator .......................................................................................... 16-3
16.4 Operations ................................................................................................................... 16-4
16.4.1 Initialization.......................................................................................................... 16-4
16.4.2 Data Transmission in Master Mode..................................................................... 16-5
16.4.3 Data Reception in Master Mode ......................................................................... 16-7
16.4.4 10-bit Addressing in Master Mode..................................................................... 16-10
16.4.5 Data Transmission in Slave Mode ...................................................................... 16-11
16.4.6 Data Reception in Slave Mode........................................................................... 16-13
16.4.7 Slave Operations in 10-bit Address Mode ......................................................... 16-15
16.4.8 Automatic Bus Clearing Operation..................................................................... 16-15
16.4.9 Error Detection ................................................................................................... 16-16
16.5 Interrupts..................................................................................................................... 16-17
16.6 DMA Transfer Requests .............................................................................................. 16-18
16.7 Control Registers ........................................................................................................ 16-18
I2C Ch.nClock Control Register ......................................................................................... 16-18
I2C Ch.nMode Register ...................................................................................................... 16-19
I2C Ch.nBaud-Rate Register.............................................................................................. 16-19
I2C Ch.nOwn Address Register.......................................................................................... 16-20
I2C Ch.nControl Register ................................................................................................... 16-20
I2C Ch.nTransmit Data Register ......................................................................................... 16-21