Table of Contents
1. INTRODUCTION ..................................................................................................................................................7
1.1 Purpose.......................................................................................................................................................7
1.2 SODIMM SOM Overview..............................................................................................................................7
1.3 List of Acronyms ..........................................................................................................................................7
1.4 Terminlogy Description................................................................................................................................9
1.5 References...................................................................................................................................................9
2. ARCHITECTURE AND DESIGN ............................................................................................................................10
2.1 Zynq-7000 SoC SODIMM SOM Block Diagram ............................................................................................10
2.2 Zynq-7000 SoC SODIMMSOM Features......................................................................................................11
2.3 Zynq-7000 SoC...........................................................................................................................................13
2.4 Zynq-7000 SoC Reference Clock.................................................................................................................15
2.5 PMIC..........................................................................................................................................................15
2.6 Memory.....................................................................................................................................................16
2.6.1 DDR3L SDRAM .......................................................................................................................................16
2.6.2 QSPI Flash..............................................................................................................................................16
2.6.3 eMMC Flash...........................................................................................................................................16
2.6.4 Micro SD Slot (Optional).........................................................................................................................17
2.6.5 NAND Flash (Optional) ...........................................................................................................................17
2.7 Wi-Fi & Bluetooth......................................................................................................................................18
2.8 SODIMM PCB Edge Connector ...................................................................................................................19
2.8.1 Gigabit Ethernet Interface......................................................................................................................23
2.8.2 USB 2.0 OTG Interface............................................................................................................................24
2.8.3 Debug UART Interface............................................................................................................................24
2.8.4 I2C Interface ..........................................................................................................................................25
2.8.5 SD/SDIO interface (Optional)..................................................................................................................25
2.8.6 FPGA IOs –PL BANK34...........................................................................................................................26
2.8.7 FPGA IOs –PL BANK35 ...........................................................................................................................32
2.8.8 FPGA IOs –PL BANK13...........................................................................................................................37
2.8.9 JTAG Interface........................................................................................................................................40
2.8.10 Power Input ...........................................................................................................................................40
2.8.11 Reset Signal ...........................................................................................................................................40
2.9 Zynq-7000 SoC PS Pin Multiplexing on SODIMM ........................................................................................41
3. TECHNICAL SPECIFICATION...............................................................................................................................43
3.1 Electrical Characteristics............................................................................................................................43
3.1.1 Power Input Requirement ......................................................................................................................43
3.1.2 Power Consumption...............................................................................................................................44
3.2 Environmental Characteristics ...................................................................................................................45
3.2.1 Environmental Specification...................................................................................................................45
3.2.2 Heat Sink ...............................................................................................................................................45
3.2.3 RoHS Compliance...................................................................................................................................46
3.2.4 Electrostatic Discharge...........................................................................................................................46