iWave i.MX53 Installation manual

Rev 1.2
Page 1 of 33
i.MX53 MXM CPU Module Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
i.MX53 MXM CPU Module
Hardware User Guide

Rev 1.2
Page 2 of 33
i.MX53 MXM CPU Module Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Document Revision History
Revision
Date
Description
Authors
1.0
26th May ‘11
Initial Draft
Roshan
1.1
28th May ‘11
On module IO mux details are added
Roshan
1.2
11th Feb ‘12
Tempt range, ordering information & Boot
switch settings, UART1 details are updated &
5mm stackingheight MXM connector part is
added
Roshan
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s).
Do not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by
others is strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you
are hereby notified that any disclosure, copying distribution or use of any of the information contained within
this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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i.MX53 MXM CPU Module Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Table of Contents
1. INTRODUCTION...........................................................................................................5
1.1 OVERVIEW....................................................................................................................... 5
1.2 REFERENCE DOCUMENTS .................................................................................................... 5
1.3 TERMINOLOGY.................................................................................................................. 6
1.4 BLOCK DIAGRAM............................................................................................................... 7
1.5 FEATURES ........................................................................................................................ 8
1.6 I.MX53 CPU MODULE...................................................................................................... 9
1.7 I.MX53 CPU MODULE DESCRIPTION ................................................................................. 10
1.7.1 Boot Setting Switch................................................................................................ 10
1.7.2 UART Connector (J3).............................................................................................. 11
1.7.3 JTAG Connector(J4)................................................................................................ 11
1.7.4 Micro SD Connector (J1) ........................................................................................ 11
1.7.5 Edge connector (J8)............................................................................................... 11
2. EXTERNAL INTERFACE................................................................................................ 12
2.1 MICRO SD CONNECTOR [J1]............................................................................................. 12
2.2 SERIAL PORT HEADER [J3]................................................................................................ 12
2.3 JTAG HEADER [J4] ......................................................................................................... 13
2.4 BOARD EDGE CONNECTOR (PCB EDGE) .............................................................................. 13
2.5 ON MODULE IO MUXING................................................................................................. 26
2.6 POWER ON SEQUENCE..................................................................................................... 28
3. MATING CONNECTOR DETAILS .................................................................................. 29
3.1 EDGE CONNECTOR (J8).................................................................................................... 29
4. LEDS DESCRIPTION .................................................................................................... 30
4.1 LEDS DESCRIPTION ......................................................................................................... 30
5. MECHANICAL DRAWING............................................................................................ 31
5.1 I.MX53 CPU MODULE ................................................................................................... 31
6. ORDERING INFORMATION......................................................................................... 32
7. TECHNICAL SUPPORT................................................................................................. 33

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List of Figures
Figure 1: Block Diagram of i.MX53 CPU Module ......................................................................... 7
Figure 2: i.MX53 CPU Module...................................................................................................... 9
Figure 3: Power ON sequence.................................................................................................... 28
Figure 4: Mechanical Drawing of i.MX53 CPU Module.............................................................. 31
List of Tables
Table 1: Terminology ................................................................................................................... 6
Table 2: Boot Mode Contact Settings ........................................................................................ 10
Table 3: Boot Device Selection .................................................................................................. 10
Table 4: List Of Connectors ........................................................................................................ 12
Table 5: Micro SD Connector [J1] Pin Assignments................................................................... 12
Table 6: Serial Port Header [J3] Pin Assignments ...................................................................... 12
Table 7: JTAG Header[J4] Pin Assignments............................................................................... 13
Table 8: PCB Edge TOP Side [J8] Pin Assignments .................................................................... 13
Table 9: PCB Edge BOTTOM Side [J8] Pin Assignments ............................................................ 20
Table 10: On module IO Muxing................................................................................................ 26
Table 11: Mating connector for Edge Connector (J8)................................................................ 29
Table 12: LEDs Description......................................................................................................... 30
Table 13: Ordering Information................................................................................................. 32

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i.MX53 MXM CPU Module Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
1. Introduction
1.1 Overview
i.MX53 CPU Module offers advanced performance, connectivity and multimedia
functionality necessary to drive next generation automotive infotainment system. The
i.MX53 CPU Module is ideal for applications that require advanced user interfaces,
sophisticated video processing, 2D and 3D graphics, single or dual high resolution
displays, and a high level of system integration. i.MX53 CPU Module will bring
advanced consumer electronics user experiences and device connectivity into the
vehicles of the future.
This manual provides a general module overview and description of components and
basic operation of i.MX53 CPU Module .
The i.MX536A processor features Freescale’s advanced implementation of the ARM™
core, which operates at speeds as high as 800 MHz and interfaces with DDR2-800,
LPDDR2-800, LVDDR2-800, or DDR3-800 DRAM memories. This device is well-suited for
graphics rendering for HMI and navigation, high performance speech processing with
large data bases, video processing and display, audio playback, and many other
applications
1.2 Reference Documents
Following documents have been referred while preparing the user manual
Document
Description
i.MX53 Datasheet
http://cache.freescale.com/files/32bit/doc/data_sheet/IM
X53AEC.pdf?fpsp=1&WT_TYPE=Data%20Sheets&WT_VEND
OR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Docu
mentation
i.MX53 User Manual
http://cache.freescale.com/files/32bit/doc/ref_manual/iM
X53RM.pdf?fpsp=1&WT_TYPE=Reference%20Manuals&WT
_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET
=Documentation
i.MX53 Development kit
http://www.iwavesystems.com/?q=node/139

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1.3 Terminology
The following is a list of commonly occurring acronyms and abbreviations used
throughout this document.
Table 1: Terminology
Term
Definition
CAN
Controller Area Network
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
CSPI
Configurable Serial Peripheral Interface
DDR2
Double Data Rate2
ECSPI
Enhanced Configurable Serial Peripheral Interface
EMI
External Memory Interface
ESAI
Enhanced serial audio interface
ESDHC
Enhanced secure digital host controller
FEC
Fast Ethernet controller
GPIO
General Purpose Input Output
I2C
Inter-IC bus
IO
Input Output
JTAG
Joint Test Action Group
LCD
Liquid Crystal Display
LED
Light Emitting Diode
MB
Mega Byte
MLB
Media local bus or MediaLB
NC
No connection
OS
Operating System
OTG
On-The-Go
PCB
Printed Circuit Board
PLL
Phase-Locked Loop
PMIC
Power Management Integrated Circuit
PWM
Pulse-Width Modulation
RTIC
Run-Time Integrity Checker
RTC
Real Time Clock
RX
Receive
SATA
Serial Advanced Technology Attachment
SDRAM
Synchronous Dynamic Random Access Memory
SPDIF
Sony Phillips Digital Interface
SSP
Synchronous Serial Ports
TX
Transmit
TTL
Transistor Transistor Logic
UART
Universal Asynchronous Receiver/Transmitter

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ULPI
Ultra Low pin Interface
USB
Universal Serial Bus
1.4 Block Diagram
The high level block diagram of i.MX53 CPU Module(SOM) is shown in Figure 1.
Figure 1: Block Diagram of i.MX53 CPU Module

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1.5 Features
The i.MX53 CPU Module supports the following features:
Standard Features
Processor: Freescale i.MX536 @ 800MHz
512MB DDR2 SDRAM (Expandable up to 2Gbyte)
16MB SPI NOR Flash
Micro SD Slot
Debug UART Console
314 Pin MXM-3 edge connector
5V, 1A Power Input from carrier board
Typical power consumption : <5W
Form Factor : 85 mm x 85mm
Operating Temperature : 0°C to +70°C
Storage Temperature: -40°C to +125°C
Optional features1
8Gbyte eMMC (Expandable up to 32Gbyte)
JTAG Connector
Operating Temperature : -40°C to +85°C
Storage Temperature: -55°C to +125°C
1Note: Optional features are in order to meet Operating Temperature : -40°C to +85°C.
Contact iWave for more details

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Functional Description
1.6 i.MX53 CPU Module
Top view of i.MX53 CPU Module is shown in Figure 2.
Figure 2: i.MX53 CPU Module

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1.7 i.MX53 CPU Module Description
1.7.1 Boot Setting Switch
SW3 is used for Boot Mode setting. Refer Table 2 for settings.
Table 2: Boot Mode Contact Settings
SW3[1:2]
Boot Type
00
Internal Boot
01
Reserved
10
Boot From Fuses
11
Serial Downloader
The selection of external boot device type is controlled by SW1.See for Table 3 more
details
Table 3: Boot Device Selection
SW1[1:4]
Boot Device
1011
SD/eSD
1100
Serial ROM (I2C/SPI)
0111
MMC/eMMC
Note1: By default SD boot mode is supported.
Note2: It is recommended not to use any external pull down/ pull up for the boot
configurations signals available at edge or expansion connector since these signals are used
for boot device selection when processor POR_B is de-asserted. Please refer i.MX53 user
Manual Chapter “System Boot” section “Device Configuration” for boot configuration
signals.

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1.7.2 UART Connector (J3)
Processor UART1 RXD, TXD signals are brought to a 3-pin 80-mil connector through a RS232
transceiver for debug console. This UART connector is optional & by default for debug this
UART is not used. Currently pin 147 & 143 of edge connector are configured as UART debug
port.
1.7.3 JTAG Connector(J4)
A 20pin 50mil pitch berg stick type connector is provided for processor JTAG interface
for debugging/development purpose using ARM tools like Real View ICE.
1.7.4 Micro SD Connector (J1)
Micro SD connector is provided for connecting the mico SD card for mass storage
expandable upto 32GB.
1.7.5 Edge connector (J8)
All the processor IO will taken through the PCB edge .It is a two row with 314 fingers in
PCB. The mating connector will be a female 314 pin MXM-3 connector.
The following interfaces are supported through
UART Interfaces-5
SDIO Interfaces-3
SPI Interfaces-3
Audio Interfaces-3
CAN Interface-2
MLB Interface-1
LVDS Interfaces-2
SATA Interface-1
Parallel RGB Out-1
Video In/CSI Interface-1
SPDIF interface –1
ESAI interface –1
USB HS Host-1
USB OTG-1
Ethernet PHY interface –1
GPIOs
Power

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2. External Interface
On-board connectors link the i.MX53 CPU Module to external interfaces such as
SD,UART etc. Refer Figure 2 for the location of the connectors on i.MX53 CPU Module.
The Table 4 lists the function of each of the board’s connectors.
Table 4: List Of Connectors
Identifier
Function
J1
Micro SD Connector
J3
Serial Port Header
J4
JTAG Connector
J8
Edge Connector
2.1 Micro SD Connector [J1]
The micro SD connector can be used to connect any Micro SD cards for mass storage.
Table 5: Micro SD Connector [J1] Pin Assignments
Pin No.
Signal name
IO Level
Pin No.
Signal name
IO Level
1
DAT2
3.3V
2
CD/DATA3
3.3V
3
CMD
3.3V
4
VDD
3.3V
5
CLK
3.3V
6
GND
0V
7
DAT0
3.3V
8
DAT1
3.3V
2.2 Serial Port Header [J3]
The RS232 serial port header can be used as debug port for diagnostics and also can be
used for any simple RS232 serial communication devices.
Table 6: Serial Port Header [J3] Pin Assignments
Pin No.
Signal name
IO Level
Direction w.r.t SOM
1
GND
0V
2
TXD
+/-5V RS232 Level
Output
3
RXD
+/-5V RS232 Level
Input
Note: SOM refers to i.MX53 CPU module

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2.3 JTAG Header [J4]
An 20-pin customized connector is used to debug the processor and to program the
flash with Host debugger software.
Table 7: JTAG Header[J4] Pin Assignments
Pin No.
Signal name
IO Level
Pin No.
Signal name
IO Level
1
VTRef
1.8V
2
VCC
3.3V
3
nTRST
1.8V
4
GND
0V
5
TDI
1.8V
6
GND
0V
7
TMS
1.8V
8
GND
0V
9
TCK
1.8V
10
GND
0V
11
NC
-
12
GND
0V
13
TDO
1.8V
14
GND
0V
15
nSRST
1.8V
16
GND
0V
17
NC
-
18
GND
0V
19
NC
-
20
GND
0V
2.4 Board Edge Connector (PCB Edge)
Board Edge Connector (PCB Edge TOP Side)
Table 8: PCB Edge TOP Side [J8] Pin Assignments
Signal mentioned in blue color is shared/muxed with other signal/pin
Pin No
Signal Name
IO
Level
Direction
w.r.t
SOM
Out of Reset
Condition-Block
IO
Description/
i.MX53 Ball name
E1-1
VCC (5V)
5V
Input
Main Input to the
Board
E1-2
VCC (5V)
E1-3
VCC (5V)
E1-4
VCC (5V)
E1-5
VCC (5V)
E1-6
NC
E1-7
NC
E1-8
NC
E1-9
GND
GND

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E1-10
LVDS1_TX1_P
2.5V
Output
gpio6_GPI[28]
Ball: AB13
E3-1
LVDS1_TX1_N
2.5V
Output
gpio6_GPI[29]
Ball: AC13
E3-2
GND
GND
E3-3
LVDS1_TX0_P
2.5V
Output
gpio6_GPI[30]
Ball: AB14
E3-4
LVDS1_TX0_N
2.5V
Output
gpio6_GPI[31]
Ball: AC14
E3-5
GND
GND
E3-6
LVDS1_CLK_P
2.5V
Output
gpio6_GPI[26]
Ball: Y13
E3-7
LVDS1_CLK_N
2.5V
Output
gpio6_GPI[27]
Ball: AA13
E3-8
GND
GND
E3-9
LVDS1_TX2_N
2.5V
Output
gpio6_GPI[25]
Ball: AC12
E3-10
LVDS1_TX2_P
2.5V
Output
gpio6_GPI[24]
Ball: AB12
1
GND
GND
3
LVDS1_TX3_P
2.5V
Output
gpio6_GPI[22]
Ball: Y12
5
LVDS1_TX3_N
2.5V
Output
gpio6_GPI[23]
Ball: AA12
7
GND
GND
9
NANDF_WE_B
3.3V
IO
gpio6_GPIO[12]
Ball : AB8
11
NANDF_RE_B
3.3V
IO
gpio6_GPIO[13]
Ball : AC8
13
EIM_WAIT
3.3V
IO
emi_EIM_WAIT
Bal: AB9
15
CSI0_PIXCLK
3.3V
IO
gpio5_GPIO[18]
Ball: P1
17
CSI0_MCLK
3.3V
IO
gpio5_GPIO[19]
Ball: P2
19
CSI0_DATA_EN
3.3V
IO
gpio5_GPIO[20]
Ball: P3
21
DI0_PIN4
2.8V
IO
gpio4_GPIO[20]
Ball:D2
23
EIM_D26
3.3V
IO
gpio3_GPIO[26]
Ball: V5
25
EIM_D27
3.3V
IO
gpio3_GPIO[27]
Ball: V4
27
S5_OFF(WAKE Signal
from PMIC)
5V
Output
Low when CPU
module power is
off
High during
normal working
(5V level signal)
29
EIM_D31
3.3V
IO
gpio3_GPIO[31]
Ball: W5
31
CSI0_VSYNC
3.3V
IO
gpio5_GPIO[21]
Ball: P4
33
NANDF_CLE
3.3V
IO
gpio6_GPIO[7]
Ball: AA10
35
NANDF_ALE
3.3V
IO
gpio6_GPIO[8]
Ball: Y11
37
NANDF_WP_B
3.3V
IO
gpio6_GPIO[9]
Ball: AC9
39
NANDF_RB0
3.3V
IO
gpio6_GPIO[10]
Ball: U11
41
PATA_DMARQ
3.3V
IO
gpio7_GPIO[0]
Ball: J1
43
PATA_BUFFER_EN
3.3V
IO
gpio7_GPIO[1]
Ball: K4
45
NC

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47
TVDAC_IOR
2.8V
IO
TVDAC_IOR
Ball:AC21
49
TVDAC_IOG
2.8V
IO
TVDAC_IOG
Ball:AB20
51
TVDAC_IOB
2.8V
IO
TVDAC_IOB
Ball:AC19
53
NC
55
NANDF_CS0
3.3V
GPIO
gpio6_GPIO[11
Ball: W12
57
GND
GND
59
LVDS0_CLK_P
2.5V
Output
gpio7_GPI[24]
Ball: AC16
61
LVDS0_CLK_N
2.5V
Output
gpio7_GPI[25]
Ball: AB16
63
LVDS0_TX0_P
2.5V
Output
gpio7_GPI[30]
Ball: AA17
65
LVDS0_TX0_N
2.5V
Output
gpio7_GPI[31]
Ball: Y17
67
LVDS0_TX1_P
2.5V
Output
gpio7_GPI[28]
Ball: AC17
69
LVDS0_TX1_N
2.5V
Output
gpio7_GPI[29]
Ball: AB17
71
GND
GND
73
LVDS0_TX2_P
2.5V
Output
gpio7_GPI[26]
Ball: AA16
75
LVDS0_TX2_N
2.5V
gpio7_GPI[27]
Ball: Y16
77
LVDS0_TX3_P
2.5V
Output
gpio7_GPI[22]
Ball: AC15
79
LVDS0_TX3_N
2.5V
Output
gpio7_GPI[23]
Ball: AB15
81
GND
GND
83
PATA_INTRQ
3.3V
IO
gpio7_GPIO[2]
Ball:K5
85
PATA_DIOR
3.3V
IO
gpio7_GPIO[3]
Ball:K3
87
GND
GND
89
NC
91
KEY_COL4
3.3V
IO
gpio4_GPIO[14]
Ball:E5
93
EIM_D30
3.3V
IO
gpio3_GPIO[30]
Ball:W4
95
NC
97
GND
GND
99
KEY_ROW2
3.3V
IO
gpio4_GPIO[11]
Ball: D5
101
KEY_COL2
3.3V
IO
gpio4_GPIO[10]
Ball: C4
103
EIM_DA9
3.3V
IO
emi_NAND_EIM_
DA[9]
Ball: W10
105
EIM_DA10
3.3V
IO
emi_NAND_EIM_
DA[10]
Ball:AB7
107
NC
109
NC
111
PATA_CS_0
3.3V
IO
gpio7_GPIO[9]
Ball: L5
113
PATA_CS_1
3.3V
IO
gpio7_GPIO[10]
Ball: L2
115
CSI0_DAT12
3.3V
IO
gpio5_GPIO[30]
Ball: T3
117
CSI0_DAT13
3.3V
IO
gpio5_GPIO[31]
Ball: T6
119
CSI0_DAT16
3.3V
IO
gpio6_GPIO[2]
Ball: T4

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121
CSI0_DAT17
3.3V
IO
gpio6_GPIO[3]
Ball: T5
123
GND
GND
125
CSI0_DAT18
3.3V
IO
gpio6_GPIO[4]
Ball: U3
133
CSI0_DAT19
3.3V
IO
gpio6_GPIO[5]
Ball: U4
135
CSI0_DAT15
3.3V
IO
gpio6_GPIO[1]
Ball: U2
137
CSI0_DAT14
3.3V
IO
gpio6_GPIO[0]
Ball: U1
139
GND
GND
141
CSI0_DAT4
3.3V
IO
gpio5_GPIO[22]
Ball: R1
143
CSI0_DAT11
3.3V
IO
gpio5_GPIO[29]
Ball: T2
Configured as
UART1 Receive
Pin. Can be used
as debug UART
port on carrier
card
145
CSI0_DAT5
3.3V
IO
gpio5_GPIO[23]
Ball: R2
147
CSI0_DAT10
3.3V
IO
gpio5_GPIO[28]
Ball: R5
Configured as
UART1 Transmit
Pin. Can be used
as debug UART
port on carrier
card
149
CSI0_DAT6
3.3V
IO
gpio5_GPIO[24]
Ball: R6
151
GPIO_0/GPIO_1*
3.3V
IO
gpio1_GPIO[0]
GPIO_0
connected by
default
153
CSI0_DAT7
3.3V
IO
gpio5_GPIO[25]
Ball: R3
155
GND
GND
157
GPIO_6
3.3V
IO
gpio1_GPIO[6]
Ball: B6
159
GPIO_2
3.3V
IO
gpio1_GPIO[2]
Ball: C7
161
GPIO_8
3.3V
IO
gpio1_GPIO[8]
Ball: B5
163
GPIO_17
3.3V
IO
gpio7_GPIO[12]
Ball: A3
165
GPIO_1
3.3V
IO
gpio1_GPIO[1]
Ball: B7
167
GPIO_18
3.3V
IO
gpio7_GPIO[13]
Ball: D7
169
GPIO_7
3.3V
IO
gpio1_GPIO[7]
Ball: A4
171
GPIO_9
3.3V
IO
gpio1_GPIO[9]
Ball: E8
173
GPIO_5*
3.3V
IO
gpio1_GPIO[5]
Not Connected
(Ball:A5)
Muxed with Pin
248

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175
GPIO_16*
3.3V
IO
gpio7_GPIO[11]
Not Connected
Ball: C6)
Muxed with Pin
246
177
GPIO_4/DISP0_DAT22*
3.3V/
2.8V
IO
gpio5_GPIO[16]
By default
DISP0_DAT22 is
connected
179
GPIO_3/DISP0_DAT20*
3.3V/
2.8V
IO
gpio5_GPIO[14]
By default
DISP0_DAT20 is
connected
181
GND
GND
183
KEY_COL0
3.3V
IO
gpio4_GPIO[6]
Ball: C5
185
KEY_COL1
3.3V
IO
gpio4_GPIO[8]
Ball: E7
187
GND
GND
189
USB_H1_DN
2.5V,
3.3V
IO
USB_H1_DN
USB Host DATA-
(Ball: B17)
191
USB_H1_DP
2.5V,
3.3V
IO
USB_H1_DP
USB Host DATA+
(Ball: A17)
193
GND
GND
195
USB_OTG_VBUS
2.5V,
3.3V
Input
USB_OTG_VBUS
USB OTG VBUS
(Ball: E15)
197
USB_OTG_ID
2.5V,
3.3V
Input
USB_OTG_ID
USB OTG ID (Ball:
C16)
199
KEY_ROW4
2.5V,
3.3V
Output
gpio4_GPIO[15]
Ball: E6
201
USB_OTG_DP
2.5V,
3.3V
IO
USB_OTG_DP
USB OTG DATA+
(Ball: B19)
203
USB_OTG_DN
2.5V,
3.3V
IO
USB_OTG_DN
USB OTG DATA-
(Ball: A19)
205
GND
GND
207
NC
209
GPIO_10
2.8V
IO
gpio4_GPIO[0]
Ball:W16
211
GND
GND
213
GPIO_12
2.8V
IO
gpio4_GPIO[2]
Ball:W17
215
DISP0_DAT2
2.8V
IO
gpio4_GPIO[23]
Ball:H2
217
GPIO_13
2.8V
IO
gpio4_GPIO[3]
Ball:AA18
219
DISP0_DAT5
2.8V
IO
gpio4_GPIO[26]
Ball: H3
221
DISP0_DAT1
2.8V
IO
gpio4_GPIO[22]
Ball: J4
223
DI0_PIN3
2.8V
IO
gpio4_GPIO[19]
Ball: C2
225
DI0_PIN2
2.8V
IO
gpio4_GPIO[18]
Ball: D3
227
DISP0_DAT3
2.8V
IO
gpio4_GPIO[24]
Ball: F1

Rev 1.2
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i.MX53 MXM CPU Module Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
229
DISP0_DAT4
2.8V
IO
gpio4_GPIO[25]
Ball: G2
231
DISP0_DAT0
2.8V
IO
gpio4_GPIO[21]
Ball: J5
233
GND
GND
235
DISP0_DAT11
2.8V
IO
gpio5_GPIO[5]
Ball: H5
237
DISP0_DAT9
2.8V
IO
gpio4_GPIO[30]
Ball: E2
239
DISP0_DAT10
2.8V
IO
gpio4_GPIO[31]
Ball: G3
241
DISP0_DAT7
2.8V
IO
gpio4_GPIO[28]
Ball: H6
243
EIM_OE*
3.3V
IO
emi_EIM_OE
Ball:V8
Optionally
connected to
PMIC IRQ pin
245
DISP0_DAT6
2.8V
IO
gpio4_GPIO[27]
Ball: G1
247
EIM_RW*
3.3V
IO
emi_EIM_RW
Ball:AB4
Optionally
connected to
PMIC PBSTAT pin
249
DISP0_DAT8
2.8V
IO
gpio4_GPIO[29]
Ball: G6
251
GND
GND
253
SATA_TXM
2.5V
Output
SATA_TXM
SATA0 Transmit-
(Ball: B10)
255
SATA_TXP
2.5V
Output
SATA_TXP
SATA0 Transmit+
(Ball: A10)
257
GND
GND
259
SATA_RXP
2.5V
Input
SATA_RXP
SATA0 Receive+
(Ball: B12)
261
SATA_RXM
2.5V
Input
SATA_RXM
SATA0 Receive-
(Ball: A12)
263
GND
GND
265
NC
267
EIM_CS1 *
3.3V
IO
emi_EIM_CS[1]
Ball:Y7
Optionally
connected to ETH
PHY INTn pin
269
GND
GND
271
NC
273
EIM_CS0 *
3.3V
IO
emi_EIM_CS[0]
By default not

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i.MX53 MXM CPU Module Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
connected.
Ball:W8
Connected to on
module SPI Flash
WP pin
275
GND
GND
277
POWER_ON
5V
Input
Connected to ON
pin of PMIC.
Can be used to
connect a
pushbutton to
power on the
SOM module
279
RST_IN# (Optional)
3.3V
Input
Connected to
RESET_IN_B pin
of i.MX53.
Can be used to
connect a reset
switch on the
carrier card to
reset the SOM
module
281
SLEEP (Optional)
3.3V/
5V
Output
PMIC_VSTBY_RE
Q signal of
i.MX53 is
inverted to 3.3V
level.
So at the MXM
connector side:
SLEEP=low means
standby request
SLEEP=high
means normal
operation

Rev 1.2
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i.MX53 MXM CPU Module Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Board Edge Connector (PCB Edge BOTTOM Side)
Table 9: PCB Edge BOTTOM Side [J8] Pin Assignments
Pin
No
Signal Name
IO
Level
Direction
w.r.t
SOM
Out of Reset
Condition-Block
IO
Description
E2-1
VCC (5V)
5V
Input
Main Input to the
Board
E2-2
VCC (5V)
E2-3
VCC (5V)
E2-4
VCC (5V)
E2-5
VCC (5V)
E2-6
NC
E2-7
VCC_3V3_MEM
3.3V
RTC
Backup
Input
Used as RTC
backup voltage,
when there is no
main supply
E2-8
NC
E2-9
GND
GND
E2-10
NC
E4-1
NC
E4-2
GND
GND
E4-3
NC
E4-4
NC
E4-5
GND
GND
E4-6
NC
E4-7
NC
E4-8
GND
GND
E4-9
NC
E4-10
NC
2
GND
GND
4
EIM_DA0
3.3V
IO
emi_NAND_EIM
_DA[0]
Ball:Y8
6
EIM_DA1
3.3V
IO
emi_NAND_EIM
_DA[1]
Ball:AC4
8
GND
GND
10
EIM_DA2
3.3V
IO
emi_NAND_EIM
_DA[2]
Ball:AA7
12
EIM_DA3
3.3V
IO
emi_NAND_EIM
_DA[3]
Ball:W9