iWave iW-RainboW-G57M Installation manual

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Versal AI Edge/Prime SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
iW-RainboW-G57M
Versal AI Edge/Prime SOM
Hardware User Guide
Preliminary Information. Subject to change

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Versal AI Edge/Prime SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Document Revision History
Document Number
iW-PRHRZ-UM-01-R1.0-REL0.3-Hardware User Guide
Release
Date
Description
0.1
20th Apr 2023
Initial Draft Version
0.2
13th Jun 2023
Updated Release
0.3
06th July 2023
•Updated Figure1 Block diagram.
•Updated Board to Board connector2 PL block section in Versal AI Edge SOM Features.
•Updated Table 7: Board to Board Connector1 Pinout for 702 Bank.
•Updated section 2.5.3 PL IOs –XPIO BANK 702 and Table 9: PL XPIO Bank 702 Pinouts.
•Corrected GTYP transceiver speed grade in 2.6.12 GTYP High Speed Transceivers section.
•Updated Table 12: Board to Board Connector2 Pinout
•Corrected Document revision history year from 2022 to 2023.
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do not read this
document if you are not the intended recipient. Any review, use, distribution or disclosure by others is strictly prohibited. If you
are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copying
distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems
Tech. Pvt. Ltd.”

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Versal AI Edge/Prime SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product specification without
notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted
by law no liability (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or
employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no circumstances,
iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners and used for
identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that our Hardware
and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076

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Versal AI Edge/Prime SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Table of Contents
1. INTRODUCTION.........................................................................................................................................................7
1.1 Purpose .............................................................................................................................................................7
1.2 SOM Overview ..................................................................................................................................................7
1.3 List of Acronyms................................................................................................................................................7
1.4 Terminology Description...................................................................................................................................9
1.5 References ........................................................................................................................................................9
2. ARCHITECTURE AND DESIGN ..................................................................................................................................10
2.1 Versal AI Edge/Prime SOM Block Diagram......................................................................................................10
2.2 Versal AI Edge SOM Features..........................................................................................................................11
2.3 Versal AI Edge .................................................................................................................................................13
2.3.1.1 SoC Power ................................................................................................................................................................16
2.3.1.2 SoC Reset..................................................................................................................................................................16
2.3.1.3 Versal System Monitor.............................................................................................................................................16
2.3.1.4 Versal Configuration Power & Status LEDs..............................................................................................................17
2.3.1.5 Versal Boot Mode Configuration .............................................................................................................................18
2.3.2 Clock Design....................................................................................................................................................19
2.3.2.1 Clock Synthesizer .....................................................................................................................................................19
2.3.3 Versal AI Edge/Prime SOM PMIC’s..................................................................................................................20
2.3.3.1 PMIC Regulator 1 with RTC ......................................................................................................................................20
2.3.3.2 PMIC Regulator 2 without RTC.................................................................................................................................20
2.3.4 SOM Memory..................................................................................................................................................21
2.3.4.1 LPDDR4 SDRAM........................................................................................................................................................21
2.3.4.2 QSPI Flash.................................................................................................................................................................21
2.3.4.3 eMMC Flash .............................................................................................................................................................21
2.4 On SOM Features............................................................................................................................................22
2.4.1 Fan Header..................................................................................................................................................22
2.5 Board to Board Connector1............................................................................................................................23
2.5.1 PL Interfaces................................................................................................................................................26
2.5.2 PL IOs –XPIO BANK 703 ..............................................................................................................................26
2.5.3 PL IOs –XPIO BANK 702 ..............................................................................................................................30
2.5.4 PL IOs –HD BANK 302.................................................................................................................................33
2.5.5 Power Control Output.................................................................................................................................34
2.6 Board to Board Connector2............................................................................................................................35
2.6.1 PS Interfaces................................................................................................................................................39
2.6.2 USB2.0 OTG Interface .................................................................................................................................39
2.6.3 Gigabit Ethernet Interface ..........................................................................................................................40
2.6.4 RGMII/ULPI Interface..................................................................................................................................41
2.6.5 SD/SDIO Interface .......................................................................................................................................42
2.6.6 Debug UART Interface.................................................................................................................................43
2.6.7 I2C Interface................................................................................................................................................43
2.6.8 SPI Interface ................................................................................................................................................44

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2.6.9 CAN FD Interface.........................................................................................................................................45
2.6.10 JTAG Interface.............................................................................................................................................45
2.6.11 PL Interfaces................................................................................................................................................46
2.6.12 GTYP High Speed Transceivers....................................................................................................................46
2.6.13 Power, Reset & Control Signals...................................................................................................................48
2.7 Versal AI Edge PS Pin Multiplexing on Board to Board Connectors................................................................51
3. TECHNICAL SPECIFICATION.....................................................................................................................................55
3.1 Electrical Characteristics .................................................................................................................................55
3.1.1 Power Input Requirement...........................................................................................................................55
3.1.2 Power Input Sequencing.............................................................................................................................56
3.1.3 Power Consumption....................................................................................................................................57
3.2 Environmental Characteristics........................................................................................................................58
3.2.1 Temperature Specification..........................................................................................................................58
3.2.2 RoHS2 Compliance......................................................................................................................................58
3.2.3 Electrostatic Discharge................................................................................................................................58
3.3 Mechanical Characteristics .............................................................................................................................59
3.3.1 Versal AI Edge SOM Mechanical Dimensions..............................................................................................59
4. ORDERING INFORMATION......................................................................................................................................61
5. APPENDIX................................................................................................................................................................62
5.1 Versal AI Edge SOM Development Platform...................................................................................................62

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List of Figures
Figure 1: Versal AI Edge/Prime SOM Block Diagram ...........................................................................................................................10
Figure 2:Indication LEDs.......................................................................................................................................................................17
Figure 3: Fan Header............................................................................................................................................................................22
Figure 4: Board to Board Connector 1 .................................................................................................................................................23
Figure 5: Board to Board Connector 2 .................................................................................................................................................35
Figure 6: Power Input Sequencing.......................................................................................................................................................56
Figure 7: Mechanical dimension of Versal AI Edge SOM SOM - Top View .........................................................................................59
Figure 8: Mechanical dimension of Versal AI Edge SOM - Bottom View.............................................................................................60
Figure 9: Top and Bottom Maximum Heighted Component ...............................................................................................................60
Figure 10: Versal AI Edge Development Platform................................................................................................................................62
List of Tables
Table 1: Acronyms & Abbreviations.......................................................................................................................................................7
Table 2: Terminology .............................................................................................................................................................................9
Table 3: MIO and EMIO Pin Mapping Table.........................................................................................................................................15
Table 4: Boot Mode Switch Truth Table ..............................................................................................................................................18
Table 5: Clock Synthesizer Input & Output..........................................................................................................................................19
Table 6: Fan Header Pinout..................................................................................................................................................................22
Table 7: : Board to Board Connector1 Pinout......................................................................................................................................24
Table 8: PL XPIO Bank 703 ...................................................................................................................................................................26
Table 9: PL XPIO Bank 702 Pinouts ......................................................................................................................................................30
Table 10: PL HD Bank 302 Pinouts .......................................................................................................................................................33
Table 11: Board to Board Connector Power Pins.................................................................................................................................34
Table 12: Board to Board Connector2 Pinout......................................................................................................................................36
Table 13: USB 2.0 Board to Board Connector2 Pinouts.......................................................................................................................39
Table 14: GEM0 Board to Board Connector2 Pinouts .........................................................................................................................40
Table 15: GEM1 Board to Board Connector2 Pinouts .........................................................................................................................41
Table 16: SD/SDIO Interface Board to Board Connector2 Pinouts ......................................................................................................42
Table 17:Debug UART Board to Board Connector2 Pinouts................................................................................................................43
Table 18: I2C Interface Board to Board Connector2 Pinouts...............................................................................................................43
Table 19: SPI Interface Board to Board Connector2 Pinouts...............................................................................................................44
Table 20: CAN FD Interface Board to Board Connector2 Pinouts........................................................................................................45
Table 21: JTAG Interface Board to Board Connector2 Pinouts............................................................................................................45
Table 22: GTYP Transceiver Speed Grade............................................................................................................................................46
Table 23: GTYP Transceiver Board to Board Connector 2 Pinouts ......................................................................................................46
Table 24: Board to Board connector2 Control & Power Pins ..............................................................................................................49
Table 25: PS IOMUX on Versal AI Edge SOM .......................................................................................................................................51
Table 26: Power Input Requirement....................................................................................................................................................55
Table 27: Power Sequence Timing.......................................................................................................................................................56
Table 28: Temperature Specification...................................................................................................................................................58
Table 29: Orderable Product Part Numbers ........................................................................................................................................61

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Versal AI Edge/Prime SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
1. INTRODUCTION
1.1 Purpose
This document is the Hardware User Guide for the Versal AI Edge/Prime System on Module. This board is fully supported by iWave
Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design and usage of the Versal AI Edge/
Prime System on Module from a Hardware Systems perspective.
1.2 SOM Overview
Versal AI Edge/Prime SOM has a form factor of 50mm x 60mm and provides the functional requirements for an embedded
application with integrated Processing System (PS) and Programable logic (PL). Two High-Speed High-Density connectors provide
the carrier board interface to carry all the I/O signals to and from the Versal AI Edge/Prime SOM.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
ARM
Advanced RISC Machine
BSP
Board Support Package
B2B
Board to Board Connector
CAN
Controller Area Network
CPU
Central Processing Unit
LPDDR4
Low- Power Double Data Rate
FPGA
Field Programmable Gate Array
eMMC
Embedded Multimedia Card
GB
Giga Byte
Gbps
Gigabits per sec
GEM
Gigabit Ethernet Controller
GHz
Giga Hertz
GPIO
General Purpose Input Output
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
JTAG
Joint Test Action Group
Kbps
Kilobits per second
LVDS
Low Voltage Differential Signalling
MAC
Media Access Controller
MB
Mega Byte
Mbps
Megabits per sec
MHz
Mega Hertz

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Acronyms
Abbreviations
NPTH
Non-Plated Through hole
PCB
Printed Circuit Board
PMIC
Power Management Integrated Circuit
PTH
Plated Through hole
PL
Programmable Logic
PS
Processing System
QSPI
Quad Serial Peripheral Interface
RGMII
Reduced Gigabit Media Independent Interface
RTC
Real Time Clock
RX
Receiver
SD
Secure Digital
SDIO
Secure Digital Input Output
SoC
System On Chip
SPI
Serial Peripheral Interface
SOM
System On Module
TX
Transmitter
UART
Universal Asynchronous Receiver/Transmitter
ULPI
UTMI+ Low Pin Interface
USB
Universal Serial Bus
USB OTG
USB On The Go

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1.4 Terminology Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
DIFF
Differential Signal
LVDS
Low Voltage Differential Signal
GBE
Gigabit Ethernet Media Dependent Interface differential pair signals
USB
Universal Serial Bus differential pair signals
OD
Open Drain Signal
OC
Open Collector Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes the pull-ups
or pull-downs implemented On-SOM.
1.5 References
•Versal AI Edge/Prime Technical Reference Manual
•Versal AI Edge/Prime Device Overview
•Versal AI Edge/Prime AC and DC characteristics

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the Versal AI Edge/Prime SOM features and Hardware architecture with high level
block diagram. Also, this section provides detailed information about Board-to-Board connectors pin assignment and usage.
2.1 Versal AI Edge/Prime SOM Block Diagram
Versal AI Edge/Prime SOM Block Diagram
Processing System (PS)
Dual-core Arm Cortex-A72,
Dual-core Arm Cortex-R5F
Versal AI Edge
VE2302/2202/2102/2002
Versal AI Prime
VM1102¹
Programmable Logic (PL)
PL IOs
Bank 702
GTYP Transceiver²´³
B2B
Connector2
(240pin)
B2B
Connector1
(240pin)
Power
Regulators
5V
USB2.0
PHY
USB
10/100/1000
PHY
GEM0
USB 2.0
Gigabit Ethernet
ULPI
RGMII
GEM1 RGMII x 1
SD1 SD (4bit) x 1
UART0 UART (Debug) x 1
PMC I2C I2C x 1
SPI1 SPI (with 3 CS) x 1
SD0
eMMC 16GB
(Upgradable)
eMMC (8bit)
QSPI
QSPI 256MB
(Upgradable)
QSPI
High Speed Transceiver (4 Channels)¹
High Speed Transceiver (4 Channels)¹
Bank 703
FPGA XP IOs (12LVDS/24SE)
PL Bank
700
701
LPDDR4 (64bit)
LPDDR4 4GB
(Upgradable)
FPGA XP IOs (27LVDS/54SE)
FPGA HD IOs (20SE) Bank 302
PL IOs
Bank 103
Bank 104
CAN FD1 CAN FD x 1
¹ Versal Prime doesn’t support AI/ML Engine
² GTYP transceiver is not supported in VE2102 & VE2002
JTAG JTAG x 1
Preliminary Information Subject to Change
Clock
Generator
SYNC_CLK_IN
To Bank 103,104,
702, Eth & USB PHY
Figure 1: Versal AI Edge/Prime SOM Block Diagram

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2.2 Versal AI Edge SOM Features
The Versal AI Edge/Prime SOM supports the following features.
SoC
•Xilinx Versal AI Edge/Prime
➢Pin Compatible Devices: VE2302/VE2202/VE2102/VE2002 & VM1102
➢System Logic cells up to 328.72K Logic cells and up to 300.544K Configurable Logic Blocks and 150.227K LUTs .
➢Processing System with integrated Dual-core Cortex-A72 Cores application processor and Dual-core Cortex-R5F
Cores real-time processing and control.
➢Programmable Network on Chip (NoC)
➢40G Multi-rate Ethernet MAC
➢AIE-ML Data & Shared memory
PMIC
•Dialog’s DA9062 PMIC Regulator 1 & 2
Memory
•256MB QSPI Flash (Expandable)
•16GB eMMC Flash (Expandable)
•4GB LPDDR4 (Expandable)
Clock Generator
•6-bit Clock synthesizer
Other On-SOM Features
•10/100/1000 Ethernet PHY Transceiver
•USB2.0 PHY Transceiver
•FAN Header
Board to Board Connector1 Interfaces (240pin)
From PL Block
•12 LVDS/24 Single ended signals from XP Bank 7022
•27 LVDS/54 Single ended signals from XP Bank 7032
•20 Single ended signals from HD Bank 3022
•Synchronous Clock In/Out
•10MHz Reference Clock Input

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Board to Board Connector2 Interfaces (240pin)
From PS Block
•Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY transceiver)
•USB2.0 OTG x 1 Port (through ON-SOM USB2.0 PHY Transceiver)
•RGMII Interface x1
•SD1 (4bit) x1 Port
•UART x1 Port
•PMC I2C x1 Port
•SPI(3CS) x1 Port
•CAN FD x1 Port
•PS JTAG x1 Port
From PL Block
•PL-GTYP High Speed Transceivers (up to 32 Gbps) x 81
•1PPS Clock Input
General Specification
•Power Supply : 5V (from Board-to-Board Connector2)
•Form Factor : 50mm x 60mm
Note:
1GTYP Transceiver’s are not supported in VE2002 & VE2102 devices.
2In Versal AI Edge/Prime SOM, PL XP & HD IO BANKs supports variable IO voltage setting which configurable through software.

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2.3 Versal AI Edge
As an adaptive compute acceleration platform (ACAP), the Versal AI Edge series allows developers to rapidly evolve their sensor
fusion and AI algorithms while leveraging the world’s most scalable device portfolio for diverse performance and power profiles
from edge to endpoint. This is a composition of Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge
memory and interfacing technologies. As an adaptive compute acceleration platform (ACAP), the Versal AI Edge series allows
developers to rapidly evolve their sensor fusion and AI algorithms while leveraging the world’s most scalable device portfolio for
diverse performance and power profiles from edge to endpoint. It also supports a such as 32 Gbps high-speed transceiver blocks
to support all necessary protocols in edge applications, 40G multi-rate Ethernet, PCIe, and native MIPI support for vision sensors
which are a must for advanced AI applications. The Versal AI Edge integrated with Processing system (PS) and programmable logic
(PL) in a single device. Versal’s Processing system includes dual-core Arm Cortex™-A53 and dual-core Arm Cortex-R5F based
processing system.
Figure 1: Versal AI Edge Simplified Block Diagram
Note: Please refer the latest Versal AI Edge Datasheet & Technical Reference Manual for more details which may be revised from
time to time.

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The Versal AI Edge/Prime SOM is compatible for VE2302/VE2202/VE2102/VE2002 & VM1102 with SFVA784 Pin package of Versal
AI Edge devices. This SFVA784 pin package is a 784 pin 23 mm x 23mm with 0.8mm ball pitch. The Versal AI Edge SOM is compatible
to VE2302, VE2202, VE2102, VE2002 & VM1102 devices and feature comparison between these devices are shown below.
Features
VE2002
VE2102
VE2202
VE2302
VM1102
APU
Dual-core Arm Cortex-A72; 48KB/32KB L1 Cache w/ parity and ECC; 1MB L2 Cache w/ ECC
RPU
Dual-core Arm Cortex-R5F; 32KB/32KB L1 Cache, and TCM w/ECC
Memory
256KB On-Chip Memory w/ECC
Connectivity
Ethernet (x2); UART (x2); CAN-FD (x2); USB 2.0 (x1); SPI (x2); I2C (x2)
DDR Memory Controllers
1
1
1
1
1
PCIe-GEN4
0
0
1
1
0
40G Multirate Ethernet MAC
0
0
1
1
0
100G Multirate Ethernet MAC
0
0
0
0
1
AI Engines-ML
8
12
24
32
0
AIE/AIE-ML Data Memory (Mb)
4
6
12
17
0
AIE-ML Shared Memory (Mb)
48
48
68
68
0
AIE to NoC Interface Tiles
2
2
6
6
0
AIE to PL Interface Tiles
7
7
12
12
0
DSP Engines
90
176
324
464
464
System Logic Cells
43,750
80,080
229,688
328,720
328,720
CLB Flip-Flops
40,000
73,216
210,000
300,544
300,544
LUTs
20,000
36,608
105,000
150,272
150,272
Distributed RAM (Mb)
0.6
1.1
3.2
4.6
4.6
Block RAM Blocks
24
47
108
155
155
Block RAM (Mb)
0.8
1.7
3.8
5.4
5.4
UltraRAM Blocks
24
47
108
155
155
UltraRAM (Mb)
6.8
13.2
30.4
43.6
43.6
Accelerator RAM (Mb)
32
32
32
32
32
XPIO
96
96
96
96
96
HDIO
20
20
20
20
20
GTYP Transceivers
0
0
8
8
8
The Versal AI Edge, Processing System (PS) supports a total 78 dedicated I/O pins referred as MIO (Multiplexed I/O) for peripheral
interfaces. These 78 MIO pins are divided as Platform Management Controller (PMC) and Low Power Domain (LPD). The PMC
supports total 52 MIO with BANK 500 & 501 and each bank includes 26 device pins. The LPD supports a 26 MIO with Bank 502 and
this bank also includes a 26 MIO pins. 78 MIO pins are not enough to support simultaneous use of all the peripherals supported by
PS, there is option in Versal to route IO peripheral interfaces to PL Bank I/O pins referred as EMIO (Extended MIO). Versal AI Edge
PS Peripheral Pin mapping options between MIO & EMIO is shown below.

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Table 3: MIO and EMIO Pin Mapping Table
Peripheral
Interface
Controller
Location
PMC MIO
LPD MIO
EMIO
Notes
CAN_FD 0,1
LPD
Yes
Yes
Yes
-
GEM 0,1
LPD
Yes
Yes
-
RGMII
-
-
Yes
GMII/MII, TSU, and external
FIFO
Yes
Yes
Yes
MDIO
LPD DMA
LPD
-
-
YES
Flow control
PMC_GPIO
PMC
Yes
-
-
Bank 0,1 (no Bank 2)
-
-
Yes
BANK 3,4
LPD_GPIO
LPD
-
Yes
-
LPD GPIO BANK 0 (no Bank
1,2)
-
-
Yes
LPD GPIO Bank 3
LPD_I2C 0,1
LPD
Yes
Yes
Yes
-
PMC_I2C
PMC
Yes
-
Yes
-
Octal SPI
PMC
Yes
-
-
SD/eMMC 0, 1
PMC
Yes
-
Yes
-
Select MAP
PMC
Yes
-
-
SPI 0, 1
LPD
Yes
Yes
Yes
-
Quad SPI
PMC
Yes
-
UART 0, 1
LPD
Yes
Yes
Yes
MIO only includes RX, TX,
CTS, and RTS
USB_2.0
LPD
Yes
ULPI
LPD_SWDT
LPD
Yes
Yes
Yes
-
The Versal AI Edge PL Banks are classified as Xtreme Performance (XP) banks or high-density (HD) banks. The XP Bank IO’s are
optimized for highest performance operation organized in a banks of 700, 701, 702 & 703. Each XPIO bank contains a 54 SE / 27
LVDS pins. The HD Bank I/O’s are reduced-feature I/O’s organized in a bank of 302 with 20 SE pins.
In Versal AI Edge, each XPIO bank supports four Global Clock (GC) input pin pairs. GC pins have direct access to the global clock
buffers, MMCMs and DPLLs of the same Bank. The HD bank supports a two High Density Global Clock (HDGC) input pin pair and
have direct access only to the DPLL.
Also, Versal AI Edge supports 8 high-speed transceiver GTYP from Programmable Logic (PL). These transceivers are arranged in
groups of four known as a transceiver Quad with Bank 103 & Bank 104 and supported line rate of 32 Gb/s.

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2.3.1.1 SoC Power
The Versal AI Edge/ Prime SOM uses discrete power regulators along with two DA9062 PMIC from Dialog Semiconductor for SoC
power management. The Versal SOM supports a -2 & -1 speed grade. The -2 devices can operate at a VCCINT voltage of 0.88V (H),
0.80V (M), or 0.70V (L), and the -1 devices can operate at a VCCINT voltage of 0.80V (M) or 0.70V (L). Primary supply operating
voltages typically scale with VCCINT, except for supported overdrive of the VCC_PMC, VCC_PSFP, VCC_PSLP, and VCC_CPM5 at
0.88V (H) when VCCINT and other primary supplies operate at 0.70V (L). Also, all PS Bank I/O voltage is fixed to 1.8V.
The I/O voltage of PL XP Banks 700 & 701 are connected to LPDDR4 and generated from On SOM buck regulator with 1.1V. The
other two XP Banks 702 & 703 voltages which are connected to Board-to-Board Connectors 1 are generated from PMIC Regulator
1 of LDO2 and LDO3 respectively with 1.0V and 1.8V. The Voltage of XP and HD bank on Versal SOM can be configurable through
software after bootup.
2.3.1.2 SoC Reset
The Versal AI Edge Prime SOM uses PMIC Regulator2’s Reset output (nRESET) for PS Power On Reset and connected to POR_B_503
pin of SoC.
2.3.1.3 Versal System Monitor
The System Monitor (SYSMON) resides in the PMC and monitors operating conditions on the device. The SYSMON can access
internal sensors for monitoring internal power supplies and temperature. The results captured by the SYSMON are stored in a
register map that is accessible through platform management controller resources. MIO or high-density I/O (HDIO) pins can be
used by the SYSMON for measuring voltage levels external to the device.

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2.3.1.4 Versal Configuration Power & Status LEDs
The Platform management controller (PMC) is responsible for booting the Versal from the primary boot source in a multi-stage
boot process that supports both a non-secure and a secure boot. Upon reset, device executes code out of on-chip ROM and copies
the first stage boot loader (FSBL) from the boot device to the on-chip RAM.
Figure 2:Indication LEDs
The Versal AI Edge/Prime SOM supports two LEDs for the Power LED indication and error Out indication. LED D1 & D2 is for Power
Status LEDs. D2 LED is connected to PMIC 2 last power rail of the SOM in power sequence to make all the powers are stable. LED
D4 is for Error Out indication it is asserted for accidental loss of power, a hardware error and not booting etc..
The Versal AI Edge/Prime SOM supports one dedicated input and output configuration pins. PUDC_B pin is an input and is used to
select the behaviour of the XPIO or HDIO during configuration and this pin is connected pullup of VCC_1V8 through 4.7K by default.
If the pins is high PL IOs are in tri-stated and if this pin is low PL IOs internal pullups are enabled.
DONE_503 is output and its in open drain pin with weak internal pullup. This pin will become high when the boot sequence is
complete. By default this pin is connected to VCC_1V8 through 4.7K.

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Versal AI Edge/Prime SOM Hardware User Guide
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2.3.1.5 Versal Boot Mode Configuration
In Versal AI Edge/Prime SOM, Boot modes are categorized into master and slave mode. The master boot modes automatically load
the programmable device image from a memory source and the slave boot modes require an external processor or controller to
load the programmable device image with a command set (JTAG or SelectMAP). Versal SOM can support Quad SPI, SD1, & JTAG as
boot device and configurable through boot mode pins. These boot mode pins can be controlled from the D12,D13 & D14 pin of
board to board connector2. Upon reset, the mode pins are read to determine the primary boot device. By default PS Mode 0,1,2
signals are directly connected to VCC_1V8 through 200Kilo Ohm and PS Mode 3 signal is connected to ground 10Kilo ohm
Table 4: Boot Mode Switch Truth Table
Versal AI Edge
Boot Mode
SW4 (4 Position Switch)
PS Mode 0
(Boot SEL0)
SW4.1
PS Mode 1
(Boot SEL1)
SW4.2
PS Mode 2
(Boot SEL2)
SW4.3
Switch Position Image
PS JTAG
OFF
OFF
OFF
SD1
ON
OFF
ON
QSPI
OFF
ON
OFF
Note: SW4 boot media switch is assembled in the Carrier board to control SOM Boot media and SOM boot mode signals are
connected to SW4 through Board-to-Board connector2.

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Versal AI Edge/Prime SOM Hardware User Guide
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2.3.2 Clock Design
2.3.2.1 Clock Synthesizer
The Versal AI Edge/Prime SOM supports on-Board 6-Bit Clock Synthesizer “SI5332A-D-GM1” from Skyworks Solution. This clock
synthesizer provides all clock source for whole SOM & other peripheral to make the system completely synchronized. Also Versal
AI Edge SOM one dedicated on board oscillator for PS reference clock.
Table 5: Clock Synthesizer Input & Output
Sl.
No
Clock
Synthesizer
In/Out
Frequency
Versal AI Edge Pin Name
/ Net Name
SoC
Pin No
Signal Type/
Termination
Description
Input Reference Clock Options to Clock Synthesizer
1
CLKIN_2/
CLKIN_2b
100 MHz
MSIO/SYS_SYNC_CLK_INP/M
SIO/SYS_SYNC_CLK_INN
NA
1.8V, LVDS
External clock input from A15,
A16th pin of B2B1
2
CLKIN_2
10 Mhz
MSIO/SYS_SYNC_CLK_INP
NA
1.8V, LVCMOS
External clock input from
A47th pin of B2B1 (Optional)
3
XA/XB
25 MHz
CLK_XA/CLK_XB
NA
-
External Crystal input
Output Clock from Clock Synthesizer
1
OUT0/
OUT0b
156.25MHz
GTYP_REFCLK1P_103/
GTYP_REFCLK1P_103
K7,
K6
LVDS
Reference clock1 for GTYP
Bank 103
2
OUT1/
OUT1b
156.25MHz
GTYP_REFCLK1P_104/GTYP_
REFCLK1N_104
F7,
F6
LVDS
Reference clock1 for GTYP
Bank 104
3
OUT2/
OUT2b
200MHz
XP_N23_LVDS702_L24P_GC/
XP_N24_LVDS702_L24N_GC
N23,
N24
LVDS
LPDDR4 Bank reference clock
4
OUT3
25MHz
GEM0_XI_CLK
NA
1.8V, LVCMOS
GEM0 Ethernet PHY REF Clock
5
OUT4
24MHz
USB0_XI_CLK
NA
1.8V, LVCMOS
USB 2.0 Transceiver PHY Clock
6
OUT5/
OUT5b
100MHz
MSIO/SYS_SYNC_CLK_OUTp/
MSIO/SYS_SYNC_CLK_OUTn
NA
3.3V, LVDS
Clock input to A31 & A32 pin
of B2B1.
PS Dedicated Input Oscillator
1
OUT
33.3333MHz
MSIO/SYS_SYNC_CLK_INP
/MSIO/SYS_SYNC_CLK_IN
N
U14
1.8V, LVCMOS
Single ended reference clock
for PS.

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Versal AI Edge/Prime SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.3.3 Versal AI Edge/Prime SOM PMIC’s
The Versal AI Edge SOM supports two Dialog semiconductor DA9062 PMIC. The PMC I2C module of Versal AI Edge PS is used for
PMIC interface through MIO pins.
2.3.3.1 PMIC Regulator 1 with RTC
The PMC I2C module of Versal AI Edge/Prime SOM is used for PMIC 1 chip through Versal AI Edge pins with I2C address 0x48/0x49.
PMIC’s BUCK 3 is connected to I/O voltage of PS MIO Banks (MIO Bank 500, 501, 502 & 503). The I/O voltage is configured to fixed
1.8V by PMIC’s internal OTP during power up.
PMIC’s LDO2 & LDO3 are connected to I/O voltage of PL XPIO Banks (PL Bank 702, & 703). The I/O voltage is configured to 1.0 by
PMIC’s internal OTP during power up. The I/O voltage is configurable through software to 1.5V after bootup.
PMIC’s LDO4 are connected to I/O voltage of PL HD Banks (PL Bank 302). The I/O voltage is configured to 1.8V by PMIC’s internal
OTP during power up. The I/O voltage is configurable through software to 1.8V after bootup.
The Other PMIC’s Buck and LDO regulator is used for on board SOM peripherals. The PMIC supports Real Time Clock functionality.
It uses the Coin cell battery power from D9th pin of Board-to-Board Connector2 for RTC backup power. The PMIC can support
backup battery charging to charge Lithium-Manganese coin cell batteries and super capacitors if required.
2.3.3.2 PMIC Regulator 2 without RTC
The I2C module of Versal AI Edge/Prime SOM is used for PMIC 2 interface through Versal AI Edge pins with I2C address 0x58/0x59.
The 2nd PMIC’s Buck and LDO regulator is used for on SOM peripherals. Also, PMIC supports reset output and connected to Versal
AI Edge (POR_B_503) for power on reset.
Important Note: Every Power Off and On, The DA9062 PMIC work as initial OTP Setting