Sony DP-IF5100 User manual
– 1 –
SERVICE MANUAL
DP-IF5100
MICROFILM
DIGITAL SURROUND PROCESSOR
SPECIFICATIONS
Modulation System Frequency modulation
Carrier wave frequency Right channel 2.8 MHz
Left channel 2.3 MHz
Transmission distance Approx. 10 m to the front
Transmission range 20 – 20,000 Hz
Distortion rate 1% or less (1 kHz)
Audio inputs Optical input
(rectangular-type) ×1
Analog input (pin jack
left/right) ×1
Power requirements DC 9 V (from the
suppliedAC power
adapter)
Dimensions (w/h/d) Approx. 85 ×190 ×180
mm (3 3/8 ×7 1/2 ×7 1/8
inch)
Mass Approx. 1.0 kg
(1000 g) (2 lb 30 oz)
Design and specifications are subject to
change without notice.
•DP-IF5100 is the component model block one in
MDR-DS5100.
COMPONENT MODEL NAME FOR MDR-DS5100
DIGITAL SURROUND PROCESSOR DP-IF5100
CORDLESS STEREO HEADPHONES MDR-IF5000
•Manufactured under license from Dolby Laboratories Licensing
Corporation.
DOLBY, the double-D symbol ;, “PRO LOGIC”,
“Dolby Digital (AC-3)”, and “VIRTUALDOLBY DIGITAL” are
trademarks of Dolby Laboratories Licensing Corporation.
Notes on Chip Component Replacement
•Never reuse a disconnected chip component.
•Notice that the minus side of a tantalum capacitor may be dam-
aged by heat.
E Model
Ver 1.0 1999. 10
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– 2 –
TABLE OF CONTENTS
1. GENERAL
Location and Function of Parts............................................... 3
Listening to the Sound of the Connected Component............ 3
2. DISASSEMBLY
2-1. CoverAssy .......................................................................... 5
2-2. Panel Assy, Front................................................................. 5
2-3. Panel Assy, Sub ................................................................... 6
2-4. TX Board ............................................................................ 6
3. SERVICE MODE
3-1. General ................................................................................ 7
3-2. Setting the Test Mode.......................................................... 7
3-3. Releasing the Test Mode ..................................................... 7
3-4. Test Mode ............................................................................ 7
4. ELECTRICAL ADJUSTMENTS................................... 8
5. DIAGRAMS
5-1. IC Pin Descriptions ............................................................. 9
5-1-1. IC201 µPD784216 (Program, System Control) ............9
5-1-2. IC301 CXD9511AQ (Dolby Digital (AC-3)/
Pro Logic, DTS Decoder)............................................ 11
5-1-3. IC302 XCB56362PV100 (24 Bit Audio Digital
Signal Processor) ......................................................... 13
5-2. Block Diagrams ................................................................ 17
5-2-1. Block Diagram –Processor Section– ........................... 17
5-2-2. Block Diagram –Transmitter Section– ........................ 19
5-3. Printed Wiring Boards and Schematic Diagrams.............. 21
5-3-1. Printed Wiring Board –TX Board– ............................. 21
5-3-2. Schematic Diagram –TX Board (1/2)– ....................... 25
5-3-3. Schematic Diagram –TX Board (2/2)– ....................... 27
5-3-4. Printed Wiring Board –LED Board– ........................... 29
5-3-5. Schematic Diagram –LED Board–.............................. 31
5-3-6. Printed Wiring Board –AMP Board– .......................... 33
5-3-7. Schematic Diagram –AMP Board– ............................. 34
5-4. IC Block Diagrams ........................................................... 35
6. EXPLODEDVIEW........................................................... 38
7. ELECTRICAL PARTS LIST......................................... 39
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– 5 –
SECTION 2
DISASSEMBLY
2-1. COVER ASSY
• The equipment can be removed using the following procedure.
Note : Follow the disassembly procedure in the numerical order given.
2-2. PANEL ASSY, FRONT
Set Cover assy Panel assy, front Panel assy, sub
TX board
3
PTT 2.6X5
5
cover assy
2
PTT 2.6X5
4
PTT 2.6X5
1
PTT 2.6X5
4
CN103
5
CN101
6
P 3X6
7
P 3X6
3
CN102
2
PTT 2.6X5
9
panel assy, front
8
claws
1
screws (2.6x6)
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TEL 13942296513 QQ 376315150 892498299
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– 6 –
2-3. PANEL ASSY, SUB
2-4.TX BOARD
1
P 2X8
3
LED board
4
panel assy, su
b
2
P 2X8
2
screws BTT
4
TX board
1
BVTP 3X8
3
screw BTT
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TEL 13942296513 QQ 376315150 892498299
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– 7 –
SECTION 3
SERVICE MODE
3-1. GENERAL
This set has the test mode of the built-in microprocessor which
allows various check items required repairing.
3-2. SETTINGTHE TEST MODE
Press the POWER key and the EFFECT key at the same time and
turn on the power. (Insert the DC plug)
3-3. RELEASINGTHE TEST MODE
Remove the DC plug.
3-4.TEST MODE
1. LED check
*1) In test mode
*2) All infrared LEDs on
*3) All infrared LEDs on
2. Key check
*4) Corresponding LEDs
POWER key : POWER LED
INPUT key :ANALOG LED
EFFECT key : MUSIC LED
OUTPUT key : VIRTUAL LED
3. Audio check
*5) Digital input check : Do not use this in repair.
*6) Analog input check :Other than MUTE check, do not use this
in repair.
*7) Mute mode : Use this in electrical adjustment (see page 8).
*8)
LCR
LS RS
HR LED
HL LED
4. IF test tone
LEDs go on in sequence *1)
All LEDs on
All LEDs off
POWER,INPUT keys
POWER,INPUT keys
Go to Key check
*3)
*2)
POWER,INPUT keys
Go to Audio check
Press each key and its corresponding
LED goes on *4)
POWER,INPUT keys
Go to IF test tone
ANALOG, HR and HL LEDs on *5) *7)
POWER, DIGITAL,
L and R LEDs on *5)
HL and HR LEDs off *6)
POWER,INPUT keys
POWER,INPUT keys
POWER and MUSIC LEDs on
OUTPUT key
OUTPUT key
OUTPUT key
OUTPUT key
OUTPUT key
OUTPUT key
End of Test mode
1 kHz, –10 dBv
1 kHz, –30 dBv
100 Hz, –30 dBv
10 kHz, –30 dBv
1 kHz, FS
L LED on
C LED on
R LED on
RS LED on
LS LED on
POWER,INPUT keys
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TEL 13942296513 QQ 376315150 892498299
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– 8 –
SECTION 4
ELECTRICAL ADJUSTMENTS
Notes:
1. These adjustments are performed in the order that they are
described.
2. Adjustment and measurement are performed for each channel
unless otherwise specified.
3. Adjustment is made for the right channel first and then the left
channel.
4. The power voltage is supplied with 9 V.
Oscillation Frequency Adjustment
Setting:
+
–
LED board
TP03 or TP04 (L-ch)
TP05 or TP06 (R-ch)
digital frequency
counter
Adjustment method:
• Perform this adjustment without signal.
1. Connect TP (A MUTE) to ground on the TX board (to set the
mute state), or use the test mode to set the mute state (see page
7).
2. Connect a digital frequency counter to TP03 or TP04 for L-ch
and TP05 or TP06 for R-ch on the LED board.
3. Adjust L51 (L-ch) and L1 (R-ch) on the TX board so that the
reading on the digital frequency counter is each within 2.3 MHz
(L-ch) and 2.8 MHz (R-ch).
Specified value:
L-ch L51 2.298 to 2.302 MHz
R-ch L1 2.798 to 2.802 MHz
RF Level Adjustment
Setting:
digital voltmeter
+
–
LED board
TP03 or TP04 (L-ch)
TP05 or TP06 (R-ch)
Adjustment method:
• Perform this adjustment without signal.
1. Connect TP L (L-ch) and TP R (R-ch) to ground on the LED
board (to set the mute state), or use the test mode to set the mute
state (see page 7).
2. Connect a digital voltmeter to TP03 or TP04 for L-ch and TP05
or TP06 for R-ch on the LED board.
3. Adjust RV51 (L-ch) and RV1 (R-ch) on the TX board so that
the reading on the digital voltmeter is 480 mV.
Specified value:
L-ch RV51 477.5 to 482.5 mV
R-ch RV1 477.5 to 482.5 mV
Adjustment Location:
RV51 RF LEVEL
ADJUSTMENT
OSCILLATION
FREQUENCY
ADJUSTMENT
L51
RV1
L1
– TX board (side A) –
TP05
TP06
TP03
TP04
– LED board (conductor side) –
– TX board (side A) –
TP
(A MUTE)
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– 9 –
5-1. IC PIN DESCRIPTIONS
5-1-1. IC201 µPD784216 (PROGRAM, SYSTEM CONTROL)
Pin No. Pin Name I/O Pin Description
1 RTP0/P120 O Analog circuit block mute signal output (H: Mute)
2 RTP1/P121 O D/A mute signal output (H: Mute)
3 RTP2/P122 O IF circuit block power control signal output (H: ON)
4 RTP3/P123 O Main circuit block power control signal output (H: ON)
5 RTP4/P124 O DIR block clock select signal output (H: Digital, L: Analog)
6 RTP5/P125 O DIR serial select signal output
7 RTP6/P126 — Not used. (Open)
8 RTP7/P127 — Not used. (Open)
9 VDD I Power supply pin
10 X2 O Connect to crystal for main system clock oscillator
11 X1 I Connect to crystal for main system clock oscillator
12 VSS — Ground
13 XT2 — Not used. (Open)
14 XT1 — Not used. (Fix to “L”.)
15 RESET I Reset signal input
16 INTP0/P00 I DIR audio data detect signal input
17 INTP1/P01 — Not used. (Open)
18 INTP2/P02 O Sub DSP serial select signal output
19 INTP3/P03 O Decoder serial select signal output
20 INTP4/P04 O Main DSP serial select signal output
21 INTP5/P05 O SLAVE reset signal output
22 INTP6/P06 I DIR lock signal input
23 AVDD I Power supply pin
24 AVREF0 — Ground
25 ANI0/P10 I DSP serial BUSY 5 V signal input
26 ANI1/P11 — Not used. (Open)
27 ANI2/P12 I Not used. (Open)
28 ANI3/P13 I Not used. (Open)
29 ANI4/P14 I Not used. (Open)
30 ANI5/P15 I Auto mute detect signal (L: OFF, H: ON)
31 ANI6/P16 — Not used. (Open)
32 ANI7/P17 I Audio input level signal input
33 AVSS — Analog ground
34 ANO0/P130 — Not used. (Open)
35 ANO1/P131 — Not used. (Open)
36 AVREF1 I Power supply pin
37 SI2 I Main serial data signal input
38 SO2 O Main serial data signal output
39 SCK2 O Main serial clock signal output
40 SI1 I Main serial data signal input
41 SO2 O Not used. (Open)
42 SCK1 O Main serial clock signal output
43 PCL/P23 O Main DSP reset signal output
44 BUZ/P24 — Not used.
45 SI0 I LED/FLASH serial data signal input
46 SO0 O LED/FLASH serial data signal output
47 SCK0 O LED/FLASH serial clock signal output
48 A0/P80 O Main DSP mute signal output
49 A1/P81 O Not used. (Main DSPATT setting bit HIGH)
50 A2/P82 O Not used. (Main DSPATT setting bit LOW)
51 A3/P83 O Main DSPALC ON signal output
SECTION 5
DIAGRAMS
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TEL 13942296513 QQ 376315150 892498299
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– 10 –
Pin No. Pin Name I/O Pin Description
52 A4/P84 O Main DSP VR setting bit HIGH signal output
53 A5/P85 O Main DSP VR setting bit LOW signal output
54 A6/P86 O Reserve terminal (Fix to “L”.)
55 A7/P87 O Reserve terminal (Fix to “L”.)
56 – 63 AD0 – 7/P40 – 47 — Not used. (Open)
64 A8/P50 O Not used. (Open) (LED 0)
65 A9/P51 O Not used. (Open) (LED 1)
66 A10/P52 O Not used. (Open) (LED 2)
67 A11/P53 O Not used. (Open) (LED 3)
68 – 71 A12 – 15/P54 – 57 — Not used. (Open)
72 VSS — Ground
73 A16/P60 I Power on/off key input
74 A17/P61 I INPUT key input
75 A18/P62 I EFFECT key input
76 A19/P63 I OUTPUT key input
77 RD/P64 I Jump key input
78 WR/P65 I Not used. (Open)
79 WAIT/P66 I Not used. (Open)
80 ASTB/P67 I Not used. (Open)
81 VDD I Power supply pin
82 T05/P100 O LEDEN signal output
83 T06/P101 O LEDLAT signal output
84 T07/P102 O LEDRESET signal output
85 T08/P103 — Not used. (Open)
86 T00/P30 — Not used. (Open)
87 T01/P31 — Not used. (Open)
88 T02/P32 — Not used. (Open)
89 T03/P33 — Not used. (Open)
90 T04/P34 — Not used. (Open)
91 TI00/P35 — Not used. (Open)
92 TI01/P36 — Not used. (Open)
93 P37 — Not used. (Open)
94 VPP I VPP signal input
95 – 100 P90 – 95 — Not used. (Open)
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TEL 13942296513 QQ 376315150 892498299
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– 11 –
5-1-2. IC301 CXD9511AQ (DOLBY DIGITAL (AC-3)/PRO LOGIC, DTS DECODER)
Pin No. Pin Name I/O Pin Description
1 VDD1 I Power supply pin (+5 V)
2 RAMCEN — Not used. (Open)
3 • 4 RAM16 • 15 — Not used. (Open)
5 SDIB0 I PCM signal input
6 • 7 SDIB1 • 2 — Not used. (Open)
8 XI I External system clock signal input (12.288 MHz)
9 XO — Not used. (Open)
10 VSS — Ground
11 AVDD I Power supply pin (+3.3 V)
12 SDIB3 — Not used. (Open)
13 • 14 TEST — Test pin
15 OVFB — Not used. (Open)
16 DTSDATA — Not used. (Open)
17 AC3DATA — Not used. (Open)
18 SPDOB3 — Not used. (Open)
19 CPO O PLL signal output
20 AVSS — Ground
21 ADD2 I Power supply pin
22 SDOA2 O PCM signal output (C, LFE output)
23 SDOA1 O PCM signal output (LS, RS output)
24 SDOA0 O PCM signal output (L, R output)
25 – 29 RAMA14 – 10 — Not used. (Open)
30 VSS — Ground
31 VDD1 I Power supply pin (+5 V)
32 – 39 OPORT0 – 7 — Not used. (Open)
40 VSS — Ground
41 VDD2 I Power supply pin (+3.3 V)
42 – 44 RAMA9 – 7 — Not used. (Open)
45 SDOB2 — Not used. (Open)
46 SDOB1 O PCM signal output
47 SDOB0 O PCM signal output
48 SDBCK1 — Not used. (Open)
49 SDWCK1 — Not used. (Open)
50 VSS — Ground
51 VDD2 I Power supply pin (+3.3 V)
52 NONPCM — Not used. (Open)
53 CRC — Not used. (Open)
54 MUTE O Auto mute detect signal output
55 KARAOKE — Not used. (Open)
56 SCRENC — Not used. (Open)
57 SDBCK0 O SDBCK0 turn over clock signal output
58 • 59 RAMA6 • 5 — Not used. (Open)
60 VSS — Ground
61 RAMA4 — Not used. (Open)
62 IC I Initial clear terminal
63 TEST — Test pin
64 RAMA3 — Not used. (Open)
65 CSB I Sub DSP chip select signal input
66 CS I Interface chip select signal input
67 SO O Interface data signal output
68 SI I Interface and sub DSP data signal input
69 SCK I Interface and sub DSP clock signal input
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TEL 13942296513 QQ 376315150 892498299
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– 12 –
Pin No. Pin Name I/O Pin Description
70 RAMA2 — Not used. (Open)
71 VDD1 I Power supply pin (+5 V)
72 – 79 RAMD0 – 7 — Not used. (Open)
80 VSS — Ground
81 VDD2 I Power supply pin (+3.3 V)
82 SDWCK0 I SDIA, SDOA, SDIB and SDOB signal word clock signal input
83 SDBCK0 I SDIA, SDOA, SDIB and SDOB signal bit clock signal input
84 SDIA0 I AC-3/DTS bitstream (or PCM) data signal input
85 SDIA1 I AC-3/DTS bitstream (or PCM) data signal input
86 • 87 RAMA1 • 0 — Not used. (Open)
88 RAMWEN — Not used. (Open)
89 RAMOEN — Not used. (Open)
90 VSS — Ground
91 VDD2 I Power supply pin (+3.3 V)
92 • 93 IPORT7 • 6 I Input port resister pin
94 – 99 IPORT5 – 0 — Not used. (Open)
100 VSS — Ground
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TEL 13942296513 QQ 376315150 892498299
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– 13 –
5-1-3. IC302 XCB56362PV100 (24 BIT AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No. Pin Name I/O Pin Description
1 SCK I SPI serial clock signal input
2 SS I SPI SLAVE select signal input
3 HREQ O Host request signal output
4 SDO0 O Serial data signal output
5 SDO1 O Serial data signal output
6 SDO2 O Serial data signal output
7 SDO3 O Serial data signal output
8 VCCS I Power supply pin
9 GNDS — Ground
10 SDO4 O Serial data signal output
11 SDO5 O Serial data signal output
12 FST I Transmitter frame sync signal input
13 FSR I Receiver frame sync signal input
14 SCKT I Transmitter serial clock signal input
15 SCKR I Receiver serial clock signal input
16 HCKT — Not used. (Open)
17 HCKR — Not used. (Open)
18 VCCQL I Power supply pin
19 GNDQ — Ground
20 VCCQL I Power supply pin
21 HDS — Not used. (Open)
22 HRW — Not used. (Open)
23 HACK — Not used. (Open)
24 HOREQ — Not used. (Open)
25 VCCS I Power supply pin
26 GNDS — Not used. (Open)
27 ADO — Not used. (Open)
28 ACI — Not used. (Open)
29 TIO0 I Timer schmitt trigger signal input
30 HCS — Not used. (Open)
31 HA9 — Not used. (Open)
32 HA8 — Not used. (Open)
33 HAS O Host address strobe signal output
34 HAD7 — Not used.
35 HAD6 — Not used.
36 HAD5 I Host address signal input
37 HAD4 I Host address signal input
38 VCCH I Power supply pin
39 GNDH — Ground
40 HAD3 I Host address signal input
41 HAD2 I Host address signal input
42 HAD1 I Host address signal input
43 HAD0 I Host address signal input
44 RESET I Reset signal input
45 VCCP I Power supply pin
46 PCAP I PLL capacitor connecting pin
47 GNDP — Ground
48 GNDP1 — Ground
49 VCCQH I Power supply pin
50 • 51 AA3 • 2 — Not used. (Open)
52 CAS — Not used. (Open)
53 DE — Not used. (Open)
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TEL 13942296513 QQ 376315150 892498299
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– 14 –
Pin No. Pin Name I/O Pin Description
54 GNDQ — Ground
55 EXTAL I External clock signal input (12.288 MHz)
56 VCCQL I Power supply pin
57 VCCC I Power supply pin
58 GNDC — Ground
59 CLKOUT — Not used. (Open)
60 NC — Not used. (Open)
61 PINIT — Ground
62 TA — Ground
63 BR — Not used. (Open)
64 BB I Bus BUSY signal input
65 VCCC I Power supply pin
66 GNDC — Ground
67 WR — Not used. (Open)
68 RD — Not used. (Open)
69 • 70 AA1 • 0 — Not used. (Open)
71 BG — Ground
72 • 73 A0 • 1 — Not used. (Open)
74 VCCA I Power supply pin
75 GNDA — Ground
76 – 79 A2 – 5 — Not used. (Open)
80 VCCA I Power supply pin
81 GNDA — Ground
82 – 85 A6 – 9 — Not used. (Open)
86 VCCA I Power supply pin
87 GNDA — Ground
88 • 89 A10 • 11 — Not used. (Open)
90 GNDQ — Ground
91 VCCQL I Power supply pin
92 – 94 A12 – 14 — Not used. (Open)
95 VCCQH I Power supply pin
96 GNDA — Ground
97 – 99 A15 – 17 — Not used. (Open)
100 – 102 D0 – 2 — Not used. (Open)
103 VCCD I Power supply pin
104 GNDD — Ground
105 – 110 D3 – 8 — Not used. (Open)
111 VCCB I Power supply pin
112 GNDD — Ground
113 – 118 D9 – 14 — Not used. (Open)
119 VCCD I Power supply pin
120 GNDD — Ground
121 – 125 D15 – 19 — Not used. (Open)
126 VCCQL I Power supply pin
127 GNDQ — Ground
128 D20 — Not used. (Open)
129 VCCD I Power supply pin
130 GNDD — Ground
131 – 133 D21 – 23 — Not used. (Open)
134 MODD — Not used. (Fix to “L”.)
135 MODC I Mode select/external discontinue request signal input
136 MODB I Mode select/external discontinue request signal input
137 MODA I Mode select/external discontinue request signal input
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TEL 13942296513 QQ 376315150 892498299
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– 15 – – 16 –
Pin No. Pin Name I/O Pin Description
138 TRST — Not used. (Open)
139 TDO — Not used. (Open)
140 TDI — Not used. (Open)
141 TCK I Test clock input
142 TMS — Not used. (Open)
143 SI I SPI master data signal input
144 SO — Not used. (Open)
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TEL 13942296513 QQ 376315150 892498299
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DP-IF5100
– 17 – – 18 –
5-2. BLOCK DIAGRAMS
5-2-1. BLOCK DIAGRAM — PROCESSOR SECTION —
4SDO0
SDO2
SDO3
SDO4
SDO5
SCKT
SCKR
18
VCCQL 8
VCCS
VCCQH
VCCH
VCCP
VCCC
VCCA
VCCD
20
38
45
57
74
33
HAS
3
HREQ
5
444340373635342
SDO1
6
7
10
11
8519
11
2
3
6
57
84
3
7
8
1015221312444342
83
82
8
371
3
14
15
12 FST
13 FSR
1SCK
55 EXTAL
143
103
SI
LR DATA
BCK
F1DA
SRESET
LRCK
MCK
AMUTE
DAMUTE
25
ANI0/P10
ANI7/P13
BUSY 5V
NOSG 5V
32
2
1
RTP0/P120
RTP1/P121 73
76
75
74
A17/P61
A18/P62
A19/P63
A16/P60
83
82
TO5/P100
TO6/P101
TO7/P102
47
SCK0 46
SO0
84
4348515253545520
94
VPP
45
SI0
38 SO2
39 SCK2
42 SCK1
18 INTP2/P02
INTP4/PO4
A7/P87
A6/P86
A5/P85
A4/P84
37/P83
A0/P90
PCL/P23
19 INTP3/P03
37 SI2
30 ANI5/P15
68
SI
SDBCK0
SDOB1
IC
SDIB0
SDOB0
SDOA2
SDOA1
SDOA0
69
SCK
65
CSB 66
CS 67
SO 54
MUTE
SO2
BCK
F1DA
SRESET
VPOUT
IF5000SG
CLFSG
CLRSG
LRSG
SCK2
CSSD
CSYM
SI2
YMMUTE
16 INTP0/P00
INTP5/P05
INTP6/P06
RTP4/P124
RTP5/P125
SI1
21
22
5
6
40
3RTP2/P122
4
36
RTP3/P123
AVREF1
23 AVDD
81 VDD
9VDD
15 RESET
1
23
6
5
4
46
62
1
•
31
•
71
11
•
41
•
51
•
81
•
91
3
2
14
13
15
4
13
14
2
3
15
12
I
5
01
I
08
12
I
5
RES
LAT
SIN
SIN
SCK
EN
LAT
RES
SO
SCK
EN
POWER
SELECT
EFFECT
OUTPUT
ANALOG
FRONT END
EIAJ(AES/EBU)
DIGITAL AUDIO
INTERFACE
DECODER
µ-CON
INTERFACE
DECIMATION/
FILTER
DIGITAL
AUDIO
INTERFACE
(1/2)
ANALOG
FRONT END
DELTA
SIGMA
MODULATOR
D OUT
V IN L
V IN R
DDIN
VDD
VDDA
S/P P/S
ASYNCHRONOUS
BUFFER
SYSTEM CLOCK
TIMING OCCURENCE
B+
(SW+5V)
B+
(+5V)
OUT
VCC
X301
12.288MHz
IC306 12M/3V
DISPLAY
LED
D201-208
DISPLAY
LED DRIVE
IC206
DISPLAY
LED DRIVE
IC205
DISPLAY
LED
D209-216
01
I
08
SW
BLOCK
SW1-5
A/D CONVERTER
IC102(1/2)
ATT SW
Q101
LINE AMP
IC101
L
-1
-2
R
J101
LINE INPUT R CH
R CH
B+
(SW+9V)
B+
(SW+5V)
B+
(+3.3V)
SW101
ATT
-8dB
0dB
OPTICAL
RECEIVER
MODULE
IC305
DIGITAL IN
DIGITAL AUDIO,INTERFACE RECEIVER
IC304
DIRSG
/BCK
LRCK
DOUT
MCC
WC
RSTN
12.288M
23 SRESET
B+
(+3.3V)
B+
(+5V) IC303
NOSG3V
BUSY 3V
24BIT AUDIO
DIGITAL
SIGNAL
PROCESSOR
IC302
SS
HAD7
HAD6
HAD5
HAD4
HAD3
HAD0
RESET
CSDSP
TMP3
TMP2
VRSBL
VRSBH
ALCON
TRANSMITTER
SECTION
TRANSMITTER
SECTION
1
TRANSMITTER
SECTION
3
2
SO0
SCK0
LEDEN
LEDLAT
LEDRES
B+
(UN+5.7V)
POWER
LEDPOWER
RESET
PROGRAM,
SYSTEM
CONTROL
IC201
DSPRESET
DSPMUTE
5
47
22
23
24
DOLBY DIGITAL(AC-3)
/PRO LOGIC,DTS
DECODER
IC301
SDIA1
VDD1
SDIA0
VDD2
X1
SDBCK0
SDWCK0
39
24
SI1
CLKSEL
LOCKN
MCK
DIRSCK
CSDIR
IC307(2/2)
IC307(1/2)
• Signal Path
: ANALOG
: DIGITAL
04
LOGIC LEVEL
CONVERTER
(Page 19)
(Page 19)
(Page 19)
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TEL 13942296513 QQ 376315150 892498299
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– 19 – – 20 –
DP-IF5100
5-2-2. BLOCK DIAGRAM — TRANSMITTER SECTION —
18
12
12
13 10
9
5
14
1
8
27
6
5
3
12
4
14
13
9
10
11
16
LOGIC
LEVEL
CONVERTER
2
3
5
17
12 6
6
8
57
3
21
6
57
3
2
SERIAL
DATA
INTERFACE
MULTIBIT
SIGMA-DELTA
MODULATOR
2
24
23
28
CLOCK
CIRCUIT
ATTEN/
MUTE
INTERPOLATION
FILTER DELTA SIGMA
MODULATION BIAS
LPF
&
BUFFER
LPF
&
BUFFER
8x
INTERPOLATOR OUTPUT
BUFFER
DAC
15
11
6
4
2
6
4
2
L51
FREQUENCY
(L-CH)
2.3MHz OSC
COIL
L1
FREQUENCY
(R-CH)
RV1
RF LEVEL
(R-CH)
RV51
RF LEVEL
(L-CH)
2.8MHz OSC
COIL
OSC
Q51 BUFFER
Q52
LED
DRIVE
Q301,351
OSC
Q1
MUTE
Q901
MUTE
Q902
UN5.7V
REG
IC801
RESET
IC204
BUFFER
Q2
!
8
UN+5V
REG
Q903
B+
(UN+5V)
B+
(UN+5.7V)
LF801
PROCESSOR
SECTION
3
PROCESSOR
SECTION
1
PROCESSOR
SECTION
2
LED POWER
POWER
RESET
+3.3V
REG
IC803
B+
(+3.3V)
LR DATA
LR CK
BCK
MCK
SRESET
A MUTE
F1DA
DAMUTE
DIN
16
17
22
28 RESET
CLK/OSC
MANAGER
DIGITAL
AUDIO
INTERFACE
(2/2)
V OUT L
V COM
V OUT R 3
D51
D1
B+
(+9V)
INFRARED
EMITTER
D301-304
B+
(+9V)
INFRARED
EMITTER
D305-308
27
25
B+
(SW+5V)
PD/RST
MUTE
R CH
SDATA
BCK
LRCK
MCLK
R CH
DVDD
STEREO AUDIO DAC SYSTEM
IC105
LPF
IC106
-1
L
-2
R
HEADPHONES
AMP
IC901
HEADPHONES
AMP
IC902
1
J901
PHONES
J801
DC IN 9V
+9V
REG
IC804
+9V
REG
IC805
+5V
REG
IC802
B+
(SW+5V)
B+
(SW+9V)
B+
(+9V)
B+
(UN+5V)
MUTE
VCC 15
D/A CONVERTER
IC102(2/2) BINAURAL L
BINAURAL R
BINAURAL L
BINAURAL R
MUTE SWITCH
IC104 EMPHASIS & LPF
IC103
LED
DRIVE
Q302,352
B+
(SW+5V)
1
7
• Signal Path
: DIGITAL
: ANALOG
: RF
04
26
B+
(UN+5.7V)
PHONES LEVEL
RV901
(Page 18)
(Page 18)
(Page 18)
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
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DP-IF5100
– 21 – – 22 –
1
A
B
C
D
E
F
G
H
I
J
234567891011
TP
(A MUTE)
5-3. PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS
5-3-1. PRINTED WIRING BOARD — TX BOARD —
D1 G-4
D51 F-4
D101 H-10
D102 H-10
D103 G-5
D104 I-10
D201 E-5
D202 B-3
IC101 G-10
IC102 E-6
IC103 F-4
IC104 G-5
IC105 E-7
IC106 G-8
IC201 C-3
IC204 E-3
IC301 D-8
IC302 C-6
IC303 D-4
IC304 E-9
IC306 E-8
IC307 C-4
Q1 G-3
Q2 H-3
Q51 F-3
Q52 F-2
Q101 G-9
Q102 G-10
• Semiconductor
Location
Ref.No. Location
Note:
•X: parts extracted from the component side.
•a: Through hole.
•b: Pattern from the side which enables seeing.
(The other layer’s patterns are not indicated.)
Caution:
Pattern face side: Parts onthe patternfacesideseenfromthe
(Side B) pattern face are indicated.
Parts face side: Parts on the parts face side seen from the
(Side A) parts face are indicated.
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TEL 13942296513 QQ 376315150 892498299
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http://www.xiaoyu163.com
1
A
B
C
D
E
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234567891011
– 23 – – 24 –
DP-IF5100
•Waveforms
1
2
3
4
5
IC102 qh (LRCK)
IC201 qa (X1)
IC301 tj (SDBCK0)
IC302 qs (FST) qd (FSR)
6
IC304 7(MCC)
5Vp-p
21µsec
4.8Vp-p
IC102 qj (BCKIN)
3.2Vp-p
0.3µsec
8MHz
5Vp-p
0.3µsec
5Vp-p
22µsec
5Vp-p
0.3µsec
7
IC304 qs (XI)
3.3Vp-p
12.288MHz
IC305 E-11
IC801 H-8
IC802 I-9
IC803 H-6
IC804 H-9
IC805 I-5
• Semiconductor
Location
Ref.No. Location
(Page 33)
(Page 29)
(Page 30)
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
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DP-IF5100
– 25 – – 26 –
EMPHASIS
&
LPF
5-3-2. SCHEMATIC DIAGRAM —TX BOARD (1/2) — • Refer to page 35 for IC Block Diagrams. • Refer to page 24 forWaveforms.
Note:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
•f: internal component.
•C: panel designation.
•U: B+ Line.
•H: adjustment for repair.
• Power voltage is dc 9 V and fed with regulated dc power
supply from external power voltage jack.
• Voltage and waveforms are dc with respect to ground
under no-signal conditions.
no mark : DIGITAL mode
( ) : ANALOG mode
∗: Impossible to measure
• Voltages aretaken witha VOM (Inputimpedance 10MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
F: ANALOG
J: RF
c:DIGITAL
(Page
34) (Page
31)
(Page
31)
(Page 27, 28)
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
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