Toshiba TMP91C815F Product guide

REV4.2 September 7, 2001
Rev. 4.2 05/September/2001
16bit Micro controller
TLCS-900/L1 series
TMP91C815F
Data Boo
k

contents
Table of Contents
TLCS-900/L1 Devices
TMP91C815F
1. OUTLINEAND DEVICE CHARACTERISTICS 91C815-1
2. PIN ASSIGNMENT AND PIN FUNCTIONS 91C815-4
2.1 PinAssignment Diagram 91C815-4
2.2 Pin Names and Functions 91C815-6
3. OPERATION 91C815-9
3.1 CPU 91C815-9
3.1.1 Reset 91C815-9
3.2 Memory Map 91C815-11
3.3 Triple clock, Stand-by function, Noise reduction 91C815-12
3.4 Interrupts 91C815-36
3.5 Functions of Ports 91C815-51
3.5.1 Port 1 91C815-55
3.5.2 Port 2 91C815-56
3.5.3 Port 5 91C815-58
3.5.4 Port 6 91C815-61
3.5.5 Port 7 91C815-62
3.5.6 Port 8 91C815-68
3.5.7 Port 9 91C815-69
3.5.8 Port A 91C815-70
3.5.9 Port B 91C815-71
3.5.10 Port C 91C815-74
3.5.11 Port D 91C815-77
3.6 Chip Select / Wait Controller 91C815-79
3.7 8-bit Timers(TMRA) 91C815-89
3.8 MMU 91C815-109
3.9 Serial Channel 91C815-120
3.10Serial Bus Interface 91C815-152
3.11Analog / Digital Converter 91C815-181
3.12Watch Dog Timer 91C815-191
3.13RTC 91C815-197
3.14LCD Controller 91C815-211
3.15Melody / Alarm Generator 91C815-229
4. ELECTRICAL CHARACTERISTICS 91C815-235
5. TABLE OF SFR 91C815-248
6. POINTSAND RESTRICTIONS 91C815-272
7. PACKAGES 91C815-274

Data Book modification history
REV/DATE
REV/DATEREV/DATE
REV/DATE page
pagepage
page Modification item
Modification itemModification item
Modification item Reason
ReasonReason
Reason
13,16
23,24 Add to description of DFM operation
154 SBI: BIT2,3 Flocked !Clocked
155 SBI: modify the explanation of BIT6
122 SIO:SC0MOD0 !SC1MOD0
17 CLK: bit0 Fc !fs
225,6 MLD: Add to “TA3OUT” in figure
131 SIO: last !stop in table
All modify of LCDC pages
17 CLK: EMCCR3 のBIT０:２
4 PIN: delete part of P74, P75
7,8 Modify pin name “HRESET, MLDALM”
12 CLK: modify figure
55 PORT1: AD !D8 toD15
62 Modify PORT70’s figure
64 PORT72: delete mistake pin “HRESET”
65 Delete mistake pin “SALEH”
156 SBI: Bit6 Transmitter, Receiver
160 Modify description
166 Add to the figure
Rev40/25-July-2001
115 Add to the figure
Rev41/21-August-2001 14 CPU: modify the figure
Rev42/07-September-2001 247 Murata factory URL added
Rev42/07-September-2001 242 SIO electric charcterestic mistake

TMP91C815
91C815-1
CMOS 16-Bit Microcontrollers
TMP91C815F
1. OUTLINE AND FEATURES
TMP91C815F is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale
equipment.
TMP91C815F comes in a 128-pin flat package.
Listed below are the features.
(1) High-speed 16-bit CPU (900/L1 CPU)
• Instruction mnemonics are upward-compatible with TLCS-90
• 16 Mbytes of linear address space
• General-purpose registers and register banks
• 16-bit multiplication and division instructions; bit transfer and arithmetic instructions
• Micro DMA: 4 channels (1.0 µs/2 bytes at 16 MHz)
(2) Minimum instruction execution time: 148 ns (at 27 MHz)
(3) Built-in RAM: 8 Kbytes
Built-in ROM: None
(4) External memory expansion
• Expandable up to 136M bytes (shared program/data area)
• Can simultaneously support 8-/16-bit width external data bus (Dynamic data bus sizing)
• Separate bus system
(5) 8-bit timers: 4 channels
(6) General-purpose serial interface: 2 channels
• UART/Synchronous mode: 2 channels
• IrDA Ver.1.0 (115.2kbps) mode selectable: 1 channel
(7) Serial bus interface: 1 channel
• I2C bus mode/clock synchronous mode selectable
Purchase of TOSHIBA I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components in a
n
I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance / Handling Precautions.
• TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product
could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used
within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions
set forth in the TOSHIBA Semiconductor Reliability Handbook.
• The products described in this document are subject to foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is
granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
980508TBA1

TMP91C815
91C815-2
(8) LCD controller
• Adapt to both Shift register type and Built-in RAM type LCD driver
(9) Timer for real-time clock (RTC)
• Based on TC8521A
(10) Key-on wake up (Interrupt key input)
(11) 10-bit A/D converter : 8 channels
(12) Watch dog timer
(13) Melody/Alarm generator
• Melody: Output of clock 4 to 5461Hz
• Alarm: Output of the 8 kinds of alarm pattern
• Output of the 5 kinds of interval interrupt
(14) Chip select/Wait controller: 4 channels
(15) MMU
• Expandable up to 136M bytes (4 local area/8bank method)
(16) Interrupts: 39 interrupts
• 9 CPU interrupts: Software interrupt instruction and illegal instruction
• 24 internal interrupts: 7 priority levels are selectable
• 6 external interrupts: 7 priority levels are selectable (among 4 interrupts are selectable
edge mode)
(17) Input/output ports: 61 pins (@External 16-bit data bus memory)
(18) Stand-by function
Three Halt modes: Idle2 (programmable), Idle1 and Stop
(19) Triple-clock controller
• Clock doubler (DFM) circuit is inside
• Clock gear function: Select a High-frequency clock fc/1 to fc/16
• RTC (fs=32.768kHz)
(20) Operating voltage
• VCC = 2.7 V to 3.6 V (fc max = 27 MHz)
• VCC = 1.8 V to 3.6 V (fc max = 10 MHz)
(21) Package
• 128-pin QFP: TQFP128 - P -1414 - 0.4

TMP91C815
91C815-3
Figure 1.1 TMP91C815F Block Diagram

8KB RAM

CPU (TLCS-900/L1)
PC
10-BIT 8CH
A/D
CONVERTER
H-OSC
SIO/UART/IrDA
(SIO0)
8BIT TIMER
(TMRA0)
32 bit F
SR
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W
A
IX
IY
IZ
SP
TXD0
(
PC0
)
RXD0 (PC1
)
TXD1
(
PC3
)
RXD1 (PC4)
CS2F (P73)
DVCC [3]
DVSS [3]
X1
X2
D0 to D7
A0 to A7
A8 to A15
P10 to P17(D8 to D15)
P20 to P27
(A16 toA23)
A
N0 to
A
N7
(P80 to P87
)
AVCC, AVSS
VREFH, VREFL
SCOUT(PD5)
RESET
AM0
AM1
WDT
(Watch
DogTimer)
Clock Gear,
Clock Doubler
SIO/UART
(SIO1)
RD
WR
HWR(P52)
WAIT (P53)
BUSRQ (P54)
BUSAK(P55)
R/W (P56)
L-OSC
EMU0
EMU1

PORT 5
CS/WAIT
CONTROLLER
(4-BLOCK)
PORT 2
CS0 toCS3,CS2A
INTERRUPT
CONTROLLER
INT0 to INT3
KEY-BOARD
I/F KI0 to KI7
(
P90 toP97
)
KO0 to KO7(PA0 to PA7)
MELODY/
ALARM-OUT
MLDALM(PD7)
8BIT TIMER
(TMRA1)
TA1OUT (PB1)

8BIT TIMER
(TMRA2)
8BIT TIMER
(TMRA3)
TA3OUT (PB2
)
( ) : Initial Function After Reset
B C
D E
H L
ADTRG(P83
)
SCLK1/ CTS1(PC5
)
(P60 to P63)
PORT 1
MMU
EA25, CS2C(P65),
LCD
Controller
D1BSCP
(
PD0
)
D2BLP (PD1)
D3BFR (PD2)
DLEBCD (PD3)
DOFFB (PD4)
PORT 6
PORT 7
PORT 8
PORT 9
PORT A
PORT B
PORT C
PORT D
MSK
(
P76
)
VEECLK(P77)
(PB3 to PB6),
SCLK0/CTS0 (PC2
)
OPTRX0,SCK
(
P70
)
OPTTX0,SO/SDA
(P71) SERIAL BUS
I/F(SBI)
SI/SCL
(P72
)
RTC ALARM,MLDALM(PD6)
XT1
XT2
TA0IN (PB0
)
CSEXA (P75)
NMI
EA24, CS2B(P64),
CS2D(P66), CS2E(P67)
CS2G
(
P74
)

TMP91C815
91C815-4
2. PIN ASSIGNMENT AND PIN FUNCTIONS
The assignment of input/output pins for the TMP91C815F, their names and functions are as follows:
2.1 Pin Assignment Diagram
Figure 2.1 shows the pin assignment of the TMP91C815F.
VREFL
TMP91C815F
QFP128
TOPVIEW
1
5
10
15
20
25
30
35
40
45
50 55
60
65
70
75
80
85
90
95
100
105
110
115
120
125
AVSS
AVCC
KI0/P90
KI1/P91
KI2/P92
KI3/P93
KI4/P94
KI5/P95
KI6/P96
KI7/P97
KO0/PA0
KO1/PA1
KO2/PA2
KO3/PA3
KO4/PA4
KO5/PA5
KO6/PA6
KO7/PA7
TA0IN/PB0
TA1OUT/PB1
TA3OUT/PB2
INT0/PB3
INT1/PB4
INT2/PB5
INT3/PB6
TXD0/PC0
RXD0/PC1
SCLK0/CTS0/PC2
TXD1/PC3
AM0
DVCC1
P55/BUSAK
P54/BUSRQ
P53/WAIT
P52/HWR
WR
RD
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
DVCC2
P20/A16
DVSS2
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15/P17 D14/P16
D13/P15
D12/P14
D11/P13
D10/P12
D9/P11
D8/P10
D7
D6
D5
D4
D3
D2 D1
D0
DOFFB/PD4
DLEBCD/PD3
D3BFR/PD2 D2BLP/PD1
D1BSCP/PD0
SCLK1/CTS1/PC
5
RXD1/PC4
EMU1
EMU0
XT2
XT1
RESET
AM1
X1
DVSS1
X2 VREFH
P87/AN7 P86/AN6
P85/AN5
P84/AN4
P83/AN3/ADTRG
P82/AN2
P81/AN1
P80/AN0
DVSS3 NMI
DVCC3
PD7/MLDALM
PD6/ALARM/MLDALM PD5/SCOUT
P77/VEECLK
P76/MSK
P75/CSEXA
P74/CS2G
P73/CS2F
P72/SI/SCL
P71/SO/SDA/OPTTX0
P70/SCK/OPTRX0
P67/CS2E
P66/CS2D
P65/EA25/CS2C P64/EA24/CS2B
P63/CS3
P62/CS2/CS2
A
P61/CS1 P60/CS0
P56/R/W
Figure 2.1.1 Pin assignment diagram (128-pin QFP)

TMP91C815
91C815- 5
2.2 PAD Layout
(Chip size 5.33mm ×5.35mm) I Item (um)
PIN
no Name X point Y point PIN No Name X point Y point PIN No Name X point Y point
1 VREFL -2532 1982 44 PD0 -443 -2542 87 P24 2524 825
2 AVSS -2532 1865 45 PD1 -323 -2542 88 P25 2524 953
3 AVCC -2532 1748 46 PD2 -202 -2542 89 P26 2524 1081
4 P90 -2532 1435 47 PD3 -81 -2542 90 P27 2524 1209
5 P91 -2532 1318 48 PD4 40 -2542 91 /RD 2524 1337
6 P92 -2532 1201 49 D0 160 -2542 92 /WR 2524 1465
7 P93 -2532 1084 50 D1 281 -2542 93 P52 2524 1593
8 P94 -2532 967 51 D2 402 -2542 94 P53 2524 1721
9 P95 -2532 850 52 D3 522 -2542 95 P54 2524 1849
10 P96 -2532 733 53 D4 643 -2542 96 P55 2524 1981
11 P97 -2532 616 54 D5 764 -2542 97 P56 1975 2532
12 PA0 -2532 499 55 D6 885 -2542 98 P60 1858 2532
13 PA1 -2532 382 56 D7 1005 -2542 99 P61 1741 2532
14 PA2 -2532 265 57 P10 1126 -2542 100 P62 1624 2532
15 PA3 -2532 148 58 P11 1247 -2542 101 P63 1507 2532
16 PA4 -2532 31 59 P12 1368 -2542 102 P64 1390 2532
17 PA5 -2532 -86 60 P13 1488 -2542 103 P65 1273 2532
18 PA6 -2532 -203 61 P14 1609 -2542 104 P66 1156 2532
19 PA7 -2532 -320 62 P15 1730 -2542 105 P67 1039 2532
20 PB0 -2532 -437 63 P16 1849 -2542 106 P70 922 2532
21 PB1 -2532 -554 64 P17 1968 -2542 107 P71 805 2532
22 PB2 -2532 -671 65 A0 2524 -1991 108 P72 688 2532
23 PB3 -2532 -788 66 A1 2524 -1864 109 P73 571 2532
24 PB4 -2532 -905 67 A2 2524 -1736 110 P74 454 2532
25 PB5 -2532 -1022 68 A3 2524 -1608 111 P75 337 2532
26 PB6 -2532 -1139 69 A4 2524 -1480 112 P76 220 2532
27 PC0 -2532 -1256 70 A5 2524 -1351 113 P77 102 2532
28 PC1 -2532 -1373 71 A6 2524 -1224 114 PD5 -14 2532
29 PC2 -2532 -1490 72 A7 2524 -1095 115 PD6 -131 2532
30 PC3 -2532 -1607 73 A8 2524 -967 116 PD7 -248 2532
31 AM0 -2532 -1724 74 A9 2524 -839 117 DVCC3 -515 2532
32 DVCC1 -2532 -1991 75 A10 2524 -711 118 /NMI -632 2532
33 X2 -1983 -2542 76 A11 2524 -583 119 DVSS3 -749 2532
34 VDSS1 -1817 -2542 77 A12 2524 -455 120 P80 -1046 2532
35 X1 -1652 -2542 78 A13 2524 -327 121 P81 -1163 2532
36 AM1 -1537 -2542 79 A14 2524 -199 122 P82 -1280 2532
37 /RESET -1416 -2542 80 A15 2524 -71 123 P83 -1397 2532
38 XT1 -1295 -2542 81 DVSS2 2524 57 124 P84 -1514 2532
39 XT2 -1047 -2542 82 P20 2524 185 125 P85 -1631 2532
40 EMU0 -926 -2542 83 DVCC2 2524 313 126 P86 -1748 2532
41 EMU1 -805 -2542 84 P21 2524 441 127 P87 -1865 2532
42 PC4 -685 -2542 85 P22 2524 569 128 VREFH -1982 2532
43 PC5 -564 -2542 86 P23 2524 697
Table 2.2.1 Pad Layout

TMP91C815
91C815-6
2.3 Pin Names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2 Pin names and functions.
Pin Name Number
of Pins I/O Functions
D0 to D7 8 I/O Data (lower): bits 0 to 7 of data bus
P10 to P17
D8 to D15
8 I/O
I/O
Port 1: I/O port that allows I/O to be selected at the bit level
(When used to the external 8bit bus)
Data (upper): bits 8 to15 of data bus
P20 to P27
A16 to A23
8 Output
Output
Port 2: Output port
Address: bits 16 to 23 of address bus
A8 to A15 8 Output Address: bits 8 to 15 of address bus
A0 to A7 8 Output Address: bits 0 to 7 of address bus
RD 1 Output Read: strobe signal for reading external memory
WR 1 Output Write: strobe signal for writing data to pins D0 to D7
P52
HWR
1 I/O
Output
Port 52: I/O port (with pull-up resistor)
High Write: strobe signal for writing data to pins D8 to D15
P53
WAIT
1 I/O
Input
Port 53: I/O port (with pull-up resistor)
Wait: pin used to request CPU bus wait
P54
BUSRQ
1 I/O
Input
Port 54: I/O port (with pull-up resistor)
Bus Request: High-Impedance used to request Bus Release
P55
BUSAK
1 I/O
Output
Port 55: I/O port (with pull-up resistor)
Bus Acknowledge: signal used to acknowledge Bus Release
P56
W/R
1 I/O
Output
Port 56: I/O port (with pull-up resistor)
Read/Write: 1 represents Read or Dummy cycle; 0 represents write cycle.
P60
CS0
1 Output
Output
Port 60:Output port
Chip select 0: Outputs “0” when address is within specified address area.
P61
CS1
1 Output
Output
Port 61:Output port
Chip Select 1: outputs “0” when address is within specified address area
P62
CS2
/CS2A
1 Output
Output
Output
Port 62: Output port
Chip Select 2: outputs “0” when address is within specified address area
Expand Chip Select: 2A: outputs 0 when address is within specified address area
P63
CS3 1 Output Output
Port 63:Output port
Chip Select 3: outputs “0” when address is within specified address area
P64
EA24
/CS2B
1
Output
Output
Output
Port 64: Output port
Chip Select 24: outputs “0” when address is within specified address area
Expand Chip Select: 2B: outputs “0” when address is within specified address area
P65
EA25
/CS2C
1 Output
Output
Output
Port 65: Output port
Chip Select 25: outputs “0” when address is within specified address area
Expand Chip Select: 2C: outputs “0” when address is within specified address area
P66
/CS2D 1 Output Output
Port 66: Output port
Expand Chip Select: 2D: outputs “0” when address is within specified address area
P67
/CS2E 1 Output Output
Port 67: Output port
Expand Chip Select: 2E: outputs “0” when address is within specified address area
Note: An external DMA controller cannot access the device’s built-in memory or built-in I/O devices using the
/BUSRQ and /BUSAK terminal. And in case of using LCDC’s SR mode, don’t use /BUSRQ and /BUSAK
terminal.

TMP91C815
91C815- 7
Pin Name Number
of Pins I/O Functions
P70
SCK
OPTRX0
1 I/O
I/O
Input
Port 70: I/O port
Serial bus interface clock I/O data at SIO mode
Serial recive data “0”
P71
S0
SDA
OPTTX0
1 I/O
Output
I/O
Output
Port 71: I/O port
Serial bus interface send data at SIO mode
Serial bus interface send/recive data at I2C mode
Open drain output mode by programmable (with pull up)
Serial send data “0”
P72
SI
SCL
1 I/O
Output
Port 72I/O port
Serial bus interface recive data at SIO mode
Serial bus interface clock I/O data at I2C mode
Open drain output mode by programmable (with pull up)
P73
/CS2F
1 I/O
Output
Port 73I/O port
Expond Chip Select 2F: outputs outputs “0” when address is within specified address
area
P74
/CS2G
1 I/O
Output
Port 74I/O port
Expond Chip Select 2G: outputs outputs “0” when address is within specified
address area
P75
/CSEXA
1 I/O
Output
Port 75I/O port
Expond Chip Select EXA: outputs outputs “0” when address is within specified
address area
P76
MSK
1 I/O
Input
Port 76I/O port
P77
VEECLK
1 I/O
output
Port 77I/O port
P80 to P87
AN0 to AN7
ADTRG
8 Input
Input
Input
Port 80 to 87 port: Pin used to input ports
Analog input 0 to 7: Pin used to Input to A/D conveter
A/D trigger: Signal used to request A/D start (with used to P83)
P90 to P97
KI0 to KI7
8 Input
Input
Port: 90 to 97 port: Pin used to input ports
Key input 0 to 7: Pin used of Key on wake-up 0 to 7
(shummit input, with pull-up register)
PA0 to PA7
KO0 to KO7
8 Input
Input
Port: A0 to A7 port: Pin used to output ports
Key output 0 to 7: Pin used of Key-scan strobe 0 to 7
PB0
TA0IN
1 I/O
Input
Port B0: I/O port
8bit timer 0 input: Timer 0 input
PB1
TA1OUT
1 I/O
Output
Port B1: I/O port
8bit timer 1 output: Timer 0 input or Timer 1 output
PB2
TA3OUT
1 I/O
Output
Port B2: I/O port
8bit timer 3 output: Timer 2 input or Timer 3 output
PB3
INT0
1 I/O
input
Port B0: I/O port
Interrupt request pin0: Interrupt request pin with programmable level / rising /
falling edge
PB4 to PB6
INT1 to INT3
3 I/O
input
Port B4 to B6: I/O port
Interrupt request pin1 to 3: Interrupt request pin with programmable level / rising
/falling edge
PC0
TXD0
1 I/O
Output
Port C0: I/O port
Serial 0 send data: Open drain output pin by programmable
PC1
RXD0
1 I/O
Output
Port C1: I/O port
Serial 0 recive data

TMP91C815
91C815-8
Pin Name Number
of Pins I/O Functions
PC2
SCLK0
CTS0
1 I/O
Output
I/O
Port C2: I/O port
Serial clock I/O 0
Serial data send enable 0 (Clear to Send)
PC3
TXD1
1 I/O
Output
Port C3: I/O port
Serial send data 1
Open drain output pin by programmable
PC4
RXD1
1 I/O
Input
Port C4: I/O port
Serial recive data 1
PC5
SCLK1
CTS1
1 I/O
I/O
Output
Port C5: I/O port
Serial clock I/O 1
Serial data send enable 1 (Clear to Send)
XT1 1 Input Low Frequency Oscillator connecting pin
XT2 1 Output Low Frequency Oscillator connecting pin
PD0
D1BSCP
1 Output
Output
Port D0: Output port
LCD driver output pin
PD1
D2BLP
1 Output
Output
Port D1: Output port
LCD driver output pin
PD2
D3BFR
1 Output
Output
Port D2: Output port
LCD driver output pin
PD3
DLEBCD
1 Output
Output
Port D3: Output port
LCD driver output pin
PD4
DOFFB
1 Output
Output
Port D4: Output port
LCD driver output pin
PD5
SCOUT
1 Output
Output
Port D5: Output port
System clock output: f
SYS
or f
S
output
PD6
ALARM
1 Output
Output
Port D6: Output port
RTC alarm output pin
PD7
MLDALM
1 Output
Output
Port D7: Output port
Melody / Alarm output pin
NMI 1 Input Non-Maskable Interrupt Request Pin: interrupt request pin with programmable
falling edge level or with both edge levels programmable
AM0 to 1 2 Input Operation mode:
Fixed to AM1=”0”,AM0=”1” 16-bit external bus or 8/16-bit dynamic sizing.
Fixed to AM1=”0”,AM0=”0” 8-bit external bus fixed.
EMU0 1 Output Open pin
EMU1 1 Output Open pin
RESET 1 Input Reset: initializes TMP91C815. (With pull-up resistor)
VREFH 1 Input Pin for reference voltage input to AD converter (H)
VREFL 1 Input Pin for reference voltage input to AD converter (L)
AVCC 1 I/O Power supply pin for AD converter
AVSS 1 GND pin for AD converter (0 V)
X1/X2 2 High-frequency oscillator connection pins
DVCC 3 Power supply pins (All Vcc pins should be connecyed with the power
Supply pin).
DVSS 3 GND pins (0 V) (All pins shuold be connected with GND(0V).

TMP91C815
91C815-9
3. OPERATION
This following describes block by block the functions and operation of the TMP91C815F.
Notes and restrictions for eatch book are outlined in “ 7, Precautions and Restrictions at the end of this manual.
3.1 CPU
The TMP91C815 incorporates a high-performance 16-bit CPU (the 900/L1-CPU). For CPU operation, see
the “TLCS-900/L1 CPU”.
The following describe the unique function of the CPU used in the TMP91C815; these functions are not
covered in the TLCS-900/L1 CPU section.
3.1.1 Reset
When resetting the TMP91C815 microcontroller, ensure that the power supply voltage is within the
operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the
RESET input to Low level at least for 10 system clocks (ten states: 80 µs at 4 MHz).
After Reset, Clock doubler circuit is set to x1 mode, and also Clock gear is set to x1/16 mode. It means
that the initial clock mode starts x1/64 speed mode against the maximum speed of TMP91C815.
When the reset is accept, the CPU:
• Sets as follows the program counter (PC) in accordance with the reset vector stored at address
FFFF00H to FFFF02H:
PC<0 to 7> ←value at FFFF00H address
PC<15 to 8> ←value at FFFF01H address
PC<23 to 16>←value at FFFF02H address
• Sets the stack pointer (XSP) to 100H.
• Sets bits <IFF2:0> of the status register(SR) to 111 (sets the interrupt level mask register to level
7).
• Sets the <MAX> bit of the status register(SR) to 1 (MAX mode).
(Note: As this product does not support MIN mode, do not write a 0 to the <MAX> )
• Clears bits <RFP2:0> of the status register(SR) to 000 (sets the register bank to 0 ).
When reset is released,the CPU starts executing instructions in accordance with the program counter
settings. CPU internal registers not mentioned above do not change when the reset is released.
When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows.
• Initializes the internal I/O registers.
• Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or
output port mode.
(Note1) The CPU internal register(except to PC,SR,XSP) and internal RAM data do not change by
resetting.
Figure 3.1.1 is a reset timing chart of the TMP91C815.

TMP91C815
91C815-10
rea
d
wr
it
e
f
FPH
A23∼0
DATA-IN
D0∼1
5
D0∼1
5
sampling
(After reset released,,startting 2 wait read cycle)
Note
)
Pull-up (internal)
High-z
DATA-OUT
sampling
(P52 input mode)
RESET
RD
W
R
HW
R
/CS0,1, 3,
0FFFF00H
/CS2
DATA-IN
XT1,XT2
Figure 3.1.1 TMP91C815 Reset Timing Chart

TMP91C815
91C815-11
3.2 Memory Map
Figure 3.2.1 is a memory map of the TMP91C815.
000000H
001000H
16Mbyte area
(R)
(−R)
(R+)
(R +R8/16)
(R +d8/16)
(nnn)
Direct
area
(
n
)
64Kbyte area
(nn)
Internal I/O
(4KByte)
Internal RAM
(8K Byte)
003000H
010000H
(=Internal area)
FFFF00H
FFFFFFH Vector table
(
256 B
y
te
)
External memory
000100H
000FE0H
Figure 3.2 1 Memory Map
Note : Address 000FE0H – 00FFFH is assigned for the external memory area of Built-in RAM type LCD
driver.

TMP91C815
91C815-12
3.3 Triple Clock Function and Standby Function
TMP91C815 contains (1) a clock gear, (2) clock doubler (DFM), (3) stand-by controller and (4)
noise-reduction circuit. It is used for low-power, low-noise systems.
This chapter is organized as follows.
The clock operating modes are as follows: (a) Single Clock Mode (X1, X2 pins only), (b) Dual Clock Mode
(X1, X2, XT1 and XT2 pins) and (c) Triple Clock Mode (the X1, X2, XT1 and XT2 pins and DFM).
Figure 3.3.1 shows a transition figure.

TMP91C815
91C815-13
Using DFM
*NOTE
Reset
(fOSCH/32)
release Reset
instruction
interrupt STOP mode
(Stops all circuits)
NORMAL mode
(f
OSCH
/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
(a) Single clock mode transition figure
(b) Dual clock mode transition fiigure
STOP mode
(Stops all circuits)
SLOW mode
(fs/2)
Reset
(fOSCH/32)
release Reset
NORMAL mode
(f
OSCH
/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
Reset
(fOSCH/32)
release Reset
NORMAL mode
(f
OSCH
/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
STOP mode
(Stops all circuits)
SLOW mode
(fs/2)
NORMAL mode
(4 ×fOSCH/gear
value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate oscillator and DFM)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
(c) Triple clock mode trasision Figure
instruction
instruction
interrupt
interrupt
instruction
instruction
interrupt
interrupt
instruction
instruction
interrupt
interrupt
instruction
interrupt
instruction
instruction
interrupt
interrupt
instruction instruction
instruction interrupt
*NOTE)
・ It’s prohibited to control DFM in SLOW mode when shifting from SLOW mode to NORMAL mode with use o
f
DFM.（DFM Start up/Stop/Change Write to DFMCR0<ACT1:0> resister）
・ If you shift from NORMAL mode with use of DFM to NORMAL mode, the instruction should be separated into
two procedures as below. Change CPU clock ->Stop DFM circuit
・ It’s prohibited to shift from NORMAL mode with use of DFM to STOP mode directly. You should set NORMAL
mode once, and then shift to STOP mode.(You should stop high frequency oscillator after you stop DFM.)
*NOTE
instruction
Figure 3.3.1 System clock block diagram
The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The
clock frequency selected by SYSCR1<SYSCK> is called the system clock f
FPH
. The system clock f
SYS
is defined as the divided clock of
f
FPH
, and one cycle of f
SYS
is regret to as one state.

TMP91C815
91C815-14
3.3.1 Block diagram of system clock
Clock gear
SYSCR1<SYSCK>
TMRA0 to 3
SYSCR0
<PRCK1, PRCK 0>
selector
fs
f
OSCH
Low-Frequency
oscillator
XT1
XT2
SYSCR0
<XTEN, RXTEN>
Warming up timer (High/Low frequency
oscillator), Lock up timer (DFM)
SYSCR0<WUEF>
SYSCR2<WUPTM1, WUPTM 0>
DFMCR0<ACT1, ACT 0, DLUPTM>
X1
X2
Clock Doubler
(DFM)
f
DFM
=f
OSCH
×4
÷2÷16 ÷4
fc/16
fc/8
fc/4
fc/2
fc
DFMCR0<ACT1, ACT 0>
SYSCR1<GEAR2, GEAR 0>
÷2÷4
fc/16
f
FPH
f
SYS
÷2
f
SYS
CPU
RAM
ADC
Interrupt
controller
WDT
I/O ports
prescaler
φT0
SIO0 to1
SBI
RTC
φT
fs
φT0
fs
φT
SYSCR0
<XEN, RXTEN>
High-Frequency
oscillator
÷8
prescaler
prescaler
LCDC
MLD/ALM
Figure 3.3.2 Block Diagram of System clock

TMP91C815
91C815-15
3.3.2 SFR
7 6 5 4 3 2 1 0
bit Symbol XEN XTEN RXEN RXTEN RSYSCK WUEF PRCK1 PRCK0
Read/Write R/W
After reset 1 1 1 0 0 0 0 0
Function
High-frequen
cyoscillator
(fc)
0: Stop
1: Oscillation
Low-frequen
cyoscillator
(fs)
0: Stop
1: Oscillation
High-frequen
cyoscillator
(fc) after
release of
Stop Mode
0: Stop
1: Oscillation
Low-frequen
cyoscillator
(fs) after
release of
Stop Mode
0: Stop
1: Oscillation
Selects clock
after release
of Stop
Mode
0: fc
1: fs
Warm-up
Timer
0: Write
Don’t care
1: Write
start timer
0: Read
end warm-up
1: Read
do not end
warm-up
Select prescaler clock
00: f
FPH
01: reserved
10: fc/16
11: reserved
7 6 5 4 3 2 1 0
bit Symbol SYSCK GEAR2 GEAR1 GEAR0
Read/Write R/W
After reset 0 1 0 0
Function
Select
system clock
0: fc
1: fs
Select gear value of high frequency (fc)
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (reserved)
110: (reserved)
111: (reserved)
7 6 5 4 3 2 1 0
bit Symbol SCOSEL WUPTM1 WUPTM0 HALTM1 HALTM0 SELDRV DRVE
Read/Write R/W R/W R/W R/W R/W R/W R/W
After reset 0 1 0 1 1 0 0
Function
0: fs
1: f
SYS
Warm-Up Timer 00: reserved
01: 2
8
/inputted frequency
10:2
14
11:2
16
HALT mode
00: reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
<DRVE>
mode
select
0: STOP
1: IDLE1
Pin state
control in
STOP mode
0: I/O off
1: Remains
the state
before
HALT
SYSCR0
(00E0H)
SYSCR1
(00E1H)
SYSCR2
(00E2H)
(note1) By Reset, low-frequency oscillator is enable.
(note2) In case of using built-in SBI circuit, it must set SYSCR0<PRCK1:0> to ‘00’.
Figure 3.3.3 SFR for system clock

TMP91C815
91C815-16
Symbol Name Address 7 6 5 4 3 2 1 0
ACT1 ACT0 DLUPFG DLUPTM
R/W R/W R R/W
0 0 0 0
DFM LUP select fFPH
DFMCR0
DFM
Control
Register 0
E8H
00
01
10
11
STOP
RUN
RUN
RUN
STOP
RUN
STOP
STOP
fOSCH
fOSCH
fDFM
fOSCH
Lock up
Status Flag
0: end
1: not end
Lock-up Time
0: 2
12
/fOSCH
1: 2
10
/fOSCH
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 1 0 0 1 1
DFMCR1
DFM
Control
Register 1
E9H
DFM revision
Input frequency 4~6.75MHz(@2.7V~3.6V) : write “0BH”
Input frequency 1~2.5MHz(@2.0±10%) : write “1BH”
Figure 3.3.4 SFR for DFM
Limitation point on the use of DFM
1. It’s prohibited to execute DFM enable/disable control in the SLOW mode(fs)
(write to DFMCR0<ACT1:0>=”10”). You should control DFM in the NORMAL mode.
2. If you stop DFM operation during using DFM(DFMCR0<ACT1:0>=”10”) , you shouldn’t execute that
change the clock f
DFM
to f
OSCH
and stop the DFM at the same time. Therefore the above execution should be
separated into two procedures as showing below.
LD (DFMCR0),C0H ;change the clock f
DFM
to f
OSCH
LD (DFMCR0),00H ;DFM stop
3. If you stop high frequency oscillator during using DFM (DFMCR0<ACT1:0>=”10”) , you should stop DFM
before you stop high frequency oscillator.
Please refer to 3.3.5 Clock Doubler (DFM) for the details.

TMP91C815
91C815-17
7 6 5 4 3 2 1 0
bit Symbol PROTECT TA3LCDE – – – EXTIN
DRVOSCH DRVOSCL
Read/Write R R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 1 0 0 0 1 1
Function
Protect flag
0: OFF
1: ON
LCDC source
CLK
0: 32KHz
1: TA3OUT
Write “1” Write “0” Write “0” 1: External
clock
fc oscillator
driver ability
1: NORMAL
0: WEAK
fs oscillator
driver ability
1: NORMAL
0: WEAK
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Switching the protect ON/OFF by write to following 1
st
-KEY,2
nd
-KEY
1
st
-KEY: EMCCR1=5AH,EMCCR2=A5H in succession write
2
nd
-KEY: EMCCR1=A5H,EMCCR2=5AH in succession write
bit Symbol ENFROM ENDROM ENPROM FFLAG
DFLAG PFLAG
Read/Write R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0
CS1A write
Operation flag
CS2B-2G
write peration
Flag
CS2A write
Operation
Flag
Function
CS1A area
detect control
0: disable
1: enable
CS2B-2G
area detect
control
0: disable
1: enable
CS2A area
detect control
0: disable
1: enable
Whenreading Whenwriting
“0” : not written “0” : clear flag
“1” : written
EMCCR0
(00E3H)
EMCCR1
(00E4H)
EMCCR2
(00E5H)
EMCCR3
(00E6H)
(note) In case of Vcc=2V±10% use, fixed to EMCCR0<DRV0SCH>=’1’.
Figure 3.3.5 SFR for noise-reduction