Toshiba TLCS-900/H1 Series User manual

TOSHIBA Original CMOS 32-Bit Microcontroller
TLCS-900/H1 Series
TMP92CH21FG
Semiconductor Company

Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.

TMP92CH21
2009-06-19
92CH21-1
CMOS 32-bit Microcontroller
TMP92CH21FG/JTMP92CH21
1. Outline and Device Characteristics
The TMP92CH21 is a high-speed advanced 32-bit Microcontroller developed for controlling
equipment which processes mass data.
The TMP92CH21 has a high-performance CPU (900/H1 CPU) and various built-in I/Os.
The TMP92CH21FG is housed in a 144-pin flat package. The JTMP92CH21 is a chip form
product.
Device characteristics are as follows:
(1) CPU: 32-bit CPU (900/H1 CPU)
•Compatible with TLCS-900/L1 instruction code
•16 Mbytes of linear address space
•General-purpose register and register banks
•Micro DMA: 8 channels (250 ns/4 bytes at fSYS = 20 MHz, best case)
(2) Minimum instruction execution time: 50 ns (at fSYS = 20 MHz)
(3) Internal memory
•Internal RAM: 16 Kbytes (can be used for program, data and display memory)
•Internal ROM: 8 Kbytes (used as boot program)
Possible downloading of user program through either USB,
UART or NAND flash.
(4) External memory expansion
•Expandable up to 512 Mbytes (shared program/data area)
•Can simultaneously support 8,- 16- or 32-bit width external data bus
... dynamic data bus sizing
•Separate bus system
(5) Memory controller
•Chip select output: 4 channels
(6) 8-bit timers: 4 channels
(7) 16-bit timer/event counter: 1 channel
(8) General-purpose serial interface: 2 channels
•UART/synchronous mode: 2 channels (channel 0 and 1)
•IrDA ver.1.0 (115 kbps) mode selectable: 1 channel (channel 0)

TMP92CH21
2009-06-19
92CH21-2
(9) USB (universal serial bus) controller: 1 channel
•Compliant with USB ver.1.1
•Full-speed (12 Mbps) (Low-speed is not supported.)
•Endpoints spec
Endpoint 0: Control 64 bytes* 1-FIFO
Endpoint 1: BULK (out) 64 bytes* 2-FIFO
Endpoint 2: BULK (in) 64 bytes* 2-FIFO
Endpoint 3: Interrupt (in) 8 bytes* 1-FIFO
•Descriptor RAM: 384 bytes
(10) I2S (Inter-IC sound) interface: 1 channel
•I2S bus mode/SIO mode selectable (Master, transmission only)
•32-byte FIFO buffer
(11) LCD controller
•Supports up to 4096 color for TFT, 256 color, 16, 8, 4 gray levels and B/W for STN
•Shift register/built-in RAM LCD driver
(12) SDRAM controller: 1 channel
•Supports 16 M, 64 M, 128 M, 256 M, and up to 512-Mbit SDR (Single Data Rate)-SDRAM
•Possible to execute instruction on SDRAM
(13) Timer for real-time clock (RTC)
(14) Key-on wakeup (Interrupt key input)
(15) 10-bit AD converter: 4 channels
(16) Touch screen interface
•Available to reduce external components
(17) Watchdog timer
(18) Melody/alarm generator
•Melody: Output of clock 4 to 5461 Hz
•Alarm: Output of 8 kinds of alarm pattern and 5 kinds of interval interrupt
(19) MMU
•Expandable up to 512 Mbytes (3 local area/8 bank method)
•Independent bank for each program, read data, write data and LCD display data
(20) Interrupts: 50 interrupt
•9 CPU interrupts: Software interrupt instruction and illegal instruction
•34 internal interrupts: Seven selectable priority levels
•7 external interrupts: Seven selectable priority levels (6-edge selectable)
(21) Input/output ports: 82 pins (Except Data bus (16bit), Address bus (24bit) and RD pin)
(22) NAND flash interface: 2 channels
•Direct NAND flash connection capability
•ECC calculation (for SLC- type)

TMP92CH21
2009-06-19
92CH21-3
(23) Stand-by function
•Three HALT modes: IDLE2 (programmable), IDLE1, STOP
•Each pin status programmable for stand-by mode
(24) Triple-clock controller
•Clock doubler (PLL) supplies 48 MHz for USB, 36 MHz system-clock for others
•Clock gear function: Select high-frequency clock fc to fc/16
•RTC (fs =32.768 kHz)
(25) Operating voltage:
•VCC =3.0 V to 3.6 V (fc max =40 MHz)
•VCC =2.7 V to 3.6 V (fc max =27 MHz)
(26) Package:
•144-pin QFP (LQFP144-P-1616-0.40C)
•144-pin chip form is also available. For details, contact your local Toshiba sales
representative.

TMP92CH21
2009-06-19
92CH21-4
Figure 1.1 TMP92CH21 Block Diagram
10-bit
4-channel
AD converter
Serial I/O
SIO0
Serial I/O SIO1
D+
D−
(I2SCKO, TXD0) P90
(I2SDO, RXD0) P91
(I2SWS, SCLK0, 0CTS ) P92
8-bit timer
(TIMERA0)
8-bit timer
(TIMERA1)
8-bit timer
(TIMERA2)
8-bit timer
(TIMERA3)
(TB0OUT0, INT2) PC2
(INT3) PC3 16-bit timer
(TIMERB0)
SDRAM
controller
(LCP0) PK0
(LLP) PK1
(LFR) PK2
(LBCD) PK3
PL0 to PL7
(
LD0 to LD7
)
WA
BC
DE
HL
IX
I
Y
IZ
SP
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
Watchdog timer
8-KB mask ROM
(Boot program)
Port 1
Port 7
NAND flash
I/F (2 channel)
H-OSC
Interrupt
controller
DVCC [4]
DVSS [3]
X1
X2
P10 to P17
(D8 to D15)
32 bits F
SR
PC
900/H1 CPU
Touch
screen
I/F (TSI)
USB
controller
I2S
Port 9
LCD
controller
PLL
Clock gear
L-OSC XT1
XT2
Port 2
Port 3
Port 4
Port 5
Port 6
D0 to D7
Port 8
Keyboard
I/F
RTC
Melody/
Alarm out
16-KB RAM
MMU
(LGOE0) P93
(LGOE1) P94
(LGOE2, CLK32KO) P95
(TA1OUT, INT0) PC0
(TA3OUT, INT1) PC1
P20 to P27
(D16 to D23, KO0 to KO7)
P30 to P37
(D24 to D31)
P40 to P47
(A0 to A7)
P50 to P57
(A8 to A15)
P60 to P67
(A16 to A23)
PA0 to PA7 (KI0 to KI7,
LD8 to LD11)
PC6
(
KO8, LDIV
)
PM1 (MLDALM)
PG0 to PG1
(AN0 to AN1)
AN2/MX (PG2)
AN3/MY/ ADTRG (PG3)
AVCC, AVSS
VREFH, VREFL
(PX, INT4) P96
(PY, INT5) P97
(SDRAS ,SRLLB ) PJ0
(SDCAS ,SRLUB ) PJ1
(SDWE ,SRWR ) PJ2
(SDLLDQM) PJ3
(SDLUDQM) PJ4
(NDALE, SDULDQM) PJ5
(NDCLE, SDUUDQM) PJ6
(SDCKE) PJ7
(SDCLK) PF7
RESET
A
M0
A
M1
P70 (RD )
P71 ( WRLL , NDRE )
P72 ( WRLU , NDWE )
P73 (EA24)
P74 (EA25)
P75 (R/ W, NDR/B)
P76 ( WAIT )
P80 ( 0CS )
P81 ( 1CS , SDCS )
P82 ( 2CS , CSZA , SDCS )
P83 ( 3CS )
P84 ( CSZB , WRUL , CE0ND )
P85 ( CSZC , WRUU , CE1ND )
P86 ( CSZD , SRULB )
P87 ( CSZE , SRUUB )
PC7
(
CSZF
,
LCP1
)
TEST
PM2 ( ALARM , MLDALM )
(TXD0, TXD1) PF0
(RXD0, RXD1) PF1
(SCLK0,SCLK1) PF2

TMP92CH21
2009-06-19
92CH21-5
2. Pin Assignment and Functions
The assignment of input/output pins for the TMP92CH21FG, their names and functions are
as follows:
2.1 Pin Assignment
Figure 2.1.1 Pin Assignment Diagram (144-pin QFP)
TMP92CH21FG
QFP144
Top View
P67, A23
P66, A22
P65, A21
P64, A20
DVCC3
P63, A19
P62, A18
P61, A17
P60, A16
P57, A15
P56, A14
P55, A13
P54, A12
P53, A11
P52, A10
P51, A9
P50, A8
P47, A7
P46, A6
P45, A5
P44, A4
P43, A3
P42, A2
P41, A1
P40, A0
P37, D31
P36, D30
DVSS3
P35, D29
P34, D28
P33, D27
P32, D26
P31, D25
P30, D24
P27, D23, KO7
P26, D22, KO6
VREFL
VREFH
PG0, AN0
PG1, AN1
PG2, AN2, MX
PG3, AN3, ADTRG , MY
P96, PX, INT4
P97, PY, INT5
PA3, KI3, LD8
PA4, KI4, LD9
PA5, KI5, LD10
PA6, KI6, LD11
PA7, KI7
P90, TXD0, I2SCKO
P91, RXD0, I2SDO
P92, SCLK0, 0CTS , I2SWS
P93, LGOE0
P94, LGOE1
P95, CLK32KO, LGOE2
PC2, TB0OUT0, INT2
PL0, LD0
PL1, LD1
PL2, LD2
PL3, LD3
PL4, LD4
PL5, LD5
PL6, LD6
PL7, LD7
PK0, LCP0
PK1, LLP
PK2, LFR
PK3, LBCD
PM2, ALARM ,MLDALM
PM1, MLDALM
XT1
XT2
DVCC4
TEST
D+ D−
DVCC1
X1
DVSS1
X2
AM0 AM1
RESET
PC3, INT3
DVSS2
DVCC2
D0 D1 D2 D3 D4 D5 D6 D7
P10, D8 P11, D9
P12, D10 P13, D11 P14, D12 P15, D13 P16, D14 P17, D15
P20, D16, KO0 P21, D17, KO1 P22, D18, KO2 P23, D19, KO3 P24, D20, KO4 P25, D21, KO5
A
VCC
A
VSS
PA2, KI2 PA1, KI1 PA0, KI0 PJ7, SDCKE PJ6, SDUUDQM, NDCLE PJ5, SDULDQM, NDALE PJ4, SDLUDQM PJ3, SDLLDQM PJ2, SDWE, SRWR
PJ1, SDCAS, SRLUB
PJ0, SDRAS, SRLLB
PF7, SDCLK PC1, TA3OUT, INT1 PC0, TA1OUT, INT0 PF2, SCLK0, CTS0, SCLK1, CTS1
PF1, RXD0, RXD1 PF0, TXD0, TXD1 PC7, CSZF, LCP1
P87, CSZE, SRUUB
P86, CSZD, SRULB
P85, CSZC, WRUU, ND1CE
P84, CSZB, WRUL, ND0CE
P83, CS3
P82, CS2, CSZA, SDCS
P81, CS1, SDCS
PC6, KO8, LDIV P80, CS0
P76, WAIT
P75, R/W, NDR/B P74, EA25 P73, EA24 P72, WRLU, NDWE
P71, WRLL, NDRE
P70, RD
1
5
10
15
20
25
30
35
105
100
95
90
85
80
75
140 135 130 125 120 115 110
40 45 50 55 60 65 70

TMP92CH21
2009-06-19
92CH21-6
2.2 PAD Assignment
(Chip size 5.98 mm ×6.42 mm)
Table 2.2.1 Pad Assignment Diagram (144-pin chip) Unit: μm
Pin
No Name X Point Y Point Pin No Name X Point Y Point Pin No Name X Point Y Point
1 VREFL −2852 2671 49 DVSS2 −488 −3072 97 P55 2848 815
2 VREFH −2852 2546 50 DVCC2 −338 −3072 98 P56 2848 941
3 PG0 −2852 2421
51 D0 −200 −3072 99 P57 2848 1066
4 PG1 −2852 2296 52 D1 −75 −3072 100 P60 2848 1191
5 PG2 −2852 2171 53 D2 49 −3072 101 P61 2848 1316
6 PG3 −2852 2045
54 D3 174 −3072 102 P62 2848 1441
7 P96 −2852 1920 55 D4 300 −3072 103 P63 2848 1566
8 P97 −2852 1795 56 D5 425 −3072 104 DVCC3 2848 1692
9 PA3
−2852 1270
57 D6 550 −3072 105 P64 2848 1823
10 PA4 −2852 1145 58 D7 675 −3072 106 P65 2848 1974
11 PA5 −2852 1020 59 P10 800 −3072 107 P66 2848 2130
12 PA6 −2852 895 60 P11 925 −3072 108 P67 2848 2292
13 PA7 −2852 769 61 P12 1050 −3072 109 P70 2460 3065
14 P90 −2852 644 62 P13 1176 −3072 110 P71 2295 3065
15 P91 −2852 519 63 P14 1301 −3072 111 P72 2127 3065
16 P92 −2852 394 64 P15 1426 −3072 112 P73 1964 3065
17 P93 −2852 269 65 P16 1551 −3072 113 P74 1807 3065
18 P94 −2852 144 66 P17 1676 −3072 114 P75 1654 3065
19 P95 −2852 18 67 P20 1801 −3072 115 P76 1506 3065
20 PC2 −2852 −106 68 P21 1927 −3072 116 P80 1361 3065
21 PL0 −2852 −231 69 P22 2052 −3072 117 PC6 1226 3065
22 PL1 −2852 −356 70 P23 2177 −3072 118 P81 1101 3065
23 PL2 −2852 −481 71 P24 2303 −3072 119 P82 976 3065
24 PL3 −2852 −606 72 P25 2460 −3072 120 P83 851 3065
25 PL4 −2852 −732 73 P26 2848 −2279 121 P84 726 3065
26 PL5 −2852 −857 74 P27 2848 −2138 122 P85 600 3065
27 PL6 −2852 −982 75 P30 2848 −1982 123 P86 475 3065
28 PL7 −2852 −1107 76 P31 2848 −1831 124 P87 350 3065
29 PK0 −2852 −1232 77 P32 2848 −1687 125 PC7 225 3065
30 PK1 −2852 −1357 78 P33 2848 −1562 126 PF0 100 3065
31 PK2 −2852 −1482 79 P34 2848 −1437 127 PF1 −24 3065
32 PK3 −2852 −1608 80 P35 2848 −1311 128 PF2 −150 3065
33 PM2 −2852 −1892 81 DVSS3 2848 −1186 129 PC0 −275 3065
34 PM1 −2852 −2017 82 P36 2848 −1061 130 PC1 −400 3065
35 XT1 −2852 −2142 83 P37 2848 −936 131 PF7 −525 3065
36 XT2 −2852 −2444 84 P40 2848 −811 132 PJ0 −650 3065
37 DVCC4 −2465 −3072 85 P41 2848 −686 133 PJ1 −775 3065
38 TEST −2339 −3072 86 P42 2848 −560 134 PJ2 −901 3065
39 D+−2062 −3072 87 P43 2848 −435 135 PJ3 −1026 3065
40 D−−1875 −3072 88 P44 2848 −310 136 PJ4 −1151 3065
41 DVCC1 −1598 −3072 89 P45 2848 −185 137 PJ5 −1276 3065
42 X1 −1472 −3072 90 P46 2848 −60 138 PJ6 −1401 3065
43 DVSS1 −1347 −3072 91 P47 2848 65 139 PJ7 −1526 3065
44 X2 −1126 −3072 92 P50 2848 190 140 PA0 −1652 3065
45 AM0 −1001 −3072 93 P51 2848 315 141 PA1 −1777 3065
46 AM1 −876 −3072 94 P52 2848 440 142 PA2 −1902 3065
47 RESET −750 −3072 95 P53 2848 565 143 AVSS −2275 3065
48 PC3 −625 −3072 96 P54 2848 690 144 AVCC −2400 3065

TMP92CH21
2009-06-19
92CH21-7
2.3 Pin Names and Functions
The following table shows the names and functions of the input/output pins
Table 2.3.1 Pin Names and Functions (1/5)
Pin Name Number of
Pins I/O Function
D0 to D7 8 I/O Data: Data bus 0 to 7
P10 to P17
D8 to D15 8 I/O I/O Port 1: I/O port input or output specifiable in units of bits Data: Data bus 8 to 15
P20 to P27
D16 to D23
KO0 to KO7 8 I/O
I/O
Output
Port 2: I/O port input or output specifiable in units of bits
Data: Data bus 16 to 23
Key output 0 to 7: Pins used of key-scan strobe (Open-drain output programmable)
P30 to P37
D24 to D31 8 I/O I/O Port 3: I/O port input or output specifiable in units of bits Data24: Data bus 24 to 31
P40 to P47
A0 to A7 8 Output Output Port 4: Output port Address: Address bus 0 to 7
P50 to P57
A8 to A15 8 Output Output Port 5: Output port Address: Address bus 8 to 15
P60 to P67
A16 to A23 8 I/O Output Port 6: I/O port input or output specifiable in units of bits Address: Address bus 16 to 23
P70
RD 1 Output Output Port70: Output port Read: Outputs strobe signal to read external memory
P71
WRLL
NDRE 1 I/O
Output
Output
Port 71: I/O port
Write: Output strobe signal for writing data on pins D0 to D7
NAND flash read: Outputs strobe signal to read external NAND flash
P72
WRLU
NDWE 1 I/O
Output
Output
Port 72: I/O port
Write: Output strobe signal for writing data on pins D8 to D15
Write Enable for NAND flash
P73
EA24 1 Output Output Port 73: Output port Extended Address 24
P74
EA25 1 Output Output Port 74: Output port Extended Address 25
P75
WR/
NDR/B 1 I/O
Output
Input
Port 75: I/O port
Read/Write: 1 represents read or dummy cycle; 0 represents write cycle
NAND flash ready (1)/Busy (0) input
P76
WAIT 1 I/O Input Port 76: I/O port Wait: Signal used to request CPU bus wait

TMP92CH21
2009-06-19
92CH21-8
Table 2.3.2 Pin Names and Functions (2/5)
Pin Name Number of
Pins I/O Function
P80
0CS 1 Output
Output Port80: Output port Chip select 0: Outputs “low” when address is within specified address area
P81
1CS
SDCS 1 Output
Output
Output
Port81: Output port
Chip select 1: Outputs “low” when address is within specified address area
Chip select for SDRAM: Outputs “0” when address is within SDRAM address area
P82
2CS
CSZA
SDCS
1
Output
Output
Output
Output
Port82: Output port
Chip select 2: Outputs “Low” when address is within specified address area
Expand chip select: ZA: Outputs “0” when address is within specified address area
Chip select for SDRAM: Outputs “0” when address is within SDRAM address area
P83
3CS 1 Output
Output Port83: Output port Chip select 3: Outputs “low” when address is within specified address area
P84
WRUL
CSZB
CE0ND
1
Output
Output
Output
Output
Port84: Output port
Write: Output strobe signal for writing data on pins D16 to D23
Expand chip select: ZB: Outputs “0” when address is within specified address area
Chip select for NAND flash 0: Outputs “0” when NAND flash 0 is enabled
P85
WRUU
CSZC
CE1ND
1
Output
Output
Output
Output
Port85: Output port
Write: Output strobe signal for writing data on pins D24 to D31
Expand chip select: ZC: Outputs “0” when address is within specified address area
Chip select for NAND flash 1: Outputs “0” when NAND flash 1 is enabled
P86
CSZD
SRULB 1 Output
Output
Output
Port86: Output port
Expand chip select: ZD: outputs “0” when address is within specified address area
Data enable for SRAM on pins D16 to D23
P87
CSZE
SRUUB 1 Output
Output
Output
Port87: Output port
Expand chip select: ZE: Outputs “0” when address is within specified address area
Data enable for SRAM on pins D24 to D31
P90
TXD0
I2SCKO 1 I/O
Output
Output
Port90: I/O port
Serial 0 send data: Open-drain output programmable
I2S clock output
P91
RXD0
I2SDO 1 I/O
Input
Output
Port91: I/O port (Schmitt-input)
Serial 0 receive data
I2S data output
P92
SCLK0
0CTS
I2SWS
1
I/O
I/O
Input
Output
Port92: I/O port (Schmitt-input)
Serial 0 clock I/O
Serial 0 data send enable (Clear to send)
I2S word select output
P93
LGOE0 1 I/O Output Port93: I/O port Output enable-0 for external TFT-LCD driver
P94
LGOE1 1 I/O Output Port94: I/O port Output enable-1 for external TFT-LCD driver
P95
CLK32KO
LGOE2 1 Output
Output
Output
Port95: Output port
Output fs (32.768 kHz) clock
Output enable-2 for external TFT-LCD driver
P96
INT4
PX
1 Input
Input
Output
Port 96: Input port (Schmitt-input)
Interrupt request pin4: Interrupt request with programmable rising/falling edge
X-Plus: Pin connectted to X+for touch screen panel
P97
INT5
PY
1 Input
Input
Output
Port 97: Input port (Schmitt-input)
Interrupt request pin5: Interrupt request with programmable rising/falling edge
Y-Plus: Pin connectted to Y+for touch screen panel
PA0 to PA2
KI0 to KI2 3 Input Input Port: A0 to A2 port: Pin used to input ports (Schmitt input, with pull-up resistor) Key input 0 to 2: Pin used for key-on wakeup 0 to 2
PA3 to PA6
KI3 to KI6
LD8 to LD11 4 Input
Input
Output
Port: A3 to A6 port: Pin used to input ports (Schmitt input, with pull-up resistor)
Key input 3 to 6: Pin used for key-on wakeup 3 to 6
Data bus 8 to 11for LCD driver
PA7
KI7 1 Input Input Port: A7 port: Pin used to input ports (Schmitt input, with pull-up resistor) Key input 7: Pin used for key-on wakeup 7

TMP92CH21
2009-06-19
92CH21-9
Table 2.3.3 Pin Names and Functions (3/5)
Pin Name Number of
Pins I/O Function
PC0
INT0
TA1OUT 1 I/O
Input
Output
Port C0: I/O port (Schmitt-input)
Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge
8-bit timer 1 output: Timer 1 output
PC1
INT1
TA3OUT 1 I/O
Input
Output
Port C1: I/O port (Schmitt-input)
Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge
8-bit timer 3 output: Timer 3 output
PC2
INT2
TB0OUT0 1 I/O
Input
Output
Port C2: I/O port (Schmitt-input)
Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge
Timer B0 output
PC3
INT3 1 I/O Input Port C3: I/O port (Schmitt-input) Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge
PC6
KO8
LDIV 1 I/O
Output
Output
Port C6: I/O port
Key Output 8: Pin used of key-scan strobe (Open-drain output programmable)
Data invert enable for external TFT-LCD driver
PC7
CSZF
LCP1 1 I/O
Output
Output
Port C7: I/O port
Expand chip select: ZF: Outputs “0” when address is within specified address area
Shift-clock-1 for external TFT-LCD driver
PF0
TXD0
TXD1 1 I/O
Output
Output
Port F0: I/O port (Schmitt-input)
Serial 0 send data: Open-drain output programmable
Serial 1 send data: Open-drain output programmable
PF1
RXD0
RXD1 1 I/O
Input
Input
Port F1: I/O port (Schmitt-input)
Serial 0 receive data
Serial 1 receive data
PF2
SCLK0
0CTS
SCLK1
1CTS
1
I/O
I/O
Input
I/O
Input
Port F2: I/O port (Schmitt-input)
Serial 0 clock I/O
Serial 0 data send enable (Clear to send)
Serial 1 clock I/O
Serial 1 data send enable (Clear to send)
PF7
SDCLK 1 Output Output Port F7: Output port Clock for SDRAM (When SDRAM is not used, SDCLK can be used as system clock)
PG0 to PG1
AN0 to AN1 2 Input Input Port G0 to G1 port: Pin used to input ports Analog input 0 to 1: Pin used to Input to AD conveter
PG2
AN2
MX 1 Input
Input
Output
Port G2 port: Pin used to input ports
Analog input 2: Pin used to Input to AD conveter
X-Minus: Pin connectted to X−for touch screen panel
PG3
AN3
MY
ADTRG
1
Input
Input
Output
Intput
Port G3 port: Pin used to input ports
Analog input 3: Pin used to input to AD conveter
Y-Minus: Pin connectted to Y−for touch screen panel
AD trigger: Signal used to request AD start

TMP92CH21
2009-06-19
92CH21-10
Table 2.3.4 Pin Names and Functions (4/5)
Pin Name Number of
Pins I/O Function
PJ0
SDRAS
SRLLB 1 Output
Output
Output
Port J0: Output port
Row address strobe for SDRAM
Data enable for SRAM on pins D0 to D7
PJ1
SDCAS
SRLUB 1 Output
Output
Output
Port J1: Output port
Column address strobe for SDRAM
Data enable for SRAM on pins D8 to D15
PJ2
SDWE
SRWR 1 Output
Output
Output
Port J2: Output port
Write enable for SDRAM
Write for SRAM: Strobe signal for writing data
PJ3
SDLLDQM 1 Output Output Port J3: Output port Data enable for SDRAM on pins D0 to D7
PJ4
SDLUDQM 1 Output Output Port J4: Output port Data enable for SDRAM on pins D8 to D15
PJ5
SDULDQM
NDALE 1 I/O
Output
Output
Port J5: I/O port
Data enable for SDRAM on pins D16 to D23
Address latch enable for NAND flash
PJ6
SDUUDQM
NDCLE 1 I/O
Output
Output
Port J6: I/O port
Data enable for SDRAM on pins D24 to D31
Command latch enable for NAND flash
PJ7
SDCKE 1 Output Output Port J7: Output port Clock enable for SDRAM
PK0
LCP0 1 Output Output Port K0: Output port LCD driver output pin
PK1
LLP 1 Output Output Port K1: Output port LCD driver output pin
PK2
LFR 1 Output Output Port K2: Output port LCD driver output pin
PK3
LBCD 1 Output Output Port K3: Output port LCD driver output pin
PL0 to PL3
LD0 to LD3 4 Output Output Port L0 to L3: Output port Data bus for LCD driver
PL4 to PL7
LD4 to LD7 4 I/O Output Port L4 to L7: I/O port Data bus for LCD driver
TEST 1 Input Connect to VCC.
PM1
MLDALM 1 Output Output Port M1: Output port Melody/alarm output pin
PM2
ALARM
MLDALM 1 Output
Output
Output
Port M2: Output port
RTC alarm output pin
Melody/alarm output pin (inverted)
Note: The output functions SDULDQM, NDALE of PJ5-pin and SDUUDQM, NDCLE of PJ6-pin cannot be
used simultaneously. Therefore, 32-bit SDRAM and NAND-Flash cannot be used at the same time.

TMP92CH21
2009-06-19
92CH21-11
Table 2.3.5 Pin Names and Functions (5/5)
Pin Name Number of
Pins I/O Function
D+, D−2 I/O
USB-data connecting pin
Connect pull-up resistor to both pins to avoid through current when USB is not in use.
AM0, AM1 2 Input
Operation mode:
Fix to AM1 =“0”, AM0 =“1” for 16-bit external bus starting
Fix to AM1 =“1”, AM0 =“0” for 32-bit external bus starting
Fix to AM1 =“1”, AM0 =“1” for BOOT (32-bit internal MROM) starting
X1/X2 2 I/O High-frequency oscillator connection pins
XT1/XT2 2 I/O Low-frequency oscillator connection pins
RESET 1 Input Reset: Initializes TMP92CH21 (with pull-up resistor, Schmitt input)
VREFH 1 Input Pin for reference voltage input to AD converter (H)
VREFL 1 Input Pin for reference voltage input to AD converter (L)
AVCC 1 − Power supply pin for AD converter
AVSS 1 − GND pin for AD converter (0 V)
DVCC 4 − Power supply pins (All VCC pins should be connected to the power supply pin)
DVSS 3 − GND pins (0 V) (All pins should be connected to GND (0 V))
Note: Use a 9.0 MHz oscillator at pins X1/X2 when USB is used.

TMP92CH21
2009-06-19
92CH21-12
3. Operation
This section describes the basic components, functions and operation of the TMP92CH21.
3.1 CPU
The TMP92CH21 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU)
3.1.1 CPU Outline
The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the
TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to
process instructions more quickly.
The following is an outline of the CPU:
Table 3.1.1 TMP92CH21 Outline
Parameter TMP92CH21
Width of CPU address bus 24 bits
Width of CPU data bus 32 bits
Internal operating frequency Max 20 MHz
Minimum bus cycle 1-clock access (50 ns at fSYS =20MHz)
Internal RAM 32-bit 1-clock access
Internal boot ROM 32-bit 2-clock access
Internal I/O 8- or 16-bit 2-clock access or
8- or 16-bit 5 to 6-clock access
External SRAM, Masked ROM 8- or 16- or 32-bit 2-clock access
(waits can be inserted)
External SDRAM 16- or 32-bit min. 1-clock access
External NAND flash 8-bit min. 4-clock access
(waits can be inserted)
Minimum instruction
execution cycle 1-clock (50 ns at fSYS =20MHz)
Conditional jump 2-clock (100 ns at fSYS =20MHz)
Instruction queue buffer 12 bytes
Instruction set Compatible with TLCS-900/L1
(LDX instruction is deleted)
CPU mode Maximum mode only
Micro DMA 8 channels

TMP92CH21
2009-06-19
92CH21-13
3.1.2 Reset Operation
When resetting the TMP92CH21, ensure that the power supply voltage is within the
operating voltage range, and that the internal high-frequency oscillator has stabilized.
Then hold the RESET input low for at least 20 system clocks (16 µs at fc = 40 MHz).
At reset, since the clock doubler (PLL) is bypassed and the clock-gear is set to 1/16, the
system clock operates at 1.25 MHz (fc = 40 MHz).
When the reset has been accepted, the CPU performs the following:
•Sets the program counter (PC) as follows in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
PC<7:0> ←data in location FFFF00H
PC<15:8> ←data in location FFFF01H
PC<23:16> ←data in location FFFF02H
•Sets the stack pointer (XSP) to 00000000H.
•Sets bits <IFF2:0> of the status register (SR) to 111 (thereby setting the interrupt
level mask register to level 7).
•Clears bits <RFP1:0> of the status register to 00 (there by selecting register bank
0).
When the reset is released, the CPU starts executing instructions according to the
program counter settings. CPU internal registers not mentioned above do not change when
the reset is released.
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
•Initializes the internal I/O registers as shown in the “Special Function Register”
table in section 5.
•Sets the port pins, including the pins that also act as internal I/O, to
general-purpose input or output port mode.
Internal reset is released as soon as external reset is released.
Memory controller operation cannot be ensured until the power supply becomes stable
after power-on reset. External RAM data provided before turning on the TMP92CH21 may
be corrupted because the control signals are unstable until the power supply becomes
stable after power on reset.
Figure 3.1.1 Power on Reset Timing Example
High-frequency oscillation stabilized time
+20 system clock 0 s (Min)
VCC (3.3 V)
RESET

TMP92CH21
2009-06-19
92CH21-14
Figure 3.1.2 TMP92CH21 Reset Timing Chart
Read Write
fsys
A23∼A0
DATA-IN
D0∼D31 D0∼D31
((After reset released, starting 1 wait read cycle)
Sampling
RESET
RD WRxx SRWR
0FFFF00H
DATA-IN
DATA-OUT
CS0,1, 3
CS2
SRxxB SRxxB
fsys×(13.5~14.5) clock
Pull up (Internal) High-Z
(Input mode)
PA0~PA7
(Output mode)
PF7
PJ3~PJ4, PJ7
PM1~PM2
(Input mode)
P71~P72, P75~P76, P90~P94, P96~P97,
PC0~PC3, PC6~PC7,
PF0~PF1, PG0~PG3,
PJ5~PJ6, PL4~PL7,
(Output mode)
P40~P47,P50~P57
P74~P72, PK0~PK3,
PL0~PL3
Note: This chart shows timing for a reset using a
32-bit external bus (AM1:0=10).

TMP92CH21
2009-06-19
92CH21-15
3.1.3 Setting of AM0 and AM1
Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage.
Table 3.1.2 Operation Mode Setup Table
Mode Setup Input Pin
Operation Mode RESET AM1 AM0
16-bit external bus starting
(MULTI 16 mode) 0 1
32-bit external bus starting
(MULTI 32 mode) 1 0
Boot (32-bit internal MROM) starting
(BOOT mode)
1 1

TMP92CH21
2009-06-19
92CH21-16
3.2 Memory Map
Figure 3.2.1 is a memory map of the TMP92CH21.
Figure 3.2.1 Memory Map
Note 1: Boot program (Internal MROM) is mapped only for BOOT mode. For other starting modes, its area (3FE000H to 3FFFFFH)
is mapped to external-memory.
Note 2: The Provisional emulator control area, mapped F00000H to F0FFFFH after reset, is for emulator use and so is not available.
When emulator WR signal and RD signal are asserted, this area is accessed. Ensure external memory is used.
Note 3: Do not use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved for an emulator.
External memory
External memory
Vector table (256 bytes)
Internal I/O
(8 Kbytes)
Internal RAM
(16 Kbytes)
Direct area (n)
64-Kbyte area
(nn)
16-Mbyte area
(R)
(−R)
(R+)
(R +R8/16)
(R +d8/16)
(nnn)
000000H
000100H
001D00H
002000H
006000H
F00000H
F10000H
FFFF00H
FFFFFFH
(
=
Internal area)
Boot (Internal MROM)
(8 Kbytes)
Provisional emulator control
(64 Kbytes)
010000H
3FE000H
400000H
(Note 2)
(Note 1)
(Note 3)

TMP92CH21
2009-06-19
92CH21-17
3.3 Clock Function and Stand-by Function
The TMP92CH21 contains (1) clock gear, (2) clock doubler (PLL), (3) stand-by controller and
(4) noise reduction circuits. They are used for low power, low noise systems.
This chapter is organized as follows:
3.3.1 Block diagram of system clock
3.3.2 SFR
3.3.3 System clock controller
3.3.4 Clock doubler (PLL)
3.3.5 Noise reduction circuits
3.3.6 Stand-by controller

TMP92CH21
2009-06-19
92CH21-18
The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual
clock mode (X1, X2, XT1 and XT2 pins) and (c) triple clock mode (X1, X2, XT1 and XT2 pins and
PLL).
Figure 3.3.1 shows a transition figure.
Reset
(fOSCH/32)
Release reset
Instruction
Interrupt STOP mode
(Stops all circuits)
NORMAL mode
(fOSCH/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
(a) Single clock mode transition figure
(b) Dual clock mode transition figure
SLOW mode
(fs/2)
Reset
(fOSCH/32)
Release reset
NORMAL mode
(fOSCH/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
Instruction
Instruction
Interrupt
Interrupt
Instruction
Instruction
Interrupt
Interrupt
Instruction
Instruction
Interrupt
Interrupt
Instruction
Interrupt STOP mode
(Stops all circuits)
Instruction
Interrupt STOP mode
(Stops all circuits)
Using PLL
Note
Reset
(fOSCH/32)
Release reset
NORMAL mode
(fOSCH/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
STOP mode
(Stops all circuits)
SLOW mode
(fs/2)
NORMAL mode
(4 ×fOSCH/gear
value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate oscillator and PLL)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
(c) Triple clock mode transition figure
Instruction
Instruction
Interrupt
Interrupt
Instruction Instruction
Instruction Interrupt
Note
Instruction
Instruction Interrupt
Instruction
Instruction
Interrupt
Interrupt
Interrupt
Interrupt
Instruction
Instruction
Instruction Interrupt
Note 1: It is not possible to control PLL in SLOW mode when shifting from SLOW mode to NORMAL mode with use of PLL.
(PLL start up/stop/change write to PLLCR0<PLLON>, PLLCR1<FCSEL> register)
Note 2: When shifting from NORMAL mode with use of PLL to NORMAL mode, execute the following setting in the same order.
1) Change CPU clock (PLLCR0<FCSEL> ←“0”)
2) Stop PLL circuit (PLLCR1<PLLON> ←“0”)
Note 3: It is not possible to shift from NORMAL mode with use of PLL to STOP mode directly.
NORMAL mode should be set once before shifting to STOP mode. (Sstop the high-frequency oscillator after stopping
PLL.)
Figure 3.3.1 System Clock Block Diagram
The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called
fs. The clock frequency selected by SYSCR1<SYSCK> is called the clock fFPH. The system clock fSYS is defined as the divided
clock of fFPH, and one cycle of fSYS is defined as one state.