Toshiba TXZ SERIES User manual

TXZ Family
Ocsillation Frequency Detector
2018-03-09 1 / 20 Rev. 1.1
© 2017-2018
Toshiba Electronic Devices & Storage Corporation
2018-03
32bit RISC Microcontroller
TXZ Family
Reference manual
Oscillation Frequency Detector
(OFD-A)
Revision 1.1

TXZ Family
Ocsillation Frequency Detector
2018-03-09 2 / 20 Rev. 1.1
Contents
Preface .............................................................................................................................................................. 4
Related document ..................................................................................................................................................... 4
Conventions .............................................................................................................................................................. 5
Terms and Abbreviations .......................................................................................................................................... 7
1. Outlines ...................................................................................................................................................... 8
2. Configuration .............................................................................................................................................. 9
3. Function and Operation ............................................................................................................................ 10
3.1. Setting method ................................................................................................................................................. 10
3.2. Detection Frequency ........................................................................................................................................ 11
3.3. Detection start timing ....................................................................................................................................... 12
3.4. Detection .......................................................................................................................................................... 12
3.5. Available operation Mode of MCU ................................................................................................................... 13
3.6. External high speed oscillation clock detection ............................................................................................... 13
4. Registers .................................................................................................................................................. 14
4.1. List of Registers ............................................................................................................................................... 14
4.2. [OFDCR1] (Frequency Detection Control Register 1) ..................................................................................... 15
4.3. [OFDMON] (Detection Target Clock 1 Monitor Setting Register) .................................................................... 15
4.4. [OFDMN0] (Minimum Detection Frequency Setting Register 0 (EHOSC)) ..................................................... 15
4.5. [OFDMN1] (Minimum Detection Frequency Setting Register 1 (fc)) ............................................................... 15
4.6. [OFDMX0] (Maximum Detection Frequency Setting Register 0 (EHOSC)) .................................................... 16
4.7. [OFDMX1] (Maximum Detection Frequency Setting Register 1 (fc)) ............................................................... 16
4.8. [OFDRST] (Reset Control Register) ................................................................................................................ 16
4.9. [OFDCR2] (Frequency Detection Control Register 2) ..................................................................................... 16
4.10. [OFDSTAT] (Status Register) ........................................................................................................................ 17
5. Usage Example ........................................................................................................................................ 18
6. Revision History ....................................................................................................................................... 19
RESTRICTIONS ON PRODUCT USE ............................................................................................................ 20

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Ocsillation Frequency Detector
2018-03-09 3 / 20 Rev. 1.1
List of Figures
Figure 2.1 Oscillation Frequency Detector Block diagram ....................................................................... 9
Figure 3.1 Example of detection frequency range (in case of 10MHz) .................................................. 11
Figure 5.1 Example of operational procedure ........................................................................................ 18
List of Tables
Table 2.1 List of signals ........................................................................................................................... 9
Table 3.1 Clock examples ..................................................................................................................... 12
Table 6.1 Revision History ..................................................................................................................... 19

TXZ Family
Ocsillation Frequency Detector
2018-03-09 4 / 20 Rev. 1.1
Preface
Related document
Document name
Clock Control and Operation Mode
Exception
Power Supply and Reset Operation
Product Information

TXZ Family
Ocsillation Frequency Detector
2018-03-09 5 / 20 Rev. 1.1
Conventions
● Numeric formats follow the rules as shown below:
Hexadecimal: 0xABC
Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers.
Binary: 0b111 – It is possible to omit the “0b” when the number of bit can be distinctly
understood from a sentence.
● “_N” is added to the end of signal names to indicate low active signals.
● It is called “assert” that a signal moves to its active level, “deassert” to its inactive level.
● When two or more signal names are referred, they are described like as [m: n].
Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.
● The characters surrounded by [ ] defines the register.
Example: [ABCD]
● “n” substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], [XYZ3]-> [XYZn]
● "x" substitutes suffix number or character of two or more same kind of units and channels in same register
name in the Register List.
In case of unit, “x” means A, B, and C ..
Example: [ADACR0], [ADBCR0], [ADCCR0]->[ADxCR0]
In case of channel, “x” means 0, 1, and 2..
Example: [T32A0RUNA], [T32A1RUNA], [T32A2RUNA]->[T32AxRUNA]
● The bit range of a register is written like as [m: n].
Example: Bit[3: 0] expresses the range of bit 3 to 0.
● The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD].EFG = 0x01 (hexadecimal), [XYZn].VW = 1 (binary)
● Word and Byte represent the following bit length.
Byte: 8 bits
Half word: 16 bits
Word: 32 bits
Double word: 64 bits
● Properties of each bit in a register are expressed as follows:
R: Read only
W: Write only
R/W: Read and Write are possible
● Unless otherwise specified, register access supports only word access.
● The register defined as reserved must not be rewritten. Moreover, do not use the read value.
● The value read from the bit having default value of "-" is unknown.
● When a register containing both of writable bits and read-only bits is written, read-only bits should be
written with their default value, In the cases that default is “-“, follow the definition of each register.
● Reserved bits of the Write-only register should be written with their default value. In the cases that default is
“-“, follow the definition of each register.
● Do not use read-modified-write processing to the register of a definition which is different by writing and
read out.

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Ocsillation Frequency Detector
2018-03-09 6 / 20 Rev. 1.1
The Flash memory uses the Super Flash® technology under the license of Silicon Storage Technology, Inc.
Super Flash® is registered trademark of Silicon Storage Technology, Inc.
All other company names, product names, and service names mentioned herein may be trademarks of their respective
companies.
***********************************************************************************************************************
Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
***********************************************************************************************************************

TXZ Family
Ocsillation Frequency Detector
2018-03-09 7 / 20 Rev. 1.1
Terms and Abbreviations
Some of abbreviations used in this document are as follows:
OFD Oscillation Frequency Detector
EHOSC External High Speed Oscillator
IHOSC2 Internal High Speed Oscillator 2

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Ocsillation Frequency Detector
2018-03-09 8 / 20 Rev. 1.1
1. Outlines
Oscillation Frequency Detector (OFD) detects abnormalities as the clock signal to monitor exceeding the range
of the set-up frequency. The lists of functions are as follows.
Function
Classification
Function Operation
Abnormal
detection of
the clock
frequency
Monitor clock
External high speed oscillator clock (fEHOSC)
or
High speed clock (fc)
Standard clock (Note) Internal high speed oscillator 2 clock (fIHOSC2)
Frequency detective
range The maximum, the minimum are settable.
State monitor
status register.
>operation / no operation
>abnormality / no abnormality
Reset output Prohibition/permission of a reset output are possible.
Protection Protection function Incorrect writing is prevented.
Note: When stopping the standard clock during OFD operation ([OFDRST]<OFDRSTEN>=1), OFD reset occurs.
(When stopping the standard clock before OFD operation, OFD reset does not occur.)

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Ocsillation Frequency Detector
2018-03-09 9 / 20 Rev. 1.1
2. Configuration
The block diagram of the frequency detection circuit is shown as follows:
Figure 2.1 Oscillation Frequency Detector Block diagram
Table 2.1 List of signals
No. Symbol Signal name I/O Related Reference Manual
1 fIHOSC2 Internal high speed oscillator 2 clock Input Clock Control and Operation Mode
2 fEHOSC External high speed oscillator clock Input Clock Control and Operation Mode
3 fc
Internal high speed oscillator
(The clock that the clock was chosen in
[CGOSCCR]<OSCSEL>and
[CGPLL0SEL] <PLL0SEL>.)
Input Clock Control and Operation Mode
4 OFDRSTOUT OFD reset Output Power Supply and Reset Operation
OFD
Oscillation Frequency Detection
Circuit
Switch
intend
detection
clock
Intend
detection
clock
Reference
clock
fc
OFDRSTOUT
fIHO SC2 fEHOSC
10
Fr equ en cy
Dete ction Con trol
Regist er 1
[OFDCR1]
Fr equ en cy
Dete ction Con trol
Regist er 2
[OFDCR2]
M in imu m
Dete ction
Fr equ en cy Se tting
Reg ist er 0
[OFDMN0]
M in imu m
Dete ction
Fr equ en cy Se tting
Reg ist er 1
[OFDMN1]
Maximum
Dete ction
Fr equ en cy Se tting
Regist er 0
[OFDMX0]
Maximum
Dete ction
Fr equ en cy Se tting
Regist er 1
[OFDMX1]
Dete ction Target
Clock 1 Mon it or
Se tting Reg ister
[OFDMON]Rese t Con trol
Reg ist er
[OFDRST]
St atu s Reg ist er
[OFDSTAT]
The frequency
detective reset
output

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Ocsillation Frequency Detector
2018-03-09 10 / 20 Rev. 1.1
3. Function and Operation
Oscillation Frequency Detector (OFD) is a function to detect the abnormality of the clock.
3.1. Setting method
When you use OFD, please set an applicable clock enable bit to “1” (clock supply) in fsys supply stop register
A ([CGFSYSENA], [CGFSYSMENA]), fsys supply stop register B ([CGFSYSENB],[CGFSYSMENB]), and fc
supply stop registers ([CGFCEN]). In addition, please set a standard clock (internal high speed oscillator
(IHOSC2) for OFD) for an oscillation.
The corresponding registers and the bit locations depend on a product. Some products do not have all registers.
For the details, refer to “Clock Control and Operation Mode” in Reference manual.
After the reset is deasserted, the registers other than [OFDCR1] cannot be written. The write is enabled by setting
0xF9 to [OFDCR1].
● When the measuring object is fEHOSC.
[OFDMON] is set as “0” and the measuring object is used as the external high speed oscillator clock
(fEHOSC). A lower limit level in the range of the frequency to detect is set by [OFDMN0] <OFDMN0>. An
upper limit level in the range of the frequency to detect is set by [OFDMX0] <OFDMX0>.
● When the measuring object is fc.
[OFDMON] is set as “1” and the measuring object is used as the high-speed clock (fc). A lower limit level
in the range of the frequency to detect is set by [OFDMN1] <OFDMN1>. An upper limit level in the range
of the frequency to detect is set by [OFDMX1] <OFDMX1>.
Permission/prohibition of reset generating is set up by [OFDRST]. The operation will be started if “0xE4” is
written in [OFDCR2].
In order to prevent erroneous write, please set “0x06” as [OFDCR1] after the setup of all the registers, and
forbid the writing. Moreover, after the operation has stopped, please make the change of the setup.