Toshiba TC9314F User manual

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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9314F
Single-Chip DTS Microcontroller (DTS-22)
TC9314F is a 4 bit CMOS microcontroller for single-chip digital
tuning systems with built-in prescaler, PLL and LCD driver.
The CPU has 4 bit parallel addition/subtraction (eg, AI and SI
instructions), logical operations (eg, OR and AN), several bit
judge and compare instructions (eg, TM and SL), and time base
functions.
The device is in an 80 pin mini flat package. It includes
abundant I/O ports controlled by powerful input and output
instructions (IN1-3, OUT1-3) exclusive key input ports, abundant
LCD output ports, interrupts, a BUZR port, 6 bit A/D and D/A
converters, serial interface, and IF counter.
With CMOS architecture for low power consumption, TC9314F
is ideal for providing digital tuning for multiband radios,
radio-cessatte players and other portable equipment.
Features
x 4 bit microcontroller for single-chip digital tuning systems
x Operating voltage VDD of 2.7~5.5 V, with CMOS architecture for low power consumption
x On-chip prescaler (fixed to 1/2 frequency division +2-modulus prescaler: fmax t130 MHz)
x 1/3-duty, 1/2-bias driven LCD driver, with on-chip 3 V constant-voltage display circuit
x Easy backup of data memory (RAM) and various ports
x Program ROM: 16 bits × 6144 steps
x Data memory (RAM): 4 bits × 384 words
x Powerful instruction set with 54 1-word instructions
x Instruction execution time of 40 µs (75 kHz crystal connected; 80 µs for MVGS and DAL instructions)
x 4 add and 4 subtract instructions
Note 1: This device is vulnerable to surge voltage. Take it into account when using this device in your system.
x Powerful compound judge instructions (TMTR, TMFR, TMT, TMF, TMTN and TMFN)
x Data transfer at the same row address (MVSR instruction)
x Register indirect transfer available (MVGD and MVGS instructions)
x 16 powerful general registers assigned in RAM
x Stack levels: 4
x No concepts of pages or fields in program ROM. Features 6144 steps that allow JUMP or CAL instructions at
any point.
x 16 bit contents of any address in 1024 steps of the program ROM can be referenced freely. (DAL instruction)
x Independent FMIN and AMIN pins for FM and AM frequency input and two phase comparison outputs (DO1
and DO2).
x Choice of seven reference frequencies by program
x Powerful input and output instructions (IN1~3 and OUT1~3)
x Input-only ports (K0~K3) for key inputs and 33 LCD drive pins (90 segments maximum).
x 26 I/O ports (16 ports specifiable in units of bits, 10 output-only ports). Three pins (IFIN1, IFIN2 and DO2) can
be switched using instructions for use as input-only ports IN1 and IN2, and output-only port OT2, respectively.
In addition LCD output pins S19~S30 can be switched to I/O ports in units of bits.
x 2 external interrupt input ports.
These are able to switch for use as general input ports by program.
Weight: 1.57 g (typ.)

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x Three backup modes can be implemented using instructions: CPU operation only, clock generation only or clock
stop.
x Features a built-in 2 Hz timer flip-flop and 10/100 Hz interval pulse output (internal time-based port)
x Detection of PLL locked state supported.
x 8 of the LCD segment outputs (S23~S30) can also be used as key return timing outputs (KR0~KR7), so that
output ports are not monopolized by key return outputs and are available for other uses.
x Built-in 20 bit general-purpose IF counter counts central frequencies for each band, providing station detection
during automatic tuning.
x Built-in 8 bit buzzer output circuit supports generation of 254-level tone signals.
x Built-in 2-channel, 6 bit A/D converter and 1-channel, 6 bit D/A converter.
x Low-voltage detection circuit stops the CPU when power supply voltage drops below 1.5 V to prevent
malfunction.
x OTP product: TC93P14F
Pin Assignment (top view)

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Block Diagram

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Pin Function
Pin No. Symbol Pin Name Function and Operation Remarks
1 COM1
2 COM2
3 COM3
LCD common
outputs
Common output pins for the LCD panel. Can
display up to 90 segments in a matrix with
S1-S30.
Three value levels, VLCD, 1/2 VLCD and GND, are
output at 2 ms intervals at an 83 Hz cycle.
After system reset or clock stop are released, 1/2
VLCD is output, setting the DISP OFF bit to 0 and
outputting the common signal.
4~21 S1~S18 LCD segments
outputs
22~25 S19/P5-0~
S22/P5-3
LCD segment
outputs/
I/O ports
26~33
S23/P6-0/
KR7~
S30/P7-3/
KR0
LCD segment
outputs/
I/O ports/key return
timing outputs
Segment signal output pins for the LCD panel.
Together with COM1, COM2 and COM3, a matrix
is formed that can display a maximum of 90
segments.
Pins S19~S30 can programmed as I/O ports.
The signals for the key matrix and the segment
signals from S23/KR7~S30/KR0 are output on a
time division basis. 4 u8 32 key matrix can be
configured with key input ports K0~K3.
34~37 K0~K3 Key input ports
4 bit port for key-matrix inputs. In combination with
key return timing outputs KR0~KR7for the LCD
segment pins, these ports support data input for
up to 4 u8 32 keys. Pull-down resistors are built
in.
A key matrix can also be configured using key
timing output ports T0~T7.
38~45 T0~T7 Key timing output
ports
Key matrix timing signal output ports. To configure
the key matrix, N-channel load resistors are built
in. When keys are connected, the matrix diodes
can be omitted.
46~53 P1-0~P2-3 I/O ports 1 and 2 8 bit I/O port. Input or output can be programmed
for each bit.

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Pin No. Symbol Pin Name Function and Operation Remarks
54~57
P3-0/DAOUT
P3-1/ADIN2
P3-2/ADIN1
P3-3/
DC-REF
I/O port 3
/D/A analog voltage
output
/A/D analog voltage
input
/A/D analog voltage
input
/reference voltage
input
4 bit I/O port.
Input or output can be programmed for each bit.
Pins P3-0 through P3-2 serve as the analog inputs
and outputs for the built-in A/D and D/A
converters.
The A/D converter operates by successive
comparison method based on software control.
Pins can be set to A/D, D/A analog input/output in
units of bits as necessary.
P3-3 can be set to reference voltage input.
Reference voltage can be set to the internal
supply voltage (VDD). It is also possible to input
VEED to the A/D analog input, enabling
measurement of battery voltage and the like.
The D/A converter outputs analog voltage through
the operating amplifier with shared the
comparison voltage generator circuit used by the
A/D converter. To share the reference voltage
generator circuit with the A/D converter, D/A
converter output is set to high impedance during
A/D conversion. It is necessary at such times to
connect an analog voltage hold capacitor to the
D/A output pin.
The A/D and D/A converters, as well as their
controls, are all programmable.
58~61
P4-0/SI
P4-1/SO
P4-2/ SCK
P4-3
I/O port 4
/serial data input
/serial data output
/serial clock
input/output
I/O port 4
4 bit I/O port.
Input or output can be programmed for each bit.
Pins P4-0 through P4-2 also serve as input/output
pins for the serial interface circuit (SIO).
SIO inputs 4 bit or 8 bit serial data at the clock
edge of the SCK pin; outputs data from the SO
pin.
The serial operating clock ( SCK ) allows selection
between internal and external, and between rising
and falling clock edge shift. The SO pin can be
switched to serial input (SI), facilitating control of a
variety of LSIs and communication between
controllers. All SIO inputs have built-in
Schmittcircuits.
All SIOs and their controls can be used or set by
program.
62 OT1/BUZR
General-purpose
output port
/buzzer output
1 bit output port that also serves as the built-in
buzzer circuit output. Buzzer buzzes in 254 levels
from 18.75 kHz to 147 Hz, with a duty factor of
50%.
Buzzer output control can be used or set by
program.
63 MUTE Muting output port
1 bit output port.
Normally used for output of the muting control
signal. It allows the internal MUTE bit to be set to
1 based on I/O port 1 input state. It can also
change MUTE bit output logic and output PLL
phase differences.
64
65
INTR1
INTR2
External interrupt
input
External interrupt input pins.
Can be used for remote control signal input or
tape travel detection input.
Can also be programmed as general-purpose
input ports.

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Pin No. Symbol Pin Name Function and Operation Remarks
66 TEST Test mode control
input
Input pin for controlling test mode.
When the pin is high, test mode; when low, normal
operation.
Normally used low or in the NC state. (pull-down
resistance built in)
67 HOLD Hold mode control
input
Input pin used to request/cancel a hold state.
Normally used for the radio mode select signal
input or for the battery detection signal input.
Hold states can be either clock stop mode (crystal
oscillation stopped) or wait mode (CPU stopped).
The mode is set by a CKSTP or WAIT instruction.
When CKSTP instruction is executed, the hold
state request/cancel differs depending on the
internal MODE bit. When the MODE bit is 0
(MODE-0), executing the CKSTP instruction while
the HOLD pin is low stops the clock generator
and the CPU, and enters memory backup state.
When the MODE bit is 1 (MODE-1), executing the
CKSTP instruction regardless of whether the
HOLD pin is high or low enters memory backup
state. This state is canceled in MODE-0 when the
HOLD pin changes to high; in MODE-1, when
the input at the HOLD pin changes.
When a WAIT instruction is executed, the state is
cancelled by changes in inputs at this pin.
During memory backup, current consumption is
reduced (to 1 PA or less) and all output pins
(display outputs, output ports, etc.) automatically
are set to low.
68
69
IFIN1/IN1
IFIN2/IN2
IF signal input
/input port
IF signal input pin for the IF counter; counts the IF
signals for the FM and AM bands and detects
autostop.
Input frequency is 0.3~12 MHz (0.2 Vp-p min). The
built-in input amplifier operates at small amplitude
withcapacitors connected.
The IF counter is a 20 bit counter with gate time
selectable to 1, 4, 16 or 64 ms, allowing 20 bits of
data to be loaded to memory directly.
This input pin can be programmed as an input port
(IN port).
When set to IN port, input is CMOS level.
70
71
DO1
DO2/OT2
Phase comparator
output
Phase comparator
output/output port
PLL phase comparator output pin.
Tri-state output. When the divider output of the
programmable counter is higher than the
reference frequency, high level is output; when
lower, low level is output. When they accord, the
output is at high impedance.
DO1 and DO2 are parallel outputs, allowing
optimized design of filter constants for both the
FM and AM bands.
The DO2 pin can also be set to high impedance or
as an output port (OT2) by program. Thus these
two pins can be used to improve lockup time, or to
provide effective use of pins as output ports.

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Pin No. Symbol Pin Name Function and Operation Remarks
75 VDD
72 GND
Power supply pins
Pin for applying the power supply.
Normally, a VDD of 2.7~5.5 V is applied during
PLL operation. When PLL is stopped, a VDD of
1.8~5.5 V is applied.
During backup (at execution of the CKSTP
instruction), voltage can be reduced to 1.2 V. If
voltage drops below 1.5 V with the CPU in
operation, the CPU is stopped to prevent CPU
malfunction (stop mode) and is restarted when the
voltage reaches 1.5 V.
The STOP F/F bit detects whether stop mode is in
effect or not, so that initialization or clock
modification may be programmed as desired.
To detect and control CPU malfunction using an
external circuit, stop mode operation can be
programmed invalid, at which time all 4 bits of the
internal test port are set to 1.
If a voltage of 0 V to 1.8 V or more is applied to
this pin, the system is reset and the program
starts from address 0 (power on reset).
Note: Due to the power on reset operation, use
the device with a supply voltage rise time of
between 10 ms and 100 ms.
73 FMIN FM broadcast signal
input
A programmable counter input pin for the FM
band.
Either the 1/2 pulse swallow method (FMH
mode) or the pulse swallow method (FMLmode)
can be selected by program.
In FM mode, a 50 to 130 MHz (0.3 Vp-p min)
locally oscillated output (VCO output) is input.
The built-in input amplifier operates at small
amplitude with capacitors connected.
Note: In PLL off mode and when AMIN input is
set, input is pulled down.
74 AMIN AM broadcast signal
input pin
A programmable counter input pin for the AM
band. Either the pulse swallow method (HF mode)
or the direct frequency division method can be
selected by program.
In HF mode, a 1 to 60 MHz (0.3 Vp-p min) locally
oscillated output (VCO output) is input; in LF
mode, 0.5 to 10 MHz (0.2 Vp-p min).
The built-in input amplifier operates at small
amplitude with capacitors connected.
Note: In PLL off mode and when FMIN input is
set, input is pulled down.
76 RESET Reset input
System reset signal input pin.
When a reset occurs while RESET is low, the
pin is set to high and the program starts from
address 0.
Normally, if a voltage of 0 V to 1.8 V or more is
supplied to VDD, the system is reset (power on
reset) so use this pin fixed to high.

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Pin No. Symbol Pin Name Function and Operation Remarks
77 XOUT
78 XIN
79 VXT
Crystal oscillator pin
Crystal oscillator pin.
A 75 kHz reference crystal oscillator is connected
to the XIN and XOUT pins.
Oscillation stops during execution of a CKSTP
instruction.
The VXT pin is the power supply for the crystal
oscillator. Connect a capacitor (0.47 PF typ.) for
stabilization.
80 VLCD 3 V constant-voltage
output pin
3 V constant-voltage output pin for driving the
LCDs.
Connect a capacitor (1.0 PF typ.) for stabilization.
Note 2: When a device is reset (VDD from 0 V to 1.8 V or more, or RESET from low to high), the I/O ports are set
to input; the LCD output and I/O port common pins are set to LCD output, the I/O ports and common pins
with additional functions (eg, SIO, A/D converter) are set to I/O port input pins; the IFIN pin is set to IF input.
Note 3: In PLL off mode (all 4 bits of the internal reference port are set to 1), IFIN and the FMIN and AMIN pins are
pulled down, and DO1 and DO2 are at high-impedance.
Note 4: In clock stop mode (during execution of the CKSTP instruction), output ports and LCD output pins are all set
to low. The constant-voltage circuit (VLCD) and clock generator power supply (VXT) are turned off.
Note 5: When a device is reset, the contents of output ports and internal ports are undefined. Therefore, initialize by
program as required.

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Explanation of Operation
CPU
CPU is composed of program counter, stack register, ALU, program memory, data memory, G-register, carry
F/F and judging circuit.
1. Program Counter (PC)
Program Counter is a block to designate the address of program memory (ROM), and is composed of 13
bits binary up counter. This is cleared by system reset, and the program starts from zero address.
Usually, it’s increment is made one by one everytime the one instruction is executed, but when JUMP
instruction or CAL instruction is executed, the address designated at operand part of that instruction is
loaded.
Further, when the instruction (SLT1, TMT, SKP, RNS instructions, etc.) having skip function is executed,
two increments of program counter is made if the result is the condition to be skipped, and the succeeding
instruction is skipped.
2. Stack Register (STACK)
This is a register composed of 4 u13 bits during the execution of subroutine call instruction, the value
obtained by adding 1 to the content of program counter, namely return address, is housed. The content of
stack register is loaded on the program counter by the execution of return instruction. (RN, RNS
instructions)
This stack level is 4 level, and nesting is 4 level.
3. ALU
ALU has binary 4 bits parallel addition and subtraction, logical operation, comparison and plural bit
judge functions.
This CPU has no accumulator, and all operations directly treat the contents of data memory.
4. Program Memory (ROM)
Program memory is composed of 16 bit u6144 steps and is the address of 0000H~17FFH.
Program memory has no concept of page or field, so JUMP instruction and CAL instruction can be freely
used among 6144 steps.
Further, it is possible to use optional address of program memory as data area, and its content, 16 bits,
can be loaded to the data register by executing DAL instruction.
Note 6: Provide the data area at the address outside the program loop in the program memory.
Note 7: In DAL instruction, the address of program memory can be designated as the data area becomes 1024
steps of 0000H~03FFH.

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5. Data Memory (RAM)
Data memory is composed of 4 bit u384 words and used for storing data.
This 384 words are expressed with row address (5 bits) and column address (4 bits).
320 words (row address 04H~17H) among the data memory are indirect addressing by G-register. For
this reason, when carrying out data processing within this territory, it is necessary to designate row
address by G-register beforehand Area of 000H~00FH address in data memory is called general register,
and can be used only by designating column address (4 bits). These 16 general registers can be used for
operation and transfer between data memories. Further, it can also be used as ordinary data memory.
Note 8: The column address (4 bits) to designate general register becomes register number of the general
register.
Note 9: It is also possible to indirectly designate all of row address ( 00H~17H) by G-register.
Note 10: 256 words (row address 00H~0FH) among the data memory are direct addressing by LD or ST
instructions.
Note 11: Indirect designation of row address (00H~17H) is also possible
6. G-Register (G-REG.)
G-register is a 5 bits register for addressing row address (DR 04H~17H) of 320 words in data memory.
Content of this register is effective during executing MVGD instruction, MVGS instruction, and is not
related with the execution of other instructions.
This register is treated as one of the port, and its content is set by the execution of OUT1 instruction
among input and output instructions.
(refer to register port item 1)
Content of this register can directly setting by the execution STIG instruction.

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7. Data Register (DATA REG.)
This is a register composed of 1 u16 bits. In this register, 16 bits data of optional address among the
program memory is loaded during executing of DAL instruction. This register is treated as one of the port,
and when KEY instruction among input and output instruction is executed, it’s content is read in the data
memory in 4 bits unit.
(refer to register port item 2)
8. Carry F/F (C㨯
㨯㨯
㨯F/F)
This is set when carry or borrow is produced as a result of executing operational instruction, and is reset
when it is not produced. Content of carry F/F changes only when addition and subtraction instruction is
executed, and does not change during the execution of other instructions.
9. Judge Circuit (J)
When a instruction with skip function is executed, this circuit judges it’s skip condition. When skip
condition is satisfied, this circuit makes two increments of program counter, and skips the succeeding
instruction.
It is provided with 15 kinds of instructions having abundant skip function.
(refer to Item 11, explanation list of function and operation of instructions, *marked instruction)
10. List of Instructions Set
54 kinds of instruction set are included, all of which consisting of one word instruction.
These instructions are expressed with 6 bits instruction code.
00 01 10 11
Higher Rank 2 Bits
Lower Rank 4 Bits 0 1 2 3
0000 0 AI M, I TMTR r, M SLTI M, I
0001 1 AIC M, I TMFR r, M SGEI M, I
0010 2 SI M, I SEQ r, M SEQI M, I
0011 3 SIB M, I SNE r, M SNEI M, I
0100 4 ORIM M, I TMTN M, N
0101 5 ANIM M, I TMT M, N
0110 6 XORIM M, I TMFN M, N
0111 7 MVIM M, I
LD r, M*
CALL ADDR1
TMF M, N
1000 8 AD r, M IN1 M, C
1001 9 AC r, M IN2 M, C
1010 A SU r, M IN3 M, C
1011 B SB r, M
ST M*, r
OUT1 C, M
1100 C ORR r, M CLT r, M OUT2 C, M
1101 D ANDR r, M CLTC r, M OUT3 C, M
1110 E XORR r, M MVGD r, M DAL ADDR2, r
SHRC M
RORC M
STIG I*
SKP, SKPN, RN, RNS
WAIT P
SKSTP
XCH M
1111 F MVSR M1, M2 MVGS M, r
JUMP ADDR1
NOOP

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11. Explanation List of Function and Operation of Instructions (explanation of symbols)
M: Data memory address
Normally, one of 000H~03FH address of data memory.
M*: Data memory address (256 word)
One of 000H~0FFH address of data memory (available at executing ST and LD instruction)
r: General register
One of 00H~0FH address of data memory.
PC: Program counter (13 bit)
STACK: Stack register (13 bit)
G: G-register (5 bit)
DATA: Data register (16 bit)
I: Immediate data (4 bit)
I*: Immediate data (5 bit)
N: Bit position (4 bit)
: All “0”
C: Code No. of port (4 bit)
CN: Lower rank 3 bit of port code No. (4 bit)
RN: General register No. (4 bit)
ADDR1: Program memory address in page 0 or 1 (13 bit)
ADDR2: Higher rank 6 bit of program memory address in page 0
Ca: Carry
b: Borrow
IN1~IN3: Port treated during the execution IN1~IN3 instruction
OUT1~OUT3: Port treated during the execution OUT1~OUT3 instruction
( ): Register or data memory content
[ ]
C: Content of port indicated by code No. C (4 bit)
[ ]: Content of data memory indicated by the content of register or data memory
[ ]
P: Content of program memory (16 bit)
IC: Instruction code (6 bit)
*: Instruction having skip function
DC: Data memory column address (4 bit)
DR: Data memory row address (2 bit)
DR*: Data memory row address (4 bit) (available at executing ST and LD instruction)
(M) b0~(M) b3: Bit data for content of data memory

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Machine Language (16 bit)
Inst. Gr.
Mnemonic
Skip
Function
Explanation of Function Explanation of Operation IC
(6 bit)
A
(2 bit)
B
(4 bit)
C
(4 bit)
AI M, I
Add immediate data to
memory M m(M) I 000000 DRD
CI
AIC M, I
Add immediate data to
memory with carry M m(M) I ca 000001 DRD
CI
AD r, M
Add memory to general
register r m(r) (M) 001000 DRD
CR N
ADDITION
INSTRUCTION
AC r, M
Add memory to general
register with carry r m(r) (M) ca 001001 DRD
CR N
SI M, I
Subtract immediate data
from memory M m(M) I 000010 DRD
CI
SIB M, I
Subtract immdediate data
from memory with borrow M m(M) I b 000011 DRD
CI
SU r, M
Subtract memory form
general register r m(r) (M) 001010 DRD
CR N
SUBTRACTION
INSTRUCTION
SB r, M
Subtract memory form
general register with
borrow
r m(r) (M) b 001011 DRD
CR N
SLTI M, I *Skip if memory is less
than immediate data Skip if (M) I 110000 DRD
CI
SGEI M, I *
Skip if memory is greater
than or equal to
immediate data
Skip if (M)
!

I 110001 DRD
CI
SEQI M, I *Skip if memory is equal to
immediate data Skip if (M) I 110010 DRD
CI
SNEI M, I *Skip if memory is not
equal to immediate data Skip if (M) zI 110011 DRD
CI
SEQ r, M *Skip if general register is
equal to memory Skip if (r) (M) 010010 DRD
CR N
SNE r, M *Skip if general register is
not equal to memory Skip if (r) z(M) 010011 DRD
CR N
CLT r, M
Set carry flag if general
register is less than
memory, or reset if not
(CY) m1 if (r) (M) or
(CY) m0 if (r)
!

(M) 011100 DRD
CR N
COMPARISON INSTRUCTION
CLTC r, M
Set carry flag if general
register is less than
memory with carry or
reset if not
(CY) m1 if (r) (M) 
(Ca) or
(CY) m0 if (r)
!

(M) 
(Ca)
011101 DRD
CR N

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Machine Language (16 bit)
Inst. Gr.
Mnemonic
Skip
Function
Explanation of Function Explanation of Operation IC
(6 bit)
A
(2 bit)
B
(4 bit)
C
(4 bit)
LD r, M*
Load memory to general
register r m(M*) 0101
DR*
(4 bit) DCR
N
ST M*, r Store general register to
memory M*m(r) 0110 DR*
(4 bit) DCR
N
MVSR M1, M2Move memory to memory
in the same row (DR, DC1) m(DR, DC2) 001111 DRD
C1 DC2
MVIM M, I
Move immediate data to
memory M mI 000111 DRD
CI
MVGD r, M
Move memory to
destination memory
referring to G-register
and general register
[(G), (r)] m(M) 011110 DRD
CR N
MVGS M, r
Move source memory
referring to G-register
and general register to
memory
M m[(G), (r)] 011111 DRD
CR N
TRANSFER INSTRUCTION
STIG I*
Move immediate data to
G-register G mI*111111 0
I*
(5 bit) 0010
IN1 M, C
Input IN1 port data to
memory M m[IN1] C111000 DRD
CC N
OUT1 C, M
Output contents of
memory to OUT1 port [OUT1] Cm(M) 111011 DRD
CC N
IN2 M, C
Input IN2 port data to
memory M m[IN2] C111001 DRD
CC N
OUT2 C, M
Output contents of
memory to OUT2 port [OUT2] Cm(M) 111100 DRD
CC N
IN3 M, C
Input IN3 port data to
memory M m[IN3] C111010 DRD
CC N
INPUT AND OUTPUT INSTRUCTION
OUT3 C, M
Output contents of
memory to OUT3 port [OUT3] Cm(M) 111101 DRD
CC N
ORR r, M
Logical OR of general
register and memory r m(r) (M) 001100 DRD
CR N
ANDR r, M
Logical AND of general
register and memory r m(r) (M) 001101 DRD
CR N
ORIM M, I
Logical OR of memory
and immediate data M m(M) I 000100 DRD
CI
ANIM M, I
Logical AND of memory
and immediate data M m(M) I 000101 DRD
CI
XORIM M, I
Logical exclusive OR of
memory and immediate
data
M m(M) I 000110 DRD
CI
LOGICAL OPERATION INSTRUCTION
XORR r, M
Logical exclusive OR of
general register and
memory
r m(r) (M) 001110 DRD
CR N

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Machine Language (16 bit)
Inst. Gr.
Mnemonic
Skip
Function
Explanation of Function Explanation of Operation IC
(6 bit)
A
(2 bit)
B
(4 bit)
C
(4 bit)
TMTR r, M *
Test general register bits
by memory bits, then skip
if all bits specified are
true
Skip if r [N (M)] all “1” 010000 DRD
CR N
TMFR r, M *
Test general register bits
by memory bits, then skip
if all bits specified are
false
Skip if r [N (M)] all “0” 010001 DRD
CR N
TMT M, N *
Test memory bits, then
skip if all bits specified
are true
Skip if M (N) all “1” 110101 DRD
CN
TMF M, N *
Test memory bits, then
skip if all bits specified
are false
Skip if M (N) all “0” 110111 DRD
CN
TMTN M, N *
Test memory bits, then
not skip if all bits
specified are true
Skip if M (N) not all “1” 110100 DRD
CN
TMFN M, N *
Test memory bits, then
not skip if all bits
specified are false
Skip if M (N) not all “0” 110110 DRD
CN
SKP *Skip if carry flag is set Skip if (CY) 1 111111 00  0011
BIT JUDGE INSTRUCTION
SKPN *Skip if carry flag is reset Skip if (CY) 0 111111 01  0011
CALL ADDR1Call subroutine STACK m(PC) 1 and
PC mADDR1100 ADDR1(13 bit)
RN Return to main routine PC m(STACK) 111111 10  0011
SUBROUTINE
INSTRUCTION
RNS *Return to main routine
and skip unconditionally PC m(STACK) and skip 111111 11  0011
JUMP
INST.
JUMP ADDR1Jump to the address
specified PC mADDR1101 ADDR1(13 bit)
SHRC M
Shift memory bits to right
direction with carry
0 o(M) b3 o(M) b2 o
(M) b1 o(M) b0 o(CY) 111111 DRD
C0000
RORC M
Rotate memory bits to
right direction with carry
(M) b3 o(M) b2 o
(M) b1 o(M) b0 o
(CY)
111111 DRD
C0001
XCH M
Exchange memory bits
mutually
(M) b3 l(M) b0,
(M) b2 l(M) b1 111111 DRD
C0110
DAL ADDR2, r Load program memory in
page 0 to DATA register
DATA m[ADDR2(r)] P
in page 0 111110 ADDR2(6 bit) RN
At P “0” H, the condition
is CPU waiting (Soft wait
mode)
WAIT P
At P “1” H, except for
clock generator, all
function is waiting (Hard
wait mode)
Wait at condition P 111111 P  0100
CKSTP Clock generator stop
Stop clock generator
according to MODE
condition
111111   0101
OTHER INSTRUCTION
NOOP No operation  111111   1111
Note 12: Among 10 bits of the program memory address assigned by DAL instruction, the lower rank of 4 bits
become indirect addressing based on the content of general register.
DAL instruction executing time is 80 Ps. (2 machine cycles)
Note 13: MVGS instruction executing time is 80 Ps. (2 machine cycles)

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I/O Map
All the ports in the device are accessed by the six input/output instructions (OUT1~OUT3 and IN1~IN3)
using the 4 bit code number matrices.
The I/O map on the following page shows the port allocation. Horizontally, the I/O map shows the ports
manipulated by each input/output instruction. Vertically, the map shows the ports corresponding to each port
code number. The G register and the data register are also treated as ports.
Use the OUT1~OUT3 instructions for output ports and the INT1~INT3 instructions for input ports.
Note 14: The diagonal lines in the I/O map indicate non-existent ports. Executing an instruction to output data to a
non-existent output port has no effect on other ports or on data memory contents. Executing an input
instruction for a non-existent input port reads all “1” into data memory.
Note 15: Output ports indicated by an asterisk (*) in the I/O map are unused ports. Data output to these ports are
“don’t care”.
Note 16: The contents of the ports are represented by four bits where Y1 corresponds to the least significant bit of the
data in data memory, and Y8 to the most significant bit.
The ports specified by the six input/output instructions and by code No.C are represented in this document by
the following notation.
(example) The G register is set by the OUT1 instruction with codes “D” and “E”. Therefore, the notation is
“IL1D” and “IL1E”.

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I/O Map
IL1 IL2 IL3 IK1 IK2 IK3
OUT1 OUT2 OUT3 IN1 IN2 IN3
I/O
Code Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
IF offset DA/AD control I/O port 1 IF control I/O port 1
0 HF
1 1
FM
DCREF ON AD1 ON AD2 ON DA ON 0 1 2 3 BUSY MANUAL OVER
1
0 1 2 3
Programmable counter DA REF data 1 I/O port 2 IF data I/O port 2
1
P0 P1 P2 P3 AR0 AR1 AR2 AR3 0 1 2 3 F0 F1 F2 F3
0 1 2 3
Programmable counter DA REF data 2 I/O port 3 IF data I/O port 3
2
P4 P5 P6 P7 AR4 AR5 SEL0 SEL1 0 1 2 3 F4 F5 F6 F7
AD OUT 1 1 1
0 1 2 3
Programmable counter SIO control 1 I/O port 4 IF data I/O port 4
3
P8 P9 P10 P11 edge INV-SCK OI/-SCK SIO-ON 0 1 2 3 F8 F9 F10 F11
0 1 2 3
Programmable counter SIO control 2 I/O port 5 IF data SIO control I/O port 5
4
P12 P13 P14 P15 STA OI/-SO bit48/ *0 1 2 3 F12 F13 F14 F15 BUSY COUNT SIO F/F
1
0 1 2 3
Reference selection SIO output data 1 I/O port 6 IF data SIO input data 1 I/O port 6
5
R0 R1 R2 R3 SO0 SO1 SO2 SO3 0 1 2 3 F16 F17 F18 F19 SI0 SI1 SI2 SI3 0 1 2 3
I/F counter control SIO output data 2 I/O port 7 SIO input data 2 I/O port 7
6
21/IF SCON IN1IF1/ IN2IF2/ SO4 SO5 SO6 SO7 0 1 2 3 SI4 SI5 SI6 SI7 0 1 2 3
I/F counter control Timer reset Output port Timer KEY SCAN digit
7
STPSTA/ MANUAL G0 G1 2 Hz F/F Clock
CKSTP
Mode TEST #4
T0 T1 T2 T3 2 Hz F/F 10 Hz 100 Hz
STOP
F/F KS0 KS1 KS2
1
MUTE control Interrupt 1 Interrupt 2 Output port KEY input data KEY SCAN input port 0
8 MUTE
I/O POL UNLOCK POL1 INTC1 POL2 INTC2 T4 T5 T6 T7
HOLD INTR1 INTR2 1
K0 K1 K2 K3 KS00 KS01 KS02 KS03
DO2 control Interrupt 1 I/O control 1 UNLOCK IN port KEY SCAN input port 1
9 UNLOCK
RESET OTC OT2 Hz INT10 INT11 INT12 INT13 0 1 2 3 F/F ENA IN1 IN2
KS10 KS11 KS12 KS13
BUZR Interrupt 1 I/O control 2 KEY SCAN input port 2
A
B0 B1 B2 B3 INT14 INT15 INTE1 INTS1 0 1 2 3
KS20 KS21 KS22 KS23
BUZR Interrupt 2 I/O control 3 KEY SCAN input port 3
B
B4 B5 B6 B7 INT20 INT21 INT22 INT23 0 1 2 3
KS30 KS31 KS32 KS33
Interrupt 2 I/O control 4 DATA-reg KEY SCAN input port 4
C
INT24 INT25 INTE2 INTS2 0 1 2 3 d0 d1 d2 d3 KS40 KS41 KS42 KS43
G register SEG data select I/O control 5 DATA-reg KEY SCAN input port 5
D
G0 G1 G2 G3 S1 S2 S4 S8 0 1 2 3 d4 d5 d6 d7
KS50 KS51 KS52 KS53
G register SEG data 1 I/O control 6 DATA-reg KEY SCAN input port 6
E
G4
*
COM1 COM1 COM3 *0 1 2 3 d8 d9 d10 d11
KS60 KS61 KS62 KS63
TEST1 SEG data 2 I/O control 7 DATA-reg KEY SCAN input port 7
F
#0 #1 #2 #3 COM1 COM2 COM3 SEG I/O 0 1 2 3 d12 d13 d14 d15
KS70 KS71 KS72 KS73

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Connecting Crystal Oscillator
The following diagram shows the connection of the 75 kHz crystal oscillator to the device’s crystal oscillator
pins (XIN, XOUT).
The oscillation signal is supplied to the clock generator, reference frequency divider, and other sub-systems to
generate the various CPU timing signals, reference frequency, and other signals. The power supply for the
crystal oscillator circuit is the voltage (VXT 1.5 V typ.) supplied by the built-in constant voltage circuit. This
stabilizes the crystal oscillation and reduces the current consumption.
Note 17: Use a crystal oscillator with a low CI value and with good startup characteristics.
System Reset
The system is reset when a low level is applied to the RESET pin, or when the voltage supplied to the VDD
pin goes from 0 V to 1.8 V or more (a power on reset). Following a system reset, the program starts from address
0 after a standby period of 100 ms.
As the power on reset function is typically used, fix the RESET pin to the high level.
Note 18: During a system reset and during the standby period following the reset, the LCD common and segment
outputs are fixed at the low level.
Note 19: After a system reset, the internal ports shown in the following table are fixed at the specified levels. The
states of the other ports after a reset are undefined. Therefore, initialize the ports in the program when
necessary.
Fixed Internal Ports
Ports Set to “0” Ports Set to “1”
SCON bit (IL16), MANUAL bit (IL17)
I/O, POL, UNLOCK bits (IL18)
DO2 control port (IL19)
BUZR ports (IL1A, IL1B)
Test ports (IL1F, IL27, IL2FF)
CKSTP MODE bit (IL27)
DA/AD control ports (IL20, IL22)
SIO control ports (IL23, IL24)
Timer port (IK27)
VLCD OFF, KSSTP bits (IL2FF)
I/O-1~I/O-7 I/O control ports (IL39~IL3F)
Reference port (IL15)
MUTE bit (IL18)
21/IF , IN1IF1/ , IN2IF2/ bits (IL16)
DISP OFF bit (IL2FF)
SEG I/O bit
(SEG/I/O switching bits: IL2F2~IL2FD)

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Backup Modes
To enter the three backup modes, execute the CKSTP or WAIT instruction.
1. Clock Stop Mode
Clock stop mode halts the system and maintains the internal state of the system immediately prior to
halting. During a halt, the system is maintained with low current consumption (1 PA or below, at VDD 5
V). In clock stop mode, the crystal oscillator halts and the output ports and LCD display output pins are all
automatically set to the low level or the off state. The supply voltage can be reduced to 1.2 V.
When the CKSTP instruction is executed, execution halts at the address of the CKSTP instruction.
Therefore, execution starts again from the next instruction when clock stop mode is released (after a
standby period of around 100 ms).
(1) Setting clock stop mode
Clock stop mode can be set to one of two modes. The CKSTP bit determines which of the two modes
is set. Use the OUT2 instruction with the operand [CN 7H] to access this bit.
1) MODE-0
In mode 0, executing the CKSTP instruction when the HOLD pin is low enters clock stop
mode. Executing the CKSTP instruction when the HOLD pin is high is equivalent to executing
a NOOP instruction.
2) MODE-1
In mode 1, executing the CKSTP instruction enters clock stop mode regardless of the level of
the HOLD pin.
Note 20: The PLL turns off during execution of the CKSTP instruction.
(2) Releasing clock stop mode
1) MODE-0
In mode 0, clock stop mode is released when the HOLD pin goes to high, or by a change in
the input state of any I/O port 1 pin (P1-0~P1-3) set as an input port.
2) MODE-1
In mode 1, clock stop mode is released by a change in the input state of the HOLD pin or in
the input state of any I/O port 1 pin (P1-0~P1-3) set as an input port.

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(3) Clock stop mode timing
1) MODE-0
(Executing the CKSTP instruction while the HOLD pin input is low sets the device to clock
stop mode.)
2) MODE-1
(Executing the CKSTP instruction always sets the device to clock stop mode.)
(4) Circuit example (MODE-0)
Example of Backup Circuit Using Battery Example of Backup Circuit Using
Capacitor