Toshiba TMPM4K User manual

TMPM4K Group(1)
Product Inromation
2018-09-18 1 / 89 Rev. 2.1
© 2017-2018
Toshiba Electronic Devices & Storage Corporation
2018-09
32-bit RISC Microcontroller
TMPM4K Group(1)
Reference Manual
Product Information
(PINFO-M4K(1))
Revision 2.1

TMPM4K Group(1)
Product Inromation
2018-09-18 2 / 89 Rev. 2.1
Contents
Preface ................................................................................................................................................................. 7
Related documents ................................................................................................................................................... 7
Conventions .............................................................................................................................................................. 8
Terms and Abbreviations ........................................................................................................................................ 10
Overview ..................................................................................................................................................... 11
Information of Peripheral Function ............................................................................................................. 11
Register Base address ..................................................................................................................................... 11
Trigger Selector(TRGSEL)............................................................................................................................... 12
2.2.1. Trigger Selector List for the each Products ................................................................................................................ 13
2.2.2. Operation and setting ................................................................................................................................................. 18
2.2.3. List of Registers .......................................................................................................................................................... 19
2.2.4. Details of Registers .................................................................................................................................................... 20
2.2.4.1. [TSELxCR0] (Control Register 0) .................................................................................................................................. 20
2.2.4.2. [TSELxCR1] (Control Register1) ................................................................................................................................... 22
2.2.4.3. [TSELxCR2] (Control Register 2) .................................................................................................................................. 24
2.2.4.4. [TSELxCR3] (Control Register 3) .................................................................................................................................. 26
2.2.4.5. [TSELxCR4] (Control Register 4) .................................................................................................................................. 28
2.2.4.6. [TSELxCR5] (Control Register 5) .................................................................................................................................. 30
2.2.4.7. [TSELxCR6] (Control Register 6) .................................................................................................................................. 32
2.2.4.8. [TSELxCR7] (Control Register 7) .................................................................................................................................. 34
2.2.4.9. [TSELxCR8] (Control Register 8) .................................................................................................................................. 36
2.2.4.10. [TSELxCR9] (Control Register 9) ................................................................................................................................ 38
2.2.4.11. [TSELxCR10] (Control Register 10) ............................................................................................................................ 40
Direct Memory Access Controller .................................................................................................................... 41
2.3.1. Built-in unit .................................................................................................................................................................. 41
2.3.2. DMA Request Table ................................................................................................................................................... 41
32-bit Timer Event Counter(T32A) ................................................................................................................... 45
2.4.1. Built-in channel ........................................................................................................................................................... 45
2.4.2. Functional pins ........................................................................................................................................................... 46
2.4.3. Clock for prescaler ...................................................................................................................................................... 48
2.4.4. Internal signal connection specification ...................................................................................................................... 48
2.4.4.1. Capture trigger signal connection .................................................................................................................................. 48
2.4.4.2. Synchronous control connection ................................................................................................................................... 52
2.4.5. Pulse Counter List for each product ........................................................................................................................... 53
2.4.6. DMA request............................................................................................................................................................... 54
2.4.7. Internal signal connection specification ...................................................................................................................... 55
Universal Asynchronous Receiver Transmitter Circuit(UART) ........................................................................ 56
2.5.1. Built-in channel ........................................................................................................................................................... 56
2.5.2. Function pin and port .................................................................................................................................................. 56
2.5.3. Half Clock mode support ............................................................................................................................................ 57
2.5.4. Clock for Prescaler ..................................................................................................................................................... 57
2.5.5. DMA request............................................................................................................................................................... 57

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2.5.6. Internal signal connection specification ...................................................................................................................... 58
2.5.6.1. Trigger transfer signal connection ................................................................................................................................. 58
2.5.6.2. T32A connection ........................................................................................................................................................... 59
Serial Peripheral Interface(TSPI) ..................................................................................................................... 60
2.6.1. Built-in channel ........................................................................................................................................................... 60
2.6.2. Function pin and port .................................................................................................................................................. 60
2.6.3. Transfer mode of each product................................................................................................................................... 61
2.6.4. [TSPIxCR2]<RXDLY> set value ................................................................................................................................. 61
2.6.5. Clock for Prescaler ..................................................................................................................................................... 61
2.6.6. Internal signal connection specification ...................................................................................................................... 62
2.6.6.1. Trigger Transfer signal connection ................................................................................................................................ 62
2.6.6.2. T32A connection ........................................................................................................................................................... 63
2.6.7. DMA request............................................................................................................................................................... 63
I2C interface ..................................................................................................................................................... 64
2.7.1. Built-in channel ........................................................................................................................................................... 64
2.7.2. Function pin and port .................................................................................................................................................. 64
2.7.3. Clock for Prescaler ..................................................................................................................................................... 64
2.7.4. DMA request............................................................................................................................................................... 65
12-bit Analog to Digital Converter(ADC) .......................................................................................................... 66
2.8.1. Built-in unit .................................................................................................................................................................. 66
2.8.2. Function pin and port .................................................................................................................................................. 66
2.8.3. Conversion clock of ADC ............................................................................................................................................ 67
2.8.4. Startup trigger ............................................................................................................................................................. 67
2.8.5. DMA request............................................................................................................................................................... 68
2.8.6. Other connection ........................................................................................................................................................ 68
Advanced Programmable Motor Control Circuit(A-PMD) ................................................................................ 69
2.9.1. Built-in channel ........................................................................................................................................................... 69
2.9.2. Function pin and port .................................................................................................................................................. 69
2.9.3. DMA request............................................................................................................................................................... 70
2.9.4. Internal signal connection specification ...................................................................................................................... 71
2.9.4.1. Other connection ........................................................................................................................................................... 71
2.9.4.2. Inter-channel synchronous control connection .............................................................................................................. 72
Advanced Vector Engine Plus(A-VE+) .......................................................................................................... 73
2.10.1. Built-in channel ......................................................................................................................................................... 73
2.10.2. Other connection ...................................................................................................................................................... 73
Advanced Encoder input circuit(A-ENC) ........................................................................................................ 74
2.11.1. Built-in channel ......................................................................................................................................................... 74
2.11.2. Function Pin and Port ............................................................................................................................................... 74
2.11.3. Internal signal connection specification .................................................................................................................... 75
2.11.3.1. T32A/A-PMD Connection ............................................................................................................................................ 75
Operational amplifier (OPAMP) ..................................................................................................................... 76
2.12.1. Built-in unit ................................................................................................................................................................ 76
2.12.2. Connected pin .......................................................................................................................................................... 76
2.12.3. Internal connection ................................................................................................................................................... 76

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Clock Selective Watchdog Timer(SIWDT) ..................................................................................................... 77
2.13.1. Built-in channel ......................................................................................................................................................... 77
2.13.2. Count Clock .............................................................................................................................................................. 77
2.13.3. Output control ........................................................................................................................................................... 77
CRC calculation circuit(CRC) ........................................................................................................................ 78
RAM Parity(RAMP) ........................................................................................................................................ 78
2.15.1. Built-in channel ......................................................................................................................................................... 78
2.15.2. Error detection block area ........................................................................................................................................ 78
Oscillation Frequency Detection circuit(OFD)................................................................................................ 79
2.16.1. Support products ...................................................................................................................................................... 79
2.16.2. Reference Clock ....................................................................................................................................................... 79
2.16.3. Clock for detection .................................................................................................................................................... 79
Debug interface .............................................................................................................................................. 80
2.17.1. Debug interface List for each product ....................................................................................................................... 80
Non Break Debug Interface (NBDIF) ............................................................................................................. 81
2.18.1. Correspondence table .............................................................................................................................................. 81
2.18.2. NBDIF List for each product ..................................................................................................................................... 81
Digital Noise Filter(DNF) ................................................................................................................................ 82
2.19.1. Built-in unit ................................................................................................................................................................ 82
2.19.2. External Interrupt list for the each product ................................................................................................................ 82
2.19.3. Sampling source clock .............................................................................................................................................. 83
Trimming Circuit(TRM) ................................................................................................................................... 83
2.20.1. Support products ...................................................................................................................................................... 83
2.20.2. Target oscillator ........................................................................................................................................................ 83
Voltage Detection Circuit(LVD) ...................................................................................................................... 84
2.21.1. Support products ...................................................................................................................................................... 84
2.21.2. Detection power supply ............................................................................................................................................ 84
Flash Memory ................................................................................................................................................ 85
2.22.1. Clock for the Programming/Erasing .......................................................................................................................... 85
2.22.2. The code flash block configuration of each product.................................................................................................. 85
2.22.3. Single boot resource ................................................................................................................................................. 86
Revision History .......................................................................................................................................... 87
RESTRICTIONS ON PRODUCT USE ............................................................................................................... 89

TMPM4K Group(1)
Product Inromation
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List of Figures
Figure 2.1 Example of Trigger Selector Connection ................................................................................ 12
List of Tables
Table 2.1 Type of Register base address ................................................................................................ 11
Table 2.2 Trigger Selector List for each Product (1/5) ............................................................................. 13
Table 2.3 Trigger Selector List for each Product (2/5) ............................................................................. 14
Table 2.4 Trigger Selector List for each Product (3/5) ............................................................................. 15
Table 2.5 Trigger Selector List for each Product (4/5) ............................................................................. 16
Table 2.6 Trigger Selector List for each Product (5/5) ............................................................................. 17
Table 2.7 DMAC built-in unit .................................................................................................................... 41
Table 2.8 DMA Request Table (1/4) ........................................................................................................ 41
Table 2.9 DMA request table (2/4) ........................................................................................................... 42
Table 2.10 DMA request table (3/4) ......................................................................................................... 43
Table 2.11 DMA request list (4/4) ............................................................................................................ 44
Table 2.12 T32A built-in channel ............................................................................................................. 45
Table 2.13 T32A functional pin and port (1/2) ......................................................................................... 46
Table 2.14 T32A functional pins and port (2/2) ........................................................................................ 47
Table 2.15 T32A clock for prescaler ........................................................................................................ 48
Table 2.16 T32A Capture trigger connection (1/3) .................................................................................. 49
Table 2.17 T32A Capture trigger connection (2/3) .................................................................................. 50
Table 2.18 T32A Capture trigger connection (3/3) .................................................................................. 51
Table 2.19 T32A Synchronous control connection specifications ........................................................... 52
Table 2.20 T32A Pulse counter list for each product ............................................................................... 53
Table 2.21 T32A DMA request (1/2) ........................................................................................................ 54
Table 2.22 T32A DMA request (2/2) ........................................................................................................ 55
Table 2.23 UART built-in channel ............................................................................................................ 56
Table 2.24 UART functional pin and port ................................................................................................. 56
Table 2.25 UART Clock for prescaler ...................................................................................................... 57
Table 2.26 UART DMA request ............................................................................................................... 57
Table 2.27 UART trigger transfer signal connection ................................................................................ 58
Table 2.28 UART inside connection list: output ....................................................................................... 59
Table 2.29 TSPI built-in channel .............................................................................................................. 60
Table 2.30 TSPI function functional pin and port ..................................................................................... 60
Table 2.31 TSPI mode list ........................................................................................................................ 61
Table 2.32 TSPI [TSPIxCR2]<RXDLY> set value ................................................................................... 61
Table 2.33 TSPI clock for prescaler ......................................................................................................... 61
Table 2.34 TSPI trigger transfer ............................................................................................................... 62
Table 2.35 TSPI inside connection (output) ............................................................................................. 63
Table 2.36 TSPI DMA request ................................................................................................................. 63
Table 2.37 I2C interface built-in channel .................................................................................................. 64
Table 2.38 I2C interface function pin and port.......................................................................................... 64
Table 2.39 I2C interface clock for prescaler ............................................................................................. 64
Table 2.40 I2C interface DMA request ..................................................................................................... 65
Table 2.41 ADC built-in unit ..................................................................................................................... 66
Table 2.42 ADC function pin and port ...................................................................................................... 66
Table 2.43 Conversion clock of ADC ....................................................................................................... 67
Table 2.44 ADC Startup trigger ................................................................................................................ 67
Table 2.45 ADC DMA request .................................................................................................................. 68
Table 2.46 ADC inside connection: output............................................................................................... 68
Table 2.47 A-PMD built-in channel .......................................................................................................... 69
Table 2.48 A-PMD function pin ................................................................................................................ 69
Table 2.49 A-PMD DMA request.............................................................................................................. 70
Table 2.50 A-PMD inside connection list: input ....................................................................................... 71
Table 2.51 A-PMD inside connection list: output ..................................................................................... 72

TMPM4K Group(1)
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Table 2.52 PMD Inter-channel synchronous control connection ............................................................. 72
Table 2.53 A-VE+ built-in channel ........................................................................................................... 73
Table 2.54 A-VE+ Internal connection specification: Input ...................................................................... 73
Table 2.55 A-VE+ Internal connection specification: Output ................................................................... 73
Table 2.56 A-ENC built-in channel ........................................................................................................... 74
Table 2.57 A-ENC function pin ................................................................................................................. 74
Table 2.58 A-ENC Internal connection specification: Input ..................................................................... 75
Table 2.59 A-ENC Internal connection specification: Output .................................................................. 75
Table 2.60 OPAMP built-in unitl ............................................................................................................... 76
Table 2.61 OPAMP connected pin ........................................................................................................... 76
Table 2.62 OPAMP internal connection ................................................................................................... 76
Table 2.63 SIWDT built-in channel .......................................................................................................... 77
Table 2.64 SIWDT count clock ................................................................................................................. 77
Table 2.65 SIWDT output control ............................................................................................................. 77
Table 2.66 CRC built-in channel .............................................................................................................. 78
Table 2.67 RAMP built-in channel ........................................................................................................... 78
Table 2.68 RAM area and address of RAMP .......................................................................................... 78
Table 2.69 OFD support product.............................................................................................................. 79
Table 2.70 OFD reference clock .............................................................................................................. 79
Table 2.71 OFD clock for detection ......................................................................................................... 79
Table 2.72 Debug interface List ............................................................................................................... 80
Table 2.73 NBDIF correspondence table ................................................................................................. 81
Table 2.74 NBDIF interface List ............................................................................................................... 81
Table 2.75 DNF built-in unit ..................................................................................................................... 82
Table 2.76 External interrupt and DNF .................................................................................................... 82
Table 2.77 DNF sampling source clock ................................................................................................... 83
Table 2.78 TRM support product ............................................................................................................. 83
Table 2.79 TRM trimming target oscillator ............................................................................................... 83
Table 2.80 LVD support product .............................................................................................................. 84
Table 2.81 LVD detection power supply .................................................................................................. 84
Table 2.82 Clock for Programming/Erasing ............................................................................................. 85
Table 2.83 The code flash of each product ............................................................................................. 85
Table 2.84 Single boot resource .............................................................................................................. 86
Table 3.1 Revision History ....................................................................................................................... 87

TMPM4K Group(1)
Product Inromation
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Preface
Related documents
Document name
IP Symbol
Input/Output Ports
PORT-M4K(1)
Exception
EXCEPT-M4K(1)
Clock Control and Operation Mode
CG-M4K(1)-A
Power supply and Reset operation
RESET-M4K(1)
DMA controller
DMAC-B
32-bit Timer Event Counter
T32A-B
Asynchronous Serial Communication Circuit
UART-C
Serial Peripheral Interface
TSPI-B
I2C interface
I2C-B
12-bit Analog to Digital Converter
ADC-B
Operational Amplifier
OPAMP-A
Advanced Programmable Motor Control Circuit
A-PMD-A
Advanced Encoder Input Circuit
A-ENC-A
Advanced Vector Engine Plus
A-VE+-B
Clock Selective Watchdog Timer
SIWDT-A
Oscillation Frequency Detector
OFD-A
Debug Interface
DEBUG-A
Non-break debug Interface
NBDIF-A
Digital Noise Filter Circuit
DNF-A
Trimming Circuit
TRM-A
Voltage Detection Circuit
LVD-B
CRC Calculation Circuit
CRC-A
RAM Parity
RAMP-A
Flash Memory
FLASH256-B

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Conventions
Numeric formats follow the rules as shown below:
Hexadecimal: 0xABC
Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers.
Binary: 0b111 – It is possible to omit the "0b" when the number of bit can be distinctly
understood from a sentence.
"_N" is added to the end of signal names to indicate low active signals.
It is called "assert" that a signal moves to its active level, "deassert" to its inactive level.
When two or more signal names are referred, they are described like as [m: n].
Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.
The characters surrounded by [ ] defines the register.
Example: [ABCD]
"n" substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], [XYZ3] [XYZn]
"x" substitutes suffix number or character of units and channels in the Register List.
In case of unit, "x" means A, B, and C ...
Example: [ADACR0], [ADBCR0], [ADCCR0] [ADxCR0]
In case of channel, "x" means 0, 1, and 2 ...
Example: [T32A0RUNA], [T32A1RUNA], [T32A2RUNA] [T32AxRUNA]
The bit range of a register is written like as [m: n].
Example: Bit[3: 0] expresses the range of bit 3 to 0.
The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD]<EFG> =0x01 (hexadecimal), [XYZn]<VW> =1 (binary)
Word and Byte represent the following bit length.
Byte: 8 bits
Half word: 16 bits
Word: 32 bits
Double word: 64 bits
Properties of each bit in a register are expressed as follows:
R: Read only
W: Write only
R/W: Read and Write are possible
Unless otherwise specified, register access supports only word access.
The register defined as reserved must not be rewritten. Moreover, do not use the read value.
The value read from the bit having default value of "-" is unknown.
When a register containing both of writable bits and read-only bits is written, read-only bits should be
written with their default value, In the cases that default is "-", follow the definition of each register.
Reserved bits of the Write-only register should be written with their default value.
In the cases that default is "-", follow the definition of each register.
Do not use read-modified-write processing to the register of a definition which is different by writing and
read out.

TMPM4K Group(1)
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The Flash memory uses the Super Flash® technology under license from Silicon Storage Technology, Inc.
Super Flash® is registered trademark of Silicon Storage Technology, Inc.
All other company names, product names, and service names mentioned herein may be trademarks of their
respective companies.
***********************************************************************************************************************
Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
***********************************************************************************************************************

TMPM4K Group(1)
Product Inromation
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Terms and Abbreviations
Some of abbreviations used in this document are as follows:
ADC Analog to Digital Converter
A-ENC Advanced Encoder input Circuit
A-PMD Advanced Programmable Motor Control Circuit
A-VE+ Advanced Vector Engine plus
CRC Cyclic Redundancy Check
DMAC Direct Memory Access Controller
DNF Digital Noise Filter
EHOSC External High Speed Oscillator
IHOSC Internal High Speed Oscillator
INT Interrupt
I2C Inter-Integrated Circuit
LVD Voltage Detection Circuit
NBDIF Non Break Debug Interface
OFD Oscillation Frequency Detector
OPAMP Operational Amplifier
RAMP RAM parity
SIWDT Clock Selective Watchdog Timer
TRGSEL Trigger Selection circuit
TRM Trimming circuit
TSPI Toshiba Serial Peripheral Interface
T32A 32-bit Timer Event Counter
UART Universal Asynchronous Receiver Transmitter

TMPM4K Group(1)
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Overview
This chapter describes peripheral function-related channels or number of units, information of pins and product-
specific function information. Use this chapter in conjunction with Reference Manual for Peripheral Function.
Information of Peripheral Function
Register Base address
The following table shows the type of base address of each peripheral.
Table 2.1 Type of Register base address
Product Type of Base Address
TMPM4K Group(1) TYPE1
To develop each peripheral function, please refer to the above type of base address.
In case of no information of Type1/2 of the base address in the Reference manual, it use as Type1.

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Trigger Selector(TRGSEL)
The trigger selector is the circuit which chooses the one trigger and outputs the trigger signal to the peripheral
function from two or more triggers inputted from the peripheral function, the port, etc.
The trigger chosen from eight triggers by [TSEL0CRn]<INSELm> is outputted to the peripheral function of a
connection destination.
"Figure 2.1 Example of Trigger Selector Connection" is an example of connection DMA transmission end
interrupts to DMAC via trigger selector. The setup of input trigger selection, edge detection condition selection,
trigger output selection, and trigger output control is performed by [TSEL0CR3].
TRGSEL
Control Register 3
[TSEL0CR3]
<INSEL13[2:0]>
ch6 transmission
end interrupt
ch7 transmission
end interrupt
ch14 transmission
end interrupt
ch15 transmission
end interrupt
ch21 transmission
end interrupt
ch25 transmission
end interrupt
ch27 transmission
end interrupt
DMAC
DMAC
(ch31)
Input Trigger
<EN13>
Trigger source
Select the
input trigger
Input Trigger
Input Trigger
Input Trigger
Edge detection
condition
Trigger output
control
Select the
output trigger
PF2 pin
<UPDN13>
<OUTSEL13>
Input Trigger
Input Trigger
Input Trigger
Input Trigger
Figure 2.1 Example of Trigger Selector Connection

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2.2.1. Trigger Selector List for the each Products
Trigger selector of TMPM4K Group(1) consist of 11 control registers([TSEL0CR0 to 10]), and 41 triggers are
controlled.
The following table shows "Trigger Selector List of each Product".
Table 2.2 Trigger Selector List for each Product (1/5)
Register Trigger
source Trigger Source Product (

:Available, -:N/A)
Bit Symbol
M4K4
M4K2
M4K1
M4K0
[TSEL0CR0]
INSEL0 DMA ch18
ADC general purpose trigger DMA request
ADC single conversion DMA request
ADC continuous conversion DMA request
   
INSEL1 DMA ch19
T32A ch0 DMA request at match A1 register
T32A ch0 DMA request at match C1 register
T32A ch1 DMA request at match A1 register
T32A ch1 DMA request at match C1 register
A-PMD ch0 PWM interrupt
   
INSEL2 DMA ch20
T32A ch2 DMA request at match A1 register
T32A ch2 DMA request at match C1 register
T32A ch3 DMA request at match A1 register
T32A ch3 DMA request at match C1 register
A-PMD ch1 PWM interrupt
   
INSEL3 DMA ch21
T32A ch4 DMA request at match A1 register
T32A ch4 DMA request at match C1 register
T32A ch5 DMA request at match A1 register
T32A ch5 DMA request at match C1 register
   
[TSEL0CR1]
INSEL4 DMA ch22
T32A ch0 DMA request at match B1 register
T32A ch1 DMA request at match B1 register
T32A ch2 DMA request at match B1 register
T32A ch3 DMA request at match B1 register
T32A ch4 DMA request at match B1 register
T32A ch5 DMA request at match B1 register
   
INSEL5 DMA ch23
T32A ch0 DMA request at capture A0 register
T32A ch0 DMA request at capture A1 register
T32A ch1 DMA request at capture A0 register
T32A ch1 DMA request at capture A1 register
T32A ch0 DMA request at capture C0 register
T32A ch0 DMA request at capture C1 register
T32A ch1 DMA request at capture C0 register
T32A ch1 DMA request at capture C1 register
   
INSEL6 DMA ch24
T32A ch2 DMA request at capture A0 register
T32A ch2 DMA request at capture A1 register
T32A ch3 DMA request at capture A0 register
T32A ch3 DMA request at capture A1 register
T32A ch2 DMA request at capture C0 register
T32A ch2 DMA request at capture C1 register
T32A ch3 DMA request at capture C0 register
T32A ch3 DMA request at capture C1 register
   
INSEL7 DMA ch25
T32A ch4 DMA request at capture A0 register
T32A ch4 DMA request at capture A1 register
T32A ch5 DMA request at capture A0 register
T32A ch5 DMA request at capture A1 register
T32A ch4 DMA request at capture C0 register
T32A ch4 DMA request at capture C1 register
T32A ch5 DMA request at capture C0 register
T32A ch5 DMA request at capture C1 register
   

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Table 2.3 Trigger Selector List for each Product (2/5)
Register Trigger
source Trigger Source Product (

:Available, -:N/A)
Bit Symbol M4K4 M4K2 M4K1 M4K0
[TSEL0CR2]
INSEL8 DMA ch26
T32A ch0 DMA request at capture B0 register
T32A ch0 DMA request at capture B1 register
T32A ch1 DMA request at capture B0 register
T32A ch1 DMA request at capture B1 register
T32A ch2 DMA request at capture B0 register
T32A ch2 DMA request at capture B1 register
   
INSEL9 DMA ch27
T32A ch3 DMA request at capture B0 register
T32A ch3 DMA request at capture B1 register
T32A ch4 DMA request at capture B0 register
T32A ch4 DMA request at capture B1 register
T32A ch5 DMA request at capture B0 register
T32A ch5 DMA request at capture B1 register
   
INSEL10 DMA ch28
DMAC ch0 transfer completion
DMAC ch1 transfer completion
DMAC ch8 transfer completion
DMAC ch9 transfer completion
DMAC ch16 transfer completion
DMAC ch17 transfer completion
DMAC ch22 transfer completion
   
INSEL11 DMA ch29
DMAC ch2 transfer completion
DMAC ch3 transfer completion
DMAC ch10 transfer completion
DMAC ch11 transfer completion
DMAC ch18 transfer completion
DMAC ch19 transfer completion
DMAC ch23 transfer completion
   
PF0 (TRGIN0) 
 
-
[TSEL0CR3]
INSEL12 DMA ch30
DMAC ch4 transfer completion
DMAC ch5 transfer completion
DMAC ch12 transfer completion
DMAC ch13 transfer completion
DMAC ch20 transfer completion
DMAC ch24 transfer completion
DMAC ch26 transfer completion
   
PB1 (TRGIN1) 
 
-
INSEL13 DMA ch31
DMAC ch6 transfer completion
DMAC ch7 transfer completion
DMAC ch14 transfer completion
DMAC ch15 transfer completion
DMAC ch21 transfer completion
DMAC ch25 transfer completion
DMAC ch27 transfer completion
   
PF2 (TRGIN2) 
-
-
-
INSEL14 ADC
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer register B1 match trigger
T32A ch5 Timer register C1 match trigger
   
INSEL15 TSPI ch0
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer register B1 match trigger
T32A ch5 Timer register C1 match trigger
   

TMPM4K Group(1)
Product Inromation
2018-09-18 15 / 89 Rev. 2.1
Table 2.4 Trigger Selector List for each Product (3/5)
Register
Trigger
source Trigger Source
Product (:Available, -:N/A)
Bit Symbol M4K4 M4K2 M4K1 M4K0
[TSEL0CR4]
INSEL16 TSPI ch1
PF0 (TRGIN0) 
-
-
-
PB1 (TRGIN1) 
-
-
-
PF2 (TRGIN2) 
-
-
-
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer register B1 match trigger
T32A ch5 Timer register C1 match trigger
 - - -
INSEL17 TSPI ch2
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer register B1 match trigger
T32A ch5 Timer register C1 match trigger
   
INSEL18 TSPI ch3
PF0 (TRGIN0) 
-
-
-
PB1 (TRGIN1) 
-
-
-
PF2 (TRGIN2) 
-
-
-
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer register B1 match trigger
T32A ch5 Timer register C1 match trigger
 - - -
INSEL19 UART ch0
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer register B1 match trigger
T32A ch5 Timer register C1 match trigger
   
[TSEL0CR5]
INSEL20 UART ch1
PF0 (TRGIN0)   - -
PB1 (TRGIN1) 

-
-
PF2 (TRGIN2)  - - -
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer register B1 match trigger
T32A ch5 Timer register C1 match trigger
  - -
INSEL21 UART ch2
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer register B1 match trigger
T32A ch5 Timer register C1 match trigger
   
INSEL22 UART ch3
PF0 (TRGIN0) 
-
-
-
PB1 (TRGIN1) 
-
-
-
PF2 (TRGIN2) 
-
-
-
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer register B1 match trigger
T32A ch5 Timer register C1 match trigger
 - - -
INSEL23 T32A ch0
Timer A
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
UART ch0 transmission completion trigger
UART ch0 reception completion trigger
TSPI ch0 transmit completion
TSPI ch0 receive completion
   

TMPM4K Group(1)
Product Inromation
2018-09-18 16 / 89 Rev. 2.1
Table 2.5 Trigger Selector List for each Product (4/5)
Register
Trigger
source Trigger Source
Product (:Available, -:N/A)
Bit Symbol M4K4 M4K2 M4K1 M4K0
[TSEL0CR6]
INSEL24 T32A ch0
Timer B
T32A ch0 Timer register A0 match trigger
T32A ch0 Timer register A1 match trigger
T32A ch0 Timer A overflow trigger
T32A ch0 Timer A underflow trigger
   
INSEL25 T32A ch0
Timer C
T32A ch5 Timer register C0 match trigger
T32A ch5 Timer register C1 match trigger
T32A ch5 Timer C overflow trigger
T32A ch5 Timer C underflow trigger
   
INSEL26 T32A ch1
Timer A
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
UART ch1 transmission completion trigger
UART ch1 reception completion trigger
TSPI ch1 transmit completion
TSPI ch1 receive completion
  - -
INSEL27 T32A ch1
Timer B
T32A ch1 Timer register A0 match trigger
T32A ch1 Timer register A1 match trigger
T32A ch1 Timer A overflow trigger
T32A ch1 Timer A underflow trigger
   
[TSEL0CR7]
INSEL28 T32A ch1
Timer C
T32A ch0 Timer register C0 match trigger
T32A ch0 Timer register C1 match trigger
T32A ch0 Timer C overflow trigger
T32A ch0 Timer C underflow trigger
   
INSEL29 T32A ch2
Timer A
PF0 (TRGIN0)    -
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
UART ch2 transmission completion trigger
UART ch2 reception completion trigger
TSPI ch2 transmit completion
TSPI ch2 receive completion
   
INSEL30 T32A ch2
Timer B
T32A ch2 Timer register A0 match trigger
T32A ch2 Timer register A1 match trigger
T32A ch2 Timer A overflow trigger
T32A ch2 Timer A underflow trigger
   
INSEL31 T32A ch2
Timer C
T32A ch1 Timer register C0 match trigger
T32A ch1 Timer register C1 match trigger
T32A ch1 Timer C overflow trigger
T32A ch1 Timer C underflow trigger
   

TMPM4K Group(1)
Product Inromation
2018-09-18 17 / 89 Rev. 2.1
Table 2.6 Trigger Selector List for each Product (5/5)
Register
Trigger
source Trigger Source
Product (:Available, -:N/A)
Bit Symbol M4K4 M4K2 M4K1 M4K0
[TSEL0CR8]
INSEL32 T32A ch3
Timer A
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
UART ch3 transmission completion trigger
UART ch3 reception completion trigger
TSPI ch3 transmit completion
TSPI ch3 receive completion
 - - -
I2C ch0 I2C interrupt 
 
-
INSEL33 T32A ch3
Timer B
T32A ch3 Timer register A0 match trigger
T32A ch3 Timer register A1 match trigger
T32A ch3 Timer A overflow trigger
T32A ch3 Timer A underflow trigger
   
INSEL34 T32A ch3
Timer C
T32A ch2 Timer register C0 match trigger
T32A ch2 Timer register C1 match trigger
T32A ch2 Timer C overflow trigger
T32A ch2 Timer C underflow trigger
   
INSEL35 T32A ch4
Timer A
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
A-ENC ch0 divided pulse signal 
  
[TSEL0CR9]
INSEL36 T32A ch4
Timer B
T32A ch4 Timer register A0 match trigger
T32A ch4 Timer register A1 match trigger
T32A ch4 Timer A overflow trigger
T32A ch4 Timer A underflow trigger
   
INSEL37 T32A ch4
Timer C
T32A ch3 Timer register C0 match trigger
T32A ch3 Timer register C1 match trigger
T32A ch3 Timer C overflow trigger
T32A ch3 Timer C underflow trigger
   
INSEL38 T32A ch5
Timer A
PF0 (TRGIN0) 
 
-
PB1 (TRGIN1) 
 
-
PF2 (TRGIN2) 
-
-
-
ADC general purpose trigger interrupt
ADC single conversion interrupt
ADC continuous conversion interrupt
ADC monitor function 0 Interrupt
ADC monitor function 1 Interrupt
   
INSEL39 T32A ch5
Timer B
T32A ch5 Timer register A0 match trigger
T32A ch5 Timer register A1 match trigger
T32A ch5 Timer A overflow trigger
T32A ch5 Timer A underflow trigger
   
[TSEL0CR10] INSEL40 T32A ch5
Timer C
T32A ch4 Timer register C0 match trigger
T32A ch4 Timer register C1 match trigger
T32A ch4 Timer C overflow trigger
T32A ch4 Timer C underflow trigger
   

TMPM4K Group(1)
Product Inromation
2018-09-18 18 / 89 Rev. 2.1
2.2.2. Operation and setting
When using TRGSEL, please set an applicable clock enable bit to "1" (clock supply) in fsys supply stop register A
([CGFSYSENA], [CGFSYSMENA]), fsys supply stop register B ([CGFSYSENB], [CGFSYSMENB]), and fc
supply stop registers ([CGFCEN]).
An applicable register and the bit position vary according to a product. Therefore, the register may not exist with
the product. Please refer to "Clock Control and Operation Mode" of the reference manual for the details.
Setting procedure of Trigger selector is as following.
(1) Selection of an input trigger ([TSEL0CRn] <INSELm>)
Selection of the input trigger used for the trigger source is performed.
Please set up selection of the input trigger by the input trigger subdevice bit ([TSEL0CRn] <INSELm>)
of the control register. (n: register number, m: trigger number)
(2) Selection of edge detection conditions ([TSEL0CRn] <UPDNm>)
For the input trigger signal which needs edge detection, selection of rising edge or falling edge detection
is performed.
Please set up selection of edge detection conditions in the selection bit ([TSEL0CRn]<UPDNm>) of a
control register.
The following shows the trigger signal which needs edge detection.
- External trigger input (TRGIN0, TRGIN1, and TRGIN2)
(3) Selection of a trigger output ([TSEL0CRn]<OUTSELm>)
Selection of an output without or with edge detection is performed.
Please set up selection of a trigger output in the selection bit ([TSEL0CRn]<OUTSELm>) of a control
register.
(4) Output enable ([TSEL0CRn]<ENm>)
The output (enable/disable) of the selected trigger signal is chosen.
Please set up selection of output (enable/disable) in the setting bit ([TSEL0CRn]<ENm>) of a control
register. A trigger output will be enabled if [TSEL0CRn]<ENm> is set as "1".

TMPM4K Group(1)
Product Inromation
2018-09-18 19 / 89 Rev. 2.1
2.2.3. List of Registers
The table below shows control registers and their addresses.
Peripheral function Channel/Unit Base address
Trigger selector TRGSEL ch0 0x400BB800
Register name Address(Base+)
Control Register 0 [TSELxCR0] 0x0000
Control Register 1 [TSELxCR1] 0x0004
Control Register 2 [TSELxCR2] 0x0008
Control Register 3 [TSELxCR3] 0x000C
Control Register 4 [TSELxCR4] 0x0010
Control Register 5 [TSELxCR5] 0x0014
Control Register 6
[TSELxCR6]
0x0018
Control Register 7
[TSELxCR7]
0x001C
Control Register 8
[TSELxCR8]
0x0020
Control Register 9
[TSELxCR9]
0x0024
Control Register 10 [TSELxCR10] 0x0028

TMPM4K Group(1)
Product Inromation
2018-09-18 20 / 89 Rev. 2.1
2.2.4. Details of Registers
The following chapters show the detail of registers. The sign in the functional column parenthesis of each table
expresses each function signal name.
2.2.4.1. [TSELxCR0](Control Register 0)
Bit Bit Symbol
After
Reset
Type Function
31 - 0 R Read as 0
30:28 INSEL3[2:0] 000 R/W
Select the input trigger (DMA ch21)
000: T32A ch4 DMA request at match A1 register (T32A04DMAREQCMPA1)
001: T32A ch4 DMA request at match C1 register(T32A04DMAREQCMPC1)
010: T32A ch5 DMA request at match A1 register(T32A05DMAREQCMPA1)
011: T32A ch5 DMA request at match C1 register(T32A05DMAREQCMPC1)
100: Reserved
101: Reserved
110: Reserved
111: Reserved
27 - 0 R Read as 0
26 UPDN3 0 R/W
Edge detection
0: Rising edge detection
1: falling edge detection
25 OUTSEL3 0 R/W
Select the output trigger
0: The edge detection is disable
1: The edge detection is enable
24 EN3 0 R/W
Trigger output control
0: Disable
1: Enable
23 - 0 R Read as 0
22:20 INSEL2[2:0] 000 R/W
Select the input trigger (DMA ch20)
000: T32A ch2 DMA request at match A1 register(T32A02DMAREQCMPA1)
001: T32A ch2 DMA request at match C1 register(T32A02DMAREQCMPC1)
010: T32A ch3 DMA request at match A1 register(T32A03DMAREQCMPA1)
011: T32A ch3 DMA request at match C1 register(T32A03DMAREQCMPC1)
100: A-PMD ch1 PWM interrupt (INTPWM1)
101: Reserved
110: Reserved
111: Reserved
19 - 0 R Read as 0
18 UPDN2 0 R/W
Edge detection
0: Rising edge detection
1: Falling edge detection
17 OUTSEL2 0 R/W
Select the output trigger
0: The edge detection is disable
1: The edge detection is enable
16 EN2 0 R/W
Trigger output control
0: Disable
1: Enable
15 - 0 R Read as 0