Toshiba TXZ SERIES User manual

TXZ Family
CAN Controller
2018-10-30 1 / 54 Rev. 1.1
© 2018
Toshiba Electronic Devices & Storage Corporation
2018-10
32-bit RISC Microcontroller
TXZ Family
Reference Manual
CAN Controller
(CAN-A)
Revision 1.1

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CAN Controller
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Contents
Preface.................................................................................................................................................................5
Related document.....................................................................................................................................................5
Conventions ............................................................................................................................................................6
Terms and Abbreviations.......................................................................................................................................8
1. Outlines.........................................................................................................................................................9
2. Block Diagram.............................................................................................................................................10
3. Function and Operation..............................................................................................................................11
3.1. Clock Supply....................................................................................................................................................11
3.2. CAN Interface ..................................................................................................................................................11
3.3. Function ...........................................................................................................................................................12
Mailbox.......................................................................................................................................................................12
Transmit Control Register...........................................................................................................................................13
Receive Control Register............................................................................................................................................14
Remote Frame Control Register.................................................................................................................................15
Receive Filtering.........................................................................................................................................................16
Time Stamp Function .................................................................................................................................................17
Interrupt Control..........................................................................................................................................................18
3.4. Operation Mode ...............................................................................................................................................20
Configuration Mode....................................................................................................................................................20
Sleep Mode ................................................................................................................................................................22
Suspend Mode ...........................................................................................................................................................22
Test Loop Back Mode.................................................................................................................................................23
Test Error Mode..........................................................................................................................................................23
3.5. Bit Configuration ..............................................................................................................................................25
4. Register.......................................................................................................................................................28
4.1. Register list ......................................................................................................................................................28
CAN Mailbox...............................................................................................................................................................29
4.2. Details of Registers..........................................................................................................................................30
[CANMBnID]( Message ID Field Register) .................................................................................................................30
[CANMBnTSVMCF]( Time Stamp Values Message Control Field Register)..............................................................31
[CANMBnDL](Data fields Register ) ...........................................................................................................................32
[CANMBnDH](Data fields Register)............................................................................................................................32
[CANMC](Mailbox Configuration Register).................................................................................................................33
[CANMD](Mailbox Direction Register)........................................................................................................................33
[CANTRS](Transmission Request Set Register)........................................................................................................34
[CANTRR](Transmission Request Reset Register)....................................................................................................35
[CANTA](Transmission Acknowledge Register).........................................................................................................36
[CANAA](Abort Acknowledge Register)....................................................................................................................36
[CANRMP](Receive Message Pending Register).....................................................................................................37
[CANRML](Receive Message Lost Register) ...........................................................................................................38

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[CANLAM](Local Acceptance Mask Register).........................................................................................................39
[CANGAM](Global Acceptance Mask Register)........................................................................................................40
[CANMCR](Master Control Register)........................................................................................................................41
[CANGSR](Global Status Register)..........................................................................................................................42
[CANBCR1](Bit Configuration Register1).................................................................................................................43
[CANBCR2](Bit Configuration Register2).................................................................................................................43
[CANGIF](Global Interrupt Flag Register).................................................................................................................44
[CANGIM](Global Interrupt Mask Register)..............................................................................................................45
[CANMBTIF](Mailbox Transmit Interrupt Flag Register)...........................................................................................46
[CANMBRIF](Mailbox Receive Interrupt Flag Register)............................................................................................46
[CANMBIM](Mailbox Interrupt Mask Register)..........................................................................................................46
[CANCDR](Change Data Request Register)............................................................................................................47
[CANRFP](Remote Frame Pending Register)..........................................................................................................47
[CANCEC](CAN Error Counter Register) .................................................................................................................48
[CANTSP](Time Stamp Counter Prescaler Register)...............................................................................................49
[CANTSC](Time Stamp Counter Register)...............................................................................................................49
5. Usage..........................................................................................................................................................50
5.1. Receive Messages...........................................................................................................................................50
5.2. Transmitting Message......................................................................................................................................51
5.3. Remote Frame Handling..................................................................................................................................52
6. Revision History..........................................................................................................................................53
RESTRICTIONS ON PRODUCT USE...............................................................................................................54

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List of Figures
Figure 2.1 Block Diagram of CAN controller............................................................................................10
Figure 3.1 Configuration of Mailboxes.....................................................................................................12
Figure 3.2 Timing when a Receive Message Lost Occurs......................................................................14
Figure 3.3 Receive filtering ......................................................................................................................16
Figure 3.4 Timer Stamp Counter..............................................................................................................17
Figure 3.5 Block Diagram of CAN interrupt signals.................................................................................19
Figure 3.6 Flowchart of Initial Setup of CAN Controller...........................................................................21
Figure 3.7 Flowchart of Setup of Test Loop Back Mode and Test Error Mode...............................24
Figure 3.8 CAN Bit Timing .......................................................................................................................25
Figure 5.1 Flowchart of Message Reception...........................................................................................50
Figure 5.2 Flowchart of Message Transmission......................................................................................51
Figure 5.3 Flowchart of Remote Frame Handling Using the Automatic Reply Feature..........................52
List of Tables
Table 2.1 List of Signals...........................................................................................................................10
Table 3.1 List of Interrupt sources ...........................................................................................................18
Table 3.2 Restrictions when Setting the Baud Rate ................................................................................26
Table 4.1 Change of [CANRMP] and [CANRML] Registers before/ after a Message is received..........38
Table 6.1 Revision History.......................................................................................................................53

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CAN Controller
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Preface
Related document
Document Name
Clock Control and Operation Mode
Memory Map
Product Information

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CAN Controller
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Conventions
Numeric formats follow the rules as shown below:
Hexadecimal: 0xABC
Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers.
Binary: 0b111 – It is possible to omit the "0b" when the number of bit can be distinctly
understood from a sentence.
"_N" is added to the end of signal names to indicate low active signals.
It is called "assert" that a signal moves to its active level, "deassert" to its inactive level.
When two or more signal names are referred, they are described like as [m: n].
Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.
The characters surrounded by [ ] defines the register.
Example: [ABCD]
"n" substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], [XYZ3] [XYZn]
"x" substitutes suffix number or character of units and channels in the Register List.
In case of unit, "x" means A, B, and C ...
Example: [ADACR0], [ADBCR0], [ADCCR0] [ADxCR0]
In case of channel, "x" means 0, 1, and 2 ...
Example: [T32A0RUNA], [T32A1RUNA], [T32A2RUNA] [T32AxRUNA]
The bit range of a register is written like as [m: n].
Example: Bit[3: 0] expresses the range of bit 3 to 0.
The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD]<EFG> =0x01 (hexadecimal), [XYZn]<VW> =1 (binary)
Word and Byte represent the following bit length.
Byte: 8 bits
Half word: 16 bits
Word: 32 bits
Double word: 64 bits
Properties of each bit in a register are expressed as follows:
R: Read only
W: Write only
R/W: Read and Write are possible
Unless otherwise specified, register access supports only word access.
The register defined as reserved must not be rewritten. Moreover, do not use the read value.
The value read from the bit having default value of "-" is unknown.
When a register containing both of writable bits and read-only bits is written, read-only bits should be
written with their default value, In the cases that default is "-", follow the definition of each register.
Reserved bits of the Write-only register should be written with their default value.
In the cases that default is "-", follow the definition of each register.
Do not use read-modified-write processing to the register of a definition which is different by writing and
read out.

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The Flash memory uses the Super Flash® technology under license from Silicon Storage Technology, Inc.
Super Flash® is registered trademark of Silicon Storage Technology, Inc.
All other company names, product names, and service names mentioned herein may be trademarks of their
respective companies.
***********************************************************************************************************************
Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
***********************************************************************************************************************

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CAN Controller
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Terms and Abbreviations
Some of abbreviations used in this document are as follows:
CAN Controller Area Network

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CAN Controller
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1. Outlines
The CAN can operate as a transmission/ reception circuit of 1channel per unit.
The following shows the List of Function.
Function
classification
Function
Operation explanation
Protocol
Compliant with CAN version 2.0B
active
Standard and extended formats supported
CAN bus baud rate
Max 1Mbps(fsys=48MHz(Min))
Baud rate prescaler built in
Bit timing parameter
Equivalent to Intel 82527™
Message Box 32 Mailboxes
31 reception and transmission
1 reception only
Transmission
Frame support
Data Frame / Remote Frame supported
Arbitration
The mailbox with the lower number will be sent first
The mailbox with the higher priority identifier will be sent
first
Reception
Frame support
Data Frame / Remote Frame supported
Masking function
Programmable global receive mask
(common to mailboxes 0 to 30)
Programmable local receive mask
(for mailbox 31 only)
ID format
Standard / Extended ID selection
Receive Mask bit function
Time stamp For Transmission/Reception 16-bit time stamp counter
Operation Mode
Configuration mode
Mode for setting CAN
Sleep mode Low power consumption mode( Bus Sleep Mode)
Suspend mode
Inactive state on the CAN bus
Test loop-back mode
Self-acknowledge
Test error mode
Writable error counters
Interrupt
CAN Transmit
interrupt(INTCANTXD)
Interrupt when a message transmission is terminated in
normal
CAN Receive
interrupt(INTCANRXD)
Interrupt when a message reception is terminated in
normal
CAN Global interrupt (INTCANGLB)
(8 sources)
Warning level / Error passive / Bus off /
Time stamp overflow/ Transmit abort / Receive message lost/
Wake-up/ Remote frame receive

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2. Block Diagram
Figure 2.1 shows the Block Diagram of CAN controller
Control & Interrupt
Transmit buffer
Transmit data
CAN protocol controller
Receive data
CPU
interface
CAN state-machine
Mailbox
RAM
(32MailBox)
Receive
mask
CANCLK
INTCANRXD
INTCANTXD
INTCANGLB
Control
Receive buffer
Priority
Comarison
register
Data output
Data input ID matched
CANTX
CANRX
Time
Stamp
counter
Receive
filter
Figure 2.1 Block Diagram of CAN controller
Table 2.1 List of Signals
No
Symbol
Signal name
I/O
Related Reference Manual
1
INTCANRXD
CAN receive interrupt
Output
Exception
2
INTCANTXD
CAN transmission interrupt
Output
Exception
3
INTCANGLB
CAN Global interrupt
Output
Exception
4 CANTX CAN TX signal
Output
Input/Output port, Product
information
5 CANRX CAN RX signal
Input
Input/Output port, Product
information
6 CANCLK CAN clock(fsys/4)
Input
Clock Control and Operation
Mode

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3. Function and Operation
3.1. Clock Supply
When you use CAN, please set an applicable clock enable bit to "1" (clock supply) in fsys supply stop register A
([CGFSYSENA], [CGFSYSMENA]), fsys supply stop register B ([CGFSYSENB], [CGFSYSMENB]), and fc
supply stop registers ([CGFCEN]).
An applicable register and the bit position vary according to a product. Therefore, the register may not exist with
the product. Please refer to "Clock Control and Operation Mode" of the reference manual for the details.
When attempting to stop supplying the clock, make sure to check whether the CAN is stopping. Note that when
the MCU enters STOP mode, make sure to check whether the CAN is stopping as well.
When fsys clocks of CAN will stop, CANCLK will be stopped.
3.2. CAN Interface
The interface to the CAN bus is an input pin CANRX and an output pin CANTX. Connect these pins via the CAN
bus transceiver (ISO / DIS 11898 compliant).
High speed and low speed transceivers are differentiated. Care must be taken to ensure that the electrical
characteristics of these pins at the chip level (eg, 3.3 V to 5 V) satisfy the requirements of the transceiver.

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3.3. Function
Mailbox
The mailboxes consist of a single port RAM (accessible from the internal CAN core and the CPU). The CPU
controls the CAN controller by changing the settings of the mailboxes and control registers. The settings of the
mailboxes and control registers are used for such processes as reception filtering, message transmission, and
interrupt processing.
To start transmission, set the transmission request bit corresponding to the mailbox to be sent. After the bit has
been set, all transmission procedures and error processes (when errors occur) are executed without CPU
involvement. When the mailbox is set to receive, the CPU reads the mailbox data using read instructions.
The user can also set it so that an interrupt will be issued to the CPU every time a message has been successfully
received or transmitted
In total, 32 mailboxes are provided, each of which consists of 8 byte data, 29 bit IDs, and several control bits. The
mailboxes (except mailbox 31) can be set to either transmission or reception. Mailbox 31 is the receive only
mailbox. Mailbox 31 is designed so that it can receive different message ID groups using other receive masks than
mailboxes 0 to 30.
“Figure 3.1” shows the configuration of the mailboxes.
D7
D3
TSV1
ID3
D6
D2
TSV0
ID2
D5
D1
D4
D0
MCF
ID0
ID1
MailBox
(CANMBn(n= 0 to 31)) Not used
31 16 15 8 7 0
0x0018
0x0010
0x0008
0x0000
Byte3Byte2Byte1Byte0
HalfWord1
Word
HalfWord0
24 23
Offset Address
Figure 3.1 Configuration of Mailboxes
(1) Message ID field (ID3 to ID0)
‒ID extension bit <IDE>
‒Global / local acceptance mask enable bit <GAME_LAME>
‒Remote frame handling bit<RFH>
‒29-bit message ID<ID[28:0]>
(2) Message control field (MCF)
‒Remote frame transmission request bit<RTR>
‒Data length of 4 bits<DLC[3:0]>
(3) Time stamp value (TSV1,TSV0)
‒Stores time stamp counter value during receiving / transmitting message.<TSV[15:0]>
(4) Data field(D7 to D0)
-- Data of 8 bytes <D7[7:0]> to <D0[7:0]>

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Transmit Control Register
Transmission control consists of two registers. One is the transmission request set register [CANTRS], and the
other is the transmission request reset register [CANTRR]. Therefore it is possible to clear the transmission
request without generating a conflict in the handling of the transmission mailboxes in the state-machine.
This mechanism also prevents clearing the transmission request of a mailbox to which transmission is already in
progress.
When a write of data and the ID to mailbox n configured as a transmission mailbox ([CANMD]<MDn>=0) is
performed and access to mailbox n is enabled ([CANMC]<MCn>=1), setting the [CANTRS]<TRSn> bit to "1"
causes the messages in mailbox n to be transmitted.
If there is more than one mailbox configured as a transmission mailbox and more than one corresponding TRS bit
is set, then the messages will be sent in the selected order. The order of transmission depends on the <MTOS> bit
in the master control register [CANMCR].
If the [CANMCR]<MTOS> bit is "0", the mailbox with the lower number has the higher priority. For example, if
the mailboxes CANMB0, CANMB2, and CANMB5 are configured as transmission mailboxes and the
corresponding
[CANTRS]<TRSn> bits are set to "1", then the messages will be transmitted in the following order:
CANMB0, CANMB2, and CANMB5. If a new transmission request is set for CANMB0 during processing of the
CANMB2 message, then in the next internal arbitration-run, CANMB0 is selected for the next transmission
message and transmission of the CANMB0 message start after CANMB2 transmission is completed.
This will also happen when an arbitration lost error occurs when the CANMB2 message is being transmitted.
The CANMB0 message will be sent instead of the CANMB2 lost in arbitration.
If the [CANMCR]<MTOS> bit is "1", the mailbox with the highest priority ID among those mailboxes for which
transmission is requested will be transmitted. In a transmission after an arbitration lost error occurred also, the
message in the mailbox with the highest priority ID among those mailboxes for which transmission is requested at
the time will be transmitted.

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Receive Control Register
The ID of a received message is compared to the ID of the mailbox set as the receive mailbox. The comparison of
the IDs depends on the [CANMBnID]<GAME_LAME> values of the global/local acceptance mask enable bit and
the data held in the global/local acceptance mask registers [CANGAM]/[CANLAM].
When a match is detected, the ID of the received message, the control bits, and data bytes are written in the
matching mailbox. At the same time, when the corresponding receive message pending bit [CANRMP]<RMPn>
is set to "1" and the mailbox interrupt is enabled ([CANMBIM]<MBIMn>=1), the CAN receive completion
interrupt (INTCANRXD) occurs. After a match is detected, no further ID comparison takes place.
If the ID of the received message does not match with any of the mailboxes 0 to 30, the ID is compared to the ID
of the receive-only mailbox 31. When a match is detected, the settings of the received message are written in
receive-only mailbox 31.
If no match is detected, the received message will not be stored in the mailbox and no change occurs in the
mailbox.
The <RMPn> bit must be cleared by the CPU after data is read. With the <RMPn> bit set to "1", if the next
message to this mailbox n is received, the corresponding receive message lost bit <RMLn> is set to "1".
In this case, mailbox n is overwritten with the new message.
Figure 3.2 shows timing when a receive message lost occurs.
Figure 3.2 Timing when a Receive Message Lost Occurs
SOF Message 1
for mailbox “n” EOF IFS SOF Message 2
for mailbox “n” EOF IFS
CAN Bus
Message is valid
Set <RMP>
[CANRMP]register
Set <RML>
[CANRML]register
Copy ID and data to
mailbox

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Remote Frame Control Register
After a remote frame is received, the remote frame ID is compared to the mailbox ID. The comparison of the IDs
depends on the [CANMBnID]<GAME_LAME> values of the global/local acceptance mask enable bit
[CANMBnID] in the mailbox and the data held in the global/local acceptance mask registers
[CANGAM]/[CANLAM].
After an ID match is detected, no further comparison takes place.
When the remote frame ID matches with the ID of transmission mailbox n where the remote frame handling bit
[CANMBnID]<RFH> is set to "1", the [CANTRS]<TRSn> bit will be set to "1" so that the message is transmitted
responding to the remote frame. For a transmission mailbox where the [CANMBxID]<RFH> bit is set to "0", the
mailbox does not respond to the remote frame even when the ID matches.
If the ID matches with the ID of receive mailbox n, the received message is handled same as a data frame, and this
sets the [CANRMP]<RMPn> bit and the [CANRMP]<RFPn> bit to "1".
When the remote frame ID matches with the ID of mailbox n where both the [CANMBxID]<RFH> bit and the
global bit are set to "1", the ID of mailbox n is overwritten with the remote frame ID, and the mailbox will
automatically respond to the remote frame using the ID (The <TRSn> bit is set to transmit a data frame).
Therefore, when the global acceptance mask register [CANGAM] is used, one mailbox n may respond to multiple
remote frame IDs depending on the mask value.

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Receive Filtering
For mailboxes 0 to 30, the global acceptance mask register [CANGAM] will be used if the global bit in the
mailbox is set. The receiving message will be stored in the first mailbox with a matching ID. Only if there is no
matching ID in the mailboxes 0 to 30, the receiving message will be compared to the receive-only mailbox
(mailbox 31). If the local bit in mailbox 31 is set, the local acceptance mask register [CANLAM] will be used.
Figure 3.3 shows receive filtering.
Mailbox ID Receive mask register
Receive message ID
ACR 0
ACR 1
ACR
n
AMR 0
AMR 1
AMR n
Reception request
Figure 3.3 Receive filtering

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Time Stamp Function
There is a free-running 16-bit time stamp counter [CANTSC] implemented in the CAN controller to show the time
of message reception and transmission. The content of the [CANTSC] is written into the time stamp value (TSV)
of the corresponding mailbox when a received message has been stored or a message has been transmitted.
The [CANTSC] is driven by the bit clock of the CAN bus line. When the operation mode of the CAN is in
configuration mode or in sleep mode, the [CANTSC] will be stopped. After power-up reset, a write to the time
stamp counter prescaler register [CANTSP] clears the [CANTSC]to "0". The [CANTSC] is readable and writable
from the CPU both in configuration mode and normal operation mode.
Figure 3.4 shows the structure of the time stamp counter.
Prescaler Register
<TSP[3:0]>
Prescaler (4 bit)
Free running
Time Stamp Counter
<TSC[15:0]>
Time Stamp Hold Register
(16 bit)
MCU read/write
CAN bus bit clock
MCU read/write
Transmission/Reception
successful load
Count-up clock
MailBox RAM
clear
clear
clear
re-load
Re-load value
Entering sleep mode
Entering configuration mode
Write to prescaler
Hardware/Software reset
Hardware/Software reset
Entering sleep mode
Entering configuration mode
Write to prescaler
Figure 3.4 Timer Stamp Counter
The free running time stamp counter and the time stamp hold register will be cleared in the following cases:
●After reset (Power on reset or software reset)
●When the controller enters into configuration mode
●When the controller enters into sleep mode
●When a write access is performed to the [CANTSP] register.

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Interrupt Control
The CAN controller has the following interrupt sources. And these interrupt sources are divided into three groups
and each group has one interrupt output.
●CAN transmission completion interrupt (INTCANTXD)
It occurs at the completion of transmission
●CAN receive completion interrupt (INTCANRXD)
It occurs at the completion of reception
●CAN Global interrupt (INTCANGLB)
It occurs by eight sources other than those above.
Table 3.1 List of Interrupt sources
Sources
Group
Transmit interrupt
a message has been transmitted successfully.
INTCANTXD
Receive interrupt
a message has been received successfully.
INTCANRXD
Warning level interrupt
at least one of the two error counters is greater than or equal to 97.
INTCANGLB
Error passive interrupt
CAN enters the error passive mode.
Bus off interrupt
CAN enters the bus off mode.
Time stamp overflow interrupt
-
Transmit abort interrupt
-
Receive message lost interrupt
-
Walk up interrupt
after walk-up from sleep mode, this interrupt will be generated.
Remote frame receive interrupt
-
For mailbox interrupts, there are two interrupt output lines separated from global interrupts. These are the mailbox
receive completion interrupt (INTCANRXD) and the mailbox transmission completion interrupt (INTCANTXD),
which are dependent on mailbox settings.
There are two interrupt flag registers and one interrupt mask register. One interrupt flag register is for the mailbox
receive interrupt flag register [CANMBRIF] and one for the mailbox transmission interrupt flag register
[CANMBTIF]. In addition, there is the mailbox interrupt mask register [CANMBIM] for setting whether to
enable or disable each mailbox interrupt. The [CANMBIM] register is used both for transmission and receive
mailboxes.
Figure 3.5 shows the block diagram of CAN interrupt signal.

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Pulse
Pulse
Pulse
INTCANRXD
INTCANTXD
INTCANGLB
<MBRIF[31]>
<MBIM[31]>
<MBRIF[30]>
<MBIM[30]>
<MBTIF[30]>
32 sources for
receive
31 sources for
transmit
<MBRIF[0]>
<MBIM[0]>
<MBTIF[0]>
[CANGIF]<RFPF>
[CANGIM]<RFPM>
8 sources from
global interrupt
[CANGIF]<WLIF>
[CANGIM]<WLIM>
Figure 3.5 Block Diagram of CAN interrupt signals
The CAN receive completion interrupt signal INTCANRXD is the OR of the signal for which the 32 sources
issued by the mailbox receive interrupt flag register [CANMBRIF] that are ANDed with each bit of the mailbox
interrupt mask register [CANMBIM].
The CAN transmission completion interrupt signal INTCANTXD is the OR of the signal for which the 31 sources
issued by the mailbox transmission interrupt flag register [CANMBTIF] that are ANDed with each bit of the
mailbox interrupt mask register [CANMBIM].
The CAN global interrupt signal INTCANGLB is the OR of the signal for which the 8 sources issued by the
global interrupt flag register [CANGIF] that are ANDed with each bit of the global interrupt mask register
[CANGIM].

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3.4. Operation Mode
Configuration Mode
The CAN controller needs initial setup before starting operation (setting of the bit configuration registers,
[CANBCR1] and [CANBCR2]). Writes to the [CANBCR1] and [CANBCR2] are possible only when the CAN
controller is in configuration mode.
After reset, the [CANMCR]<CCR> and the [CANGSR]<CCE> are set to "1" and the configuration mode is set. A
write of "0" to the [CANMCR]<CCR> bit sets the CAN controller to the normal operation mode. After leaving
configuration mode, the [CANGSR]<CCE> bit is cleared to "0" and the power-up sequence starts. The power-up
sequence detects 11 consecutive recessive bits on the CAN bus line. After detection, the CAN controller is a bus
on and ready for operation.
A write of "1" to the [CANMCR]<CCR> bit sets the CAN controller to enter configuration mode from normal
operation mode. After the CAN controller has entered configuration mode, the [CANGSR]<CCE> bit is set to "1".
Figure 3.6 shows the flowchart of the initial setup of the CAN controller.
When the CAN controller enters into configuration mode, the CAN error counter [CANCEC], the time stamp
counter [CANTSC], and the time stamp hold registers will be cleared.