Toshiba TX03 Series User manual

32 Bit RISC Microcontroller
TX03 Series
TMPM3V6/M3V4

© 2019
Toshiba Electronic Devices & Storage Corporation

TMPM3V6/M3V4
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Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
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General precautions on the use of Toshiba MCUs
This Page explains general precautions on the use of Toshiba MCUs.
Note that if there is a difference between the general precautions and the description in the body of the docu-
ment, the description in the body of document has higher priority.
1. The MCUs’ operation at power-on
At power-on, internal state of the MCUs is unstable. Therefore, state of the pins is undefined until re-
set operation is completed.
When a reset is performed by an external reset pin, pins of the MCUs that use the reset pin are unde-
fined until reset operation by the external pin is completed.
Also, when a reset is performed by the internal power-on reset, pins of the MCUs that use the internal
power-on reset are undefined until power supply voltage reaches the voltage at which power-on reset is val-
id.
2. Unused pins
Unused input/output ports of the MCUs are prohibited to use. The pins are high-impedance.
Generally, if MCUs operate while the high-impedance pins left open, electrostatic damage or latch-up
may occur in the internal LSI due to induced voltage influenced from external noise.
Toshiba recommend that each unused pin should be connected to the power supply pins or GND pins
via resistors.
3. Clock oscillation stability
A reset state must be released after the clock oscillation becomes stable. If the clock is changed to anoth-
er clock while the program is in progress, wait until the clock is stable.
TMPM3V6/M3V4

Introduction: Notes on the description of SFR (Special Function Register) under this specification
An SFR (Special Function Register) is a control register for peripheral circuits (IP).
The SFR addresses of IPs are described in the chapter on memory map, and the details of SFR are given in
the chapter of each IP.
Definition of SFR used in this specification is in accordance with the following rules.
a. SFR table of each IP as an example
・SFR tables in each chapter of IP provides register names, addresses and brief descriptions.
・All registers have a 32-bit unique address and the addresses of the registers are defined as follows,
with some exceptions: "Base address + (Unique) address"
Base Address = 0x0000_0000
Register name Address(Base+)
Control register SAMCR 0x0004
0x000C
Note: SAMCR register address is 32 bits wide from the address 0x0000_0004 (Base Address(0x00000000) +
unique address (0x0004)).
Note: The register shown above is an example for explanation purpose and not for demonstration purpose.
This register does not exist in this microcontroller.
b. SFR(register)
・Each register basically consists of a 32-bit register (some exceptions).
・The description of each register provides bits, bit symbols, types, initial values after reset and func-
tions.
TMPM3V6/M3V4

1.2.2 SAMCR(Control register)
31 30 29 28 27 26 25 24
bit symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit symbol - - - - - - MODE
After reset 0 0 0 0 0 0 0 0
76543210
bit symbol MODE TDATA
After reset 0 0 0 1 0 0 0 0
Bit Bit Symbol Type Function
31-10 − R "0" can be read.
9-7 MODE[2:0] R/W Operation mode settings
000 : Sample mode 0
001 : Sample mode 1
010 : Sample mode 2
011 : Sample mode 3
The settings other than those above: Reserved
6-0 TDATA[6:0] W Transmitted data
Note: The Type is divided into three as shown below.
R / W READ WRITE
R READ
W WRITE
c. Data description
Meanings of symbols used in the SFR description are as shown below.
・x:channel numbers/ports
・n,m:bit numbers
d. Register description
Registers are described as shown below.
・Register name <Bit Symbol>
Example: SAMCR<MODE>="000" or SAMCR<MODE[2:0]>="000"
<MODE[2:0]> indicates bit 2 to bit 0 in bit symbol mode (3bit width).
・Register name [Bit]
Example: SAMCR[9:7]="000"
It indicates bit 9 to bit 7 of the register SAMCR (32 bit width).
TMPM3V6/M3V4

Revision History
Date Revision Comment
2019-02-06 1 First Release

Table of Contents
General precautions on the use of Toshiba MCUs
TMPM3V6/M3V4
1.1 Features......................................................................................................................................1
1.2 Block Diagram...........................................................................................................................5
1.3 Pin Layout (Top view)..............................................................................................................6
1.3.1 TMPM3V6FWFG.................................................................................................................................................................6
1.3.2 TMPM3V6FWDFG..............................................................................................................................................................6
1.3.3 TMPM3V4FWUG, TMPM3V4FSUG.................................................................................................................................7
1.3.4 TMPM3V4FWEFG, TMPM3V4FSEFG..............................................................................................................................7
1.4 Pin names and Functions...........................................................................................................8
1.4.1 Pin names and Functions for each peripheral function, control pin and
power supply pin...............................................................................................................................................................8
1.4.1.1 Peripheral functions
1.4.1.2 Debug function
1.4.1.3 Control function
1.4.1.4 Power supply pins
1.4.1.5 Capacitors between power supply pins
1.4.2 Pin names and Function of TMPM3V6/M3V4..................................................................................................................12
1.4.2.1 The detail for pin names and function list
1.4.2.2 PORT / Debug pin
1.4.2.3 Control pin
1.4.2.4 Power Supply pin
2. Product Information
2.1 Built-in Functions of the M3V6 and M3V4...........................................................................20
2.2 Information of Each Peripheral Function...............................................................................21
2.2.1 Exception...........................................................................................................................................................................21
2.2.1.1 Differences of the Interrupt Factors
2.2.2 16-bit Timer / Event Counters (TMRB)...........................................................................................................................22
2.2.3 Serial Channel (SIO/UART).............................................................................................................................................24
2.2.4 Universal Asynchronous Serial Communication Circuit (UART)...................................................................................24
2.2.5 I2C Bus (I2C/SIO)............................................................................................................................................................24
2.2.6 Synchronous Serial Interface (SSP)..................................................................................................................................25
2.2.7 Analog/Digital Converter (ADC)......................................................................................................................................25
2.2.8 Debug Interface.................................................................................................................................................................26
3. Processor Core
3.1 Information on the processor core..........................................................................................27
3.2 Configurable Options..............................................................................................................27
3.3 Exceptions/ Interruptions.........................................................................................................28
3.3.1 Number of Interrupt Inputs...............................................................................................................................................28
3.3.2 Number of Priority Level Interrupt Bits...........................................................................................................................28
3.3.3 SysTick..............................................................................................................................................................................28
3.3.4 SYSRESETREQ................................................................................................................................................................28
3.3.5 LOCKUP...........................................................................................................................................................................28
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3.3.6 Auxiliary Fault Status register..........................................................................................................................................28
3.4 Events......................................................................................................................................29
3.5 Power Management.................................................................................................................29
3.6 Exclusive access......................................................................................................................29
4. Memory Map
4.1 Memory Map...........................................................................................................................31
4.2 Bus Matrix...............................................................................................................................34
4.2.1 Structure.............................................................................................................................................................................35
4.2.1.1 Single chip mode
4.2.1.2 Single boot mode
4.2.2 Connection table................................................................................................................................................................37
4.2.2.1 Code area / SRAM area
4.2.2.2 Peripheral area / External bus area
4.3 Address lists of peripheral functions.......................................................................................40
5. Reset Operation
5.1 Cold Reset...............................................................................................................................42
5.1.1 Reset by VLTD circuit (not using RESET pin)...............................................................................................................42
5.1.2 Reset by RESET pin.........................................................................................................................................................43
5.2 Warm-up..................................................................................................................................44
5.2.1 Reset Duration...................................................................................................................................................................44
5.3 After reset................................................................................................................................44
6. Clock/Mode control
6.1 Outline.....................................................................................................................................45
6.2 Registers..................................................................................................................................46
6.2.1 Register List.......................................................................................................................................................................46
6.2.2 CGSYSCR (System control register)................................................................................................................................47
6.2.3 CGOSCCR (Oscillation control register).........................................................................................................................48
6.2.4 CGSTBYCR (Standby control register)...........................................................................................................................50
6.2.5 CGPLLSEL (PLL Selection Register)..............................................................................................................................51
6.2.6 CGCKSEL (System clock selection register)...................................................................................................................52
6.3 Clock control...........................................................................................................................53
6.3.1 Clock Type........................................................................................................................................................................53
6.3.2 Initial Values after Reset...................................................................................................................................................53
6.3.3 Clock system Diagram......................................................................................................................................................54
6.3.4 Warm-up function..............................................................................................................................................................55
6.3.5 Clock Multiplication Circuit (PLL)..................................................................................................................................57
6.3.5.1 How to configure the PLL function
6.3.5.2 The sequence of PLL setting
6.3.6 System clock......................................................................................................................................................................59
6.3.6.1 The sequence of System clock setting
6.3.7 Prescaler Clock Control.....................................................................................................................................................61
6.3.8 System Clock Pin Output Function..................................................................................................................................61
6.4 Modes and Mode Transitions..................................................................................................62
6.4.1 Mode Transitions...............................................................................................................................................................62
6.5 Operation mode.......................................................................................................................63
6.5.1 NORMAL mode................................................................................................................................................................63
6.5.2 SLOW mode......................................................................................................................................................................63
6.6 Low Power Consumption Modes............................................................................................64
6.6.1 IDLE mode........................................................................................................................................................................64
6.6.2 SLEEP mode......................................................................................................................................................................64
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6.6.3 STOP mode........................................................................................................................................................................65
6.6.4 Low power Consumption Mode Setting...........................................................................................................................66
6.6.5 Operational Status in Each Mode.....................................................................................................................................67
6.6.6 Releasing the Low Power Consumption Mode................................................................................................................68
6.6.7 Warm-up............................................................................................................................................................................70
6.6.8 Clock Operations in Mode Transition..............................................................................................................................71
6.6.8.1 Transition of operation modes: NORMAL → STOP → NORMAL
6.6.8.2 Transition of operation modes: NORMAL → SLEEP → NORMAL
6.6.8.3 Transition of operation modes: SLOW → STOP → SLOW
6.6.8.4 Transition of operation modes: SLOW → SLEEP → SLOW
6.6.9 Precaution on Transition to the Low-power Consumption Mode....................................................................................74
6.6.9.1 Case when the MCU Enters IDLE, SLEEP or STOP Mode
7. Exceptions
7.1 Overview..................................................................................................................................75
7.1.1 Exception Types................................................................................................................................................................75
7.1.2 Handling Flowchart...........................................................................................................................................................76
7.1.2.1 Exception Request and Detection
7.1.2.2 Exception Handling and Branch to the Interrupt Service Routine (Pre-emption)
7.1.2.3 Executing an ISR
7.1.2.4 Exception exit
7.2 Reset Exceptions.....................................................................................................................82
7.3 Non-Maskable Interrupts (NMI).............................................................................................82
7.4 SysTick....................................................................................................................................83
7.5 Interrupts..................................................................................................................................84
7.5.1 Interrupt Sources................................................................................................................................................................84
7.5.1.1 Interrupt Route
7.5.1.2 Generation
7.5.1.3 Transmission
7.5.1.4 Precautions when using external interrupt pins
7.5.1.5 List of Interrupt Sources
7.5.1.6 Active level
7.5.2 Interrupt Handling.............................................................................................................................................................89
7.5.2.1 Flowchart
7.5.2.2 Preparation
7.5.2.3 Detection by Clock Generator
7.5.2.4 Detection by CPU
7.5.2.5 CPU processing
7.5.2.6 Interrupt Service Routine (ISR)
7.6 Exception/Interrupt-Related Registers....................................................................................95
7.6.1 Register List.......................................................................................................................................................................95
7.6.2 NVIC Registers..................................................................................................................................................................96
7.6.2.1 SysTick Control and Status Register
7.6.2.2 SysTick Reload Value Register
7.6.2.3 SysTick Current Value Register
7.6.2.4 SysTick Calibration Value Register
7.6.2.5 Interrupt Control Registers
7.6.2.6 Interrupt Priority Register
7.6.2.7 Vector Table Offset Register
7.6.2.8 Application Interrupt and Reset Control Register
7.6.2.9 System Handler Priority Register
7.6.2.10 System Handler Control and State Register
7.6.3 Clock Generator Registers...............................................................................................................................................118
7.6.3.1 CG Interrupt Mode Control Register
7.6.3.2 CGICRCG(CG Interrupt Request Clear Register)
7.6.3.3 CGNMIFLG(NMI Flag Register)
7.6.3.4 CGRSTFLG (Reset Flag Register)
8. Digital Noise Filter Circuit (DNF)
8.1 Configuration.........................................................................................................................127
8.2 Registers................................................................................................................................128
8.2.1 Register List.....................................................................................................................................................................128
8.2.1.1 NFCKCR (Noise Filter Control Register)
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8.2.1.2 NFENCR (Noise Filter Enable register)
8.3 Operation Description...........................................................................................................132
8.3.1 Configuration...................................................................................................................................................................132
8.3.2 Operation.........................................................................................................................................................................132
8.3.3 Noise Filter Usable Operation Mode..............................................................................................................................132
8.3.4 Precautions on Use of STOP Mode................................................................................................................................132
8.3.5 Minimum Noise Filtering Time......................................................................................................................................132
9. Input / Output port
9.1 Registers................................................................................................................................133
9.1.1 Register list......................................................................................................................................................................134
9.1.2 Port function and setting list...........................................................................................................................................135
9.1.2.1 PORT A
9.1.2.2 PORT B
9.1.2.3 PORT C
9.1.2.4 PORT D
9.1.2.5 PORT E
9.1.2.6 PORT F
9.1.2.7 PORT G
9.1.2.8 PORT H
9.1.2.9 PORT I
9.1.2.10 PORT J
9.1.2.11 PORT L
9.1.2.12 PORT M
9.1.2.13 PORT N
9.1.2.14 PORT P
9.2 Block Diagrams of Ports.......................................................................................................150
9.2.1 Type FT1.........................................................................................................................................................................150
9.2.2 Type FT2.........................................................................................................................................................................151
9.2.3 Type FT3.........................................................................................................................................................................152
9.2.4 Type FT4.........................................................................................................................................................................153
9.2.5 Type FT5.........................................................................................................................................................................154
9.2.6 Type FT6.........................................................................................................................................................................155
10. 16-bit Timer / Event Counters (TMRB)
10.1 Outline.................................................................................................................................157
10.2 Differences in the Specifications........................................................................................158
10.3 Configuration.......................................................................................................................159
10.4 Registers..............................................................................................................................160
10.4.1 Register list according to channel.................................................................................................................................160
10.4.2 TBxEN (Enable register)...............................................................................................................................................161
10.4.3 TBxRUN (RUN register)..............................................................................................................................................162
10.4.4 TBxCR (Control register)..............................................................................................................................................163
10.4.5 TBxMOD (Mode register).............................................................................................................................................164
10.4.6 TBxFFCR (Flip-flop control register)...........................................................................................................................165
10.4.7 TBxST (Status register).................................................................................................................................................166
10.4.8 TBxIM (Interrupt mask register)...................................................................................................................................167
10.4.9 TBxUC (Up counter capture register)..........................................................................................................................168
10.4.10 TBxRG0 (Timer register 0).........................................................................................................................................169
10.4.11 TBxRG1 (Timer register 1).........................................................................................................................................169
10.4.12 TBxCP0 (Capture register 0)......................................................................................................................................170
10.4.13 TBxCP1 (Capture register 1)......................................................................................................................................170
10.5 Description of Operations for Each Circuit........................................................................171
10.5.1 Prescaler.........................................................................................................................................................................171
10.5.2 Up-counter (UC)............................................................................................................................................................173
10.5.3 Timer registers (TBxRG0, TBxRG1)...........................................................................................................................173
10.5.4 Capture...........................................................................................................................................................................174
10.5.5 Capture registers (TBxCP0, TBxCP1)..........................................................................................................................174
10.5.6 Up-counter capture register (TBxUC)..........................................................................................................................174
10.5.7 Comparators (CP0, CP1)...............................................................................................................................................174
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10.5.8 Timer Flip-flop (TBxFF0).............................................................................................................................................174
10.5.9 Capture interrupt (INTCAPx0, INTCAPx1).................................................................................................................174
10.6 Description of Operations for Each Mode..........................................................................175
10.6.1 16-bit interval Timer Mode...........................................................................................................................................175
10.6.2 16-bit Event Counter Mode...........................................................................................................................................175
10.6.3 16-bit PPG (Programmable Pulse Generation) Output Mode......................................................................................176
10.6.4 External Trigger PPG (Programmable Square Wave) Output Mode...........................................................................178
10.6.5 Timer synchronous mode..............................................................................................................................................179
10.7 Applications using the Capture Function............................................................................180
10.7.1 One-shot pulse output triggered by an external pulse..................................................................................................180
10.7.2 Frequency measurement................................................................................................................................................182
10.7.3 Pulse width measurement..............................................................................................................................................182
11. Universal Asynchronous Receiver-Transmitter Circuit (UART)
11.1 Outline................................................................................................................................185
11.2 Structure...............................................................................................................................186
11.3 Registers..............................................................................................................................187
11.3.1 List of Registers............................................................................................................................................................187
11.3.2 UARTxDR (Data Register)...........................................................................................................................................188
11.3.3 UARTxRSR (Receive Status Register).........................................................................................................................189
11.3.4 UARTxECR (Error Clear Register)..............................................................................................................................190
11.3.5 UARTxFR (UART Flag Register)................................................................................................................................191
11.3.6 UARTxIBRD (UART Integer Baud-rate Register)......................................................................................................192
11.3.7 UARTxFBRD (UART Fractional Baud-rate Register)................................................................................................193
11.3.8 UARTxLCR_H (UART Line Control Register)..........................................................................................................194
11.3.9 UARTxCR (UART Control Register)..........................................................................................................................196
11.3.10 UARTxIFLS (UART Interrupt FIFO Level Selection Register)...............................................................................197
11.3.11 UARTxIMSC (UART Interrupt Disable/Enable Register) .......................................................................................198
11.3.12 UARTxRIS (UART Raw Interrupt Status Register)..................................................................................................199
11.3.13 UARTxMIS (UART Masked Interrupt Status Register)............................................................................................200
11.3.14 UARTxICR (UART Interrupt Clear Register)...........................................................................................................201
11.3.15 UARTxHCCR (50% Duty Control Register).............................................................................................................202
11.4 Operation Description.........................................................................................................203
11.4.1 Transmit FIFO and Receive FIFO................................................................................................................................203
11.4.1.1 Transmit FIFO
11.4.1.2 Receive FIFO
11.4.2 Transmit Data and Receive data...................................................................................................................................203
11.4.3 Baud-rate Generator......................................................................................................................................................204
11.4.3.1 Calculating A Baud-rate Divisor
11.4.4 Transmit Logic..............................................................................................................................................................204
11.4.5 Receive Logic................................................................................................................................................................204
11.4.6 Interrupt Generation Logic............................................................................................................................................205
11.4.6.1 UART Interrupt Generation Circuit
11.4.6.2 Interrupt Generation Timing
11.4.7 50% Duty Mode............................................................................................................................................................207
11.4.7.1 Outline
11.4.7.2 Control
11.4.7.3 Operational Description
12. Serial Channel with 4bytes FIFO (SIO/UART)
12.1 Overview............................................................................................................................211
12.2 Configuration.......................................................................................................................212
12.3 Registers Description...........................................................................................................213
12.3.1 Registers List.................................................................................................................................................................213
12.3.2 SCxEN (Enable Register)..............................................................................................................................................214
12.3.3 SCxBUF (Buffer Register)............................................................................................................................................215
12.3.4 SCxCR (Control Register)............................................................................................................................................216
12.3.5 SCxMOD0 (Mode Control Register 0).........................................................................................................................218
12.3.6 SCxMOD1 (Mode Control Register 1).........................................................................................................................219
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12.3.7 SCxMOD2 (Mode Control Register 2).........................................................................................................................220
12.3.8 SCxBRCR (Baud Rate Generator Control Register)....................................................................................................222
12.3.9 SCxBRADD (Baud Rate Generator Control Register 2).............................................................................................223
12.3.10 SCxFCNF (FIFO Configuration Register)..................................................................................................................224
12.3.11 SCxRFC (Receive FIFO Configuration Register)......................................................................................................226
12.3.12 SCxTFC (Transmit FIFO Configuration Register) ...................................................................................................227
12.3.13 SCxRST (Receive FIFO Status Register)...................................................................................................................228
12.3.14 SCxTST (Transmit FIFO Status Register)..................................................................................................................229
12.4 Operation in Each Mode.....................................................................................................230
12.5 Data Format.........................................................................................................................231
12.5.1 Data Format List............................................................................................................................................................231
12.5.2 Parity Control................................................................................................................................................................232
12.5.2.1 Transmission
12.5.2.2 Reception
12.5.3 STOP Bit Length...........................................................................................................................................................232
12.6 Clock Control......................................................................................................................233
12.6.1 Prescaler.........................................................................................................................................................................233
12.6.2 Serial Clock Generation Circuit....................................................................................................................................233
12.6.2.1 Baud Rate Generator
12.6.2.2 Clock Selection Circuit
12.6.3 Transmit/Receive Buffer and FIFO..............................................................................................................................237
12.6.3.1 Configuration
12.6.3.2 Transmit/Receive Buffer
12.6.3.3 Initialize Transmit Buffer
12.6.3.4 FIFO
12.7 Status Flag...........................................................................................................................239
12.8 Error Flag.............................................................................................................................239
12.8.1 OERR Flag....................................................................................................................................................................239
12.8.2 PERR Flag.....................................................................................................................................................................240
12.8.3 FERR Flag.....................................................................................................................................................................240
12.9 Receive................................................................................................................................241
12.9.1 Receive Counter............................................................................................................................................................241
12.9.2 Receive Control Unit.....................................................................................................................................................241
12.9.2.1 I/O interface mode
12.9.2.2 UART Mode
12.9.3 Receive Operation.........................................................................................................................................................241
12.9.3.1 Receive Buffer
12.9.3.2 Receive FIFO Operation
12.9.3.3 I/O interface mode with clock output mode
12.9.3.4 Read Received Data
12.9.3.5 Wake-up Function
12.9.3.6 Overrun Error
12.10 Transmit.............................................................................................................................245
12.10.1 Transmit Counter.........................................................................................................................................................245
12.10.2 Transmit Control..........................................................................................................................................................245
12.10.2.1 In I/O Interface Mode
12.10.2.2 In UART Mode
12.10.3 Transmit Operation......................................................................................................................................................246
12.10.3.1 Operation of Transmit Buffer
12.10.3.2 Transmit FIFO Operation
12.10.3.3 Transmit in I/O interface Mode with Clock Output Mode
12.10.3.4 Level of TXDx pin after the last bit is output in I/O interface mode
12.10.3.5 Under-run error
12.10.3.6 Data Hold Time In the I/O interface mode with clock input mode
12.11 Handshake function...........................................................................................................250
12.12 Interrupt/Error Generation Timing....................................................................................251
12.12.1 Receive Interrupts........................................................................................................................................................251
12.12.1.1 Single Buffer / Double Buffer
12.12.1.2 FIFO
12.12.2 Transmit interrupts......................................................................................................................................................252
12.12.2.1 Singe Buffer / Double Buffer
12.12.2.2 FIFO
12.12.3 Error Generation..........................................................................................................................................................253
12.12.3.1 UART Mode
12.12.3.2 I/O Interface Mode
12.13 Software Reset...................................................................................................................254
12.14 Operation in Each Mode...................................................................................................255
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12.14.1 Mode 0 (I/O interface mode)......................................................................................................................................255
12.14.1.1 Transmit
12.14.1.2 Receive
12.14.1.3 Transmit and Receive (Full-duplex)
12.14.2 Mode 1 (7-bit UART mode).......................................................................................................................................266
12.14.3 Mode 2 (8-bit UART mode).......................................................................................................................................266
12.14.4 Mode 3 (9-bit UART mode).......................................................................................................................................267
12.14.4.1 Wakeup function
12.14.4.2 Protocol
13. Serial Bus Interface (I2C/SIO)
13.1 Configuration.......................................................................................................................270
13.2 Register................................................................................................................................271
13.2.1 Registers for each channel............................................................................................................................................271
13.3 I2C Bus Mode Data Format................................................................................................272
13.4 Control Registers in the I2C Bus Mode..............................................................................273
13.4.1 SBICR0(Control register 0)..........................................................................................................................................273
13.4.2 SBICR1(Control register 1)..........................................................................................................................................274
13.4.3 SBICR2(Control register 2)..........................................................................................................................................276
13.4.4 SBISR (Status Register)................................................................................................................................................277
13.4.5 SBIBR0(Serial bus interface baud rate register 0).......................................................................................................278
13.4.6 SBIDBR (Serial bus interface data buffer register)......................................................................................................278
13.4.7 SBII2CAR (I2Cbus address register)............................................................................................................................279
13.5 Control in the I2C Bus Mode..............................................................................................280
13.5.1 Serial Clock...................................................................................................................................................................280
13.5.1.1 Clock source
13.5.1.2 Clock Synchronization
13.5.2 Setting the Acknowledgement Mode............................................................................................................................281
13.5.3 Setting the Number of Bits per Transfer......................................................................................................................281
13.5.4 Slave Addressing and Address Recognition Mode......................................................................................................281
13.5.5 Operating mode.............................................................................................................................................................281
13.5.6 Configuring the SBI as a Transmitter or a Receiver....................................................................................................282
13.5.7 Configuring the SBI as a Master or a Slave.................................................................................................................282
13.5.8 Generating Start and Stop Conditions..........................................................................................................................282
13.5.9 Interrupt Service Request and Release.........................................................................................................................283
13.5.10 Arbitration Lost Detection Monitor............................................................................................................................283
13.5.11 Slave Address Match Detection Monitor....................................................................................................................285
13.5.12 General-call Detection Monitor...................................................................................................................................285
13.5.13 Last Received Bit Monitor..........................................................................................................................................285
13.5.14 Data Buffer Register (SBIDBR).................................................................................................................................285
13.5.15 Baud Rate Register (SBIBR0)....................................................................................................................................286
13.5.16 Software Reset.............................................................................................................................................................286
13.6 Data Transfer Procedure in the I2C Bus Mode..................................................................287
13.6.1 Device Initialization......................................................................................................................................................287
13.6.2 Generating the Start Condition and a Slave Address...................................................................................................287
13.6.2.1 Master mode
13.6.2.2 Slave mode
13.6.3 Transferring a Data Word.............................................................................................................................................289
13.6.3.1 Master mode (<MST> = "1")
13.6.3.2 Slave mode (<MST> = "0")
13.6.4 Generating the Stop Condition......................................................................................................................................294
13.6.5 Restart Procedure...........................................................................................................................................................294
13.7 Control register of SIO mode..............................................................................................296
13.7.1 SBICR0(control register 0)...........................................................................................................................................296
13.7.2 SBICR1(Control register 1)..........................................................................................................................................297
13.7.3 SBIDBR (Data buffer register).....................................................................................................................................298
13.7.4 SBICR2(Control register 2)..........................................................................................................................................299
13.7.5 SBISR (Status Register)................................................................................................................................................300
13.7.6 SBIBR0 (Baud rate register 0)......................................................................................................................................301
13.8 Control in SIO mode...........................................................................................................302
13.8.1 Serial Clock...................................................................................................................................................................302
13.8.1.1 Clock source
13.8.1.2 Shift Edge
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13.8.2 Transfer Modes..............................................................................................................................................................304
13.8.2.1 8-bit transmit mode
13.8.2.2 8-bit receive mode
13.8.2.3 8-bit transmit/receive mode
13.8.2.4 Data retention time of the last bit at the end of transmission
14. Synchronous Serial Port (SSP)
14.1 Overview..............................................................................................................................309
14.2 Block Diagram.....................................................................................................................310
14.3 Register................................................................................................................................311
14.3.1 Register List...................................................................................................................................................................311
14.3.2 SSPCR0(Control register 0)..........................................................................................................................................312
14.3.3 SSPCR1(Control register1)...........................................................................................................................................313
14.3.4 SSPDR(Data register)....................................................................................................................................................314
14.3.5 SSPSR(Status register)..................................................................................................................................................315
14.3.6 SSPCPSR (Clock prescale register)..............................................................................................................................316
14.3.7 SSPIMSC (Interrupt enable/disable register)................................................................................................................317
14.3.8 SSPRIS (Pre-enable interrupt status register)...............................................................................................................318
14.3.9 SSPMIS (Post-enable interrupt status register)............................................................................................................319
14.3.10 SSPICR (Interrupt clear register)................................................................................................................................320
14.4 Overview of SSP.................................................................................................................321
14.4.1 Clock prescaler..............................................................................................................................................................321
14.4.2 Transmit FIFO...............................................................................................................................................................321
14.4.3 Receive FIFO.................................................................................................................................................................321
14.4.4 Interrupt generation logic..............................................................................................................................................322
14.5 SSP operation......................................................................................................................325
14.5.1 Initial setting for SSP....................................................................................................................................................325
14.5.2 Enabling SSP.................................................................................................................................................................325
14.5.3 Clock ratios....................................................................................................................................................................325
14.6 Frame Format......................................................................................................................326
14.6.1 SSI frame format...........................................................................................................................................................327
14.6.2 SPI frame format...........................................................................................................................................................328
14.6.3 Microwire frame format................................................................................................................................................330
15. Remote Control Signal Preprocessor (RMC)
15.1 Basic operation....................................................................................................................333
15.1.1 Reception of Remote Control Signal............................................................................................................................333
15.2 Block Diagram.....................................................................................................................333
15.3 Registers..............................................................................................................................334
15.3.1 Register List...................................................................................................................................................................334
15.3.2 RMCxEN(Enable Register)...........................................................................................................................................335
15.3.3 RMCxREN(Receive Enable Register)..........................................................................................................................336
15.3.4 RMCxRBUF1(Receive Data Buffer Register 1)..........................................................................................................337
15.3.5 RMCxRBUF2(Receive Data Buffer Register 2)..........................................................................................................337
15.3.6 RMCxRBUF3(Receive Data Buffer Register 3)..........................................................................................................338
15.3.7 RMCxRCR1(Receive Control Register 1)....................................................................................................................339
15.3.8 RMCxRCR2(Receive Control Register 2) ..................................................................................................................340
15.3.9 RMCxRCR3(Receive Control Register 3) ..................................................................................................................341
15.3.10 RMCxRCR4(Receive Control Register 4) ................................................................................................................342
15.3.11 RMCxRSTAT(Receive Status Register) ...................................................................................................................343
15.3.12 RMCxEND1(Receive End bit Number Register 1) ..................................................................................................344
15.3.13 RMCxEND2(Receive End bit Number Register 2) ..................................................................................................344
15.3.14 RMCxEND3(Receive End bit Number Register 3) ..................................................................................................345
15.3.15 RMCxFSSEL(Source Clock selection Register) .......................................................................................................346
15.4 Operation Description.........................................................................................................347
15.4.1 Reception of Remote Control Signal............................................................................................................................347
15.4.1.1 Sampling clock
15.4.1.2 Basic operation
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15.4.1.3 Preparation
15.4.1.4 Enabling Reception
15.4.1.5 Stopping Reception
15.4.1.6 Receiving Remote Control Signal without Leader in Waiting Leader
15.4.1.7 A Leader only with "Low" Width
15.4.1.8 Receiving a Remote Control Signal in a Phase Method
16. Analog/Digital Converter (ADC)
16.1 Functions and features.........................................................................................................357
16.2 Block Diagram.....................................................................................................................357
16.3 List of Registers...................................................................................................................358
16.4 Register Descriptions...........................................................................................................359
16.4.1 ADCLK (Clock Setting Register).................................................................................................................................359
16.4.2 ADMOD0 (Mode Setting Register 0) .........................................................................................................................360
16.4.3 ADMOD1 (Mode Setting Register 1) .........................................................................................................................361
16.4.4 ADMOD2 (Mode Setting Register 2) .........................................................................................................................362
16.4.5 ADMOD3 (Mode Setting Register 3) .........................................................................................................................363
16.4.6 ADCMPCR0(Monitoring Setting Register 0)...............................................................................................................364
16.4.7 ADCMPCR1(Monitoring Setting Register 1)...............................................................................................................365
16.4.8 ADCMP0(Conversion Result Compare Register 0).....................................................................................................366
16.4.9 ADCMP1(Conversion Result Compare Register 1).....................................................................................................366
16.4.10 ADREG0(Conversion Result Register 0)...................................................................................................................367
16.4.11 ADREG1(Conversion Result Register 1)...................................................................................................................368
16.4.12 ADREG2(Conversion Result Register 2)...................................................................................................................369
16.4.13 ADREG3(Conversion Result Register 3)...................................................................................................................370
16.4.14 ADREG4(Conversion Result Register 4)...................................................................................................................371
16.4.15 ADREG5(Conversion Result Register 5)...................................................................................................................372
16.4.16 ADREG6(Conversion Result Register 6)...................................................................................................................373
16.4.17 ADREG7(Conversion Result Register 7)...................................................................................................................374
16.4.18 ADREG8(Conversion Result Register 8)...................................................................................................................375
16.4.19 ADREG9(Conversion Result Register 9)...................................................................................................................376
16.4.20 ADREG10(Conversion Result Register 10)...............................................................................................................377
16.4.21 ADREG11(Conversion Result Register 11)...............................................................................................................378
16.4.22 ADTSET03 / ADTSET47 / ADTSET811 (Timer Trigger Program Registers) .......................................................379
16.4.23 ADSSET03 / ADSSET47 / ADSSET811( Software Trigger Program Registers )...................................................383
16.4.24 ADASET03 / ADASET47 / ADASET811( Constant Conversion Program Registers )...........................................387
16.5 Operation Descriptions........................................................................................................391
16.5.1 Analog Reference Voltages...........................................................................................................................................391
16.5.2 Starting AD Conversion................................................................................................................................................391
16.5.3 AD Conversion Monitoring Function...........................................................................................................................392
16.6 Timing chart of AD conversion..........................................................................................393
16.6.1 Software trigger Conversion.........................................................................................................................................393
16.6.2 Constant Conversion......................................................................................................................................................395
16.6.3 AD conversion by trigger..............................................................................................................................................396
17. Real Time Clock (RTC)
17.1 Function...............................................................................................................................399
17.2 Block Diagram.....................................................................................................................399
17.3 Detailed Description Register.............................................................................................400
17.3.1 Register List...................................................................................................................................................................400
17.3.2 Control Register.............................................................................................................................................................400
17.3.3 Detailed Description of Control Register.....................................................................................................................402
17.3.3.1 RTCSECR (Second column register (for PAGE0 only))
17.3.3.2 RTCMINR (Minute column register (PAGE0/1))
17.3.3.3 RTCHOURR (Hour column register(PAGE0/1))
17.3.3.4 RTCDAYR (Day of the week column register(PAGE0/1))
17.3.3.5 RTCDATER (Day column register (for PAGE0/1 only))
17.3.3.6 RTCMONTHR (Month column register (for PAGE0 only))
17.3.3.7 RTCMONTHR (Selection of 24-hour clock or 12-hour clock (for PAGE1 only))
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17.3.3.8 RTCYEARR (Year column register (for PAGE0 only))
17.3.3.9 RTCYEARR (Leap year register (for PAGE1 only))
17.3.3.10 RTCPAGER(PAGE register(PAGE0/1))
17.3.3.11 RTCRESTR (Reset register (for PAGE0/1))
17.4 Operational Description.......................................................................................................410
17.4.1 Reading clock data........................................................................................................................................................410
17.4.2 Writing clock data.........................................................................................................................................................410
17.4.3 Entering the Low Power Consumption Mode..............................................................................................................412
17.5 Alarm function.....................................................................................................................413
17.5.1 "Low" pulse (when the alarm register corresponds with the clock)...........................................................................413
17.5.2 Outputting Low-pulse (1 Hz, 2 Hz, 4 Hz, 8 Hz or 16 Hz)..........................................................................................414
18. Power-on-Reset Circuit (POR)
18.1 Structure...............................................................................................................................415
18.2 Function...............................................................................................................................416
19. Low Voltage Detection Circuit (VLTD)
19.1 Structure...............................................................................................................................417
19.2 Registers..............................................................................................................................418
19.2.1 Register List...................................................................................................................................................................418
19.2.2 VDCR (Voltage detection control register)..................................................................................................................418
19.3 Operation Description.........................................................................................................419
19.3.1 Control...........................................................................................................................................................................419
19.3.2 Function.........................................................................................................................................................................419
19.3.2.1 Enabling/disabling the voltage detection operation
19.3.2.2 Selecting the detection voltage level
20. Oscillation Frequency Detector (OFD)
20.1 Block diagram.....................................................................................................................421
20.2 Registers..............................................................................................................................422
20.2.1 Register List...................................................................................................................................................................422
20.2.1.1 OFDCR1 (Control register 1)
20.2.1.2 OFDCR2 (Control register 2)
20.2.1.3 OFDMN (Lower detection frequency setting register)
20.2.1.4 OFDMX (Higher detection frequency setting register)
20.2.1.5 OFDRST (Reset control register)
20.2.1.6 OFDSTAT (Status register)
20.3 Operational Description.......................................................................................................428
20.3.1 Setting............................................................................................................................................................................428
20.3.2 Operation.......................................................................................................................................................................428
20.3.3 Detection Frequency......................................................................................................................................................429
20.3.4 Available Operation Mode............................................................................................................................................429
20.3.5 Example of Operational Procedure...............................................................................................................................430
21. Watchdog Timer(WDT)
21.1 Configuration.......................................................................................................................431
21.2 Register................................................................................................................................432
21.2.1 WDMOD(Watchdog Timer Mode Register) ...............................................................................................................432
21.2.2 WDCR (Watchdog Timer Control Register)................................................................................................................434
21.3 Operations............................................................................................................................435
21.3.1 Basic Operation.............................................................................................................................................................435
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21.3.2 Operation Mode and Status...........................................................................................................................................435
21.4 Operation when malfunction (runaway) is detected...........................................................436
21.4.1 INTWDT interrupt generation.......................................................................................................................................436
21.4.2 Internal reset generation................................................................................................................................................437
21.5 Control register....................................................................................................................438
21.5.1 Watchdog Timer Mode Register (WDMOD)...............................................................................................................438
21.5.2 Watchdog Timer Control Register(WDCR).................................................................................................................438
21.5.3 Setting example.............................................................................................................................................................439
21.5.3.1 Disabling control
21.5.3.2 Enabling control
21.5.3.3 Watchdog timer clearing control
21.5.3.4 Detection time of watchdog timer
22. Flash Memory Operation
22.1 Features................................................................................................................................441
22.1.1 Memory Size and Configuration...................................................................................................................................441
22.1.2 Function.........................................................................................................................................................................442
22.1.3 Operation Mode.............................................................................................................................................................442
22.1.3.1 Mode Description
22.1.3.2 Mode Determination
22.1.4 Memory Map.................................................................................................................................................................445
22.1.5 Protect/Security Function..............................................................................................................................................446
22.1.5.1 Protect Function
22.1.5.2 Protect Bit Mask Function
22.1.5.3 Security Function
22.1.6 Register..........................................................................................................................................................................448
22.1.6.1 Register List
22.1.6.2 FCSECBIT (Security bit register)
22.1.6.3 FCCR (Flash Interface control register)
22.1.6.4 FCSR (Flash status register)
22.1.6.5 FCPSRA (Flash protect status register)
22.1.6.6 FCPMRA (Flash protect mask register)
22.2 Detail of Flash Memory......................................................................................................453
22.2.1 Function.........................................................................................................................................................................453
22.2.2 Operation Mode of Flash Memory...............................................................................................................................453
22.2.3 Hardware Reset..............................................................................................................................................................453
22.2.4 How to Execute Command...........................................................................................................................................454
22.2.5 Command Description...................................................................................................................................................454
22.2.5.1 Automatic Page Program
22.2.5.2 Automatic Chip Erase
22.2.5.3 Automatic Block Erase
22.2.5.4 Automatic Protect Bit Program
22.2.5.5 Auto Protect Bit Erase
22.2.5.6 ID-Read
22.2.5.7 Read Command and Read/reset Command (Software Reset)
22.2.6 Command Sequence......................................................................................................................................................458
22.2.6.1 Command Sequence List
22.2.6.2 Address Bit Configuration in the Bus Cycle
22.2.6.3 Block Address (BA)
22.2.6.4 How to Specify Protect Bit (PBA)
22.2.6.5 ID-Read Code (IA, ID)
22.2.6.6 Example of Command Sequence
22.2.7 Flowchart.......................................................................................................................................................................462
22.2.7.1 Automatic Program
22.2.7.2 Automatic Erase
22.3 How to Reprogram Flash using Single Boot Mode...........................................................464
22.3.1 Mode Setting..................................................................................................................................................................464
22.3.2 Interface Specification...................................................................................................................................................464
22.3.3 Restrictions on Internal Memories................................................................................................................................465
22.3.4 Operation Command......................................................................................................................................................465
22.3.4.1 RAM Transfer
22.3.4.2 Flash Memory Chip Erase and Protect Bit Erase
22.3.5 Common Operation regardless of Command...............................................................................................................466
22.3.5.1 Serial Operation Mode Determination
22.3.5.2 Acknowledge Response Data
22.3.5.3 Password Determination
22.3.5.4 CHECK SUM Calculation
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22.3.6 Transfer Format at RAM Transfer................................................................................................................................472
22.3.7 Transfer Format of Flash memory Chip Erase and Protect Bit Erase.........................................................................474
22.3.8 Boot Program Whole Flowchart...................................................................................................................................476
22.3.9 Reprogramming Procedure of Flash using reprogramming algorithm in the on-chip BOOT ROM..........................477
22.3.9.1 Step-1
22.3.9.2 Step-2
22.3.9.3 Step-3
22.3.9.4 Step-4
22.3.9.5 Step-5
22.3.9.6 Step-6
22.4 Programming in the User Boot Mode.................................................................................480
22.4.1 (1-A) Procedure that a Programming Routine Stored in Flash memory.....................................................................480
22.4.1.1 Step-1
22.4.1.2 Step-2
22.4.1.3 Step-3
22.4.1.4 Step-4
22.4.1.5 Step-5
22.4.1.6 Step-6
22.4.2 (1-B) Procedure that a Programming Routine is transferred from External Host .....................................................484
22.4.2.1 Step-1
22.4.2.2 Step-2
22.4.2.3 Step-3
22.4.2.4 Step-4
22.4.2.5 Step-5
22.4.2.6 Step-6
23. Debug Interface
23.1 Specification Overview.......................................................................................................489
23.2 SWJ-DP...............................................................................................................................489
23.3 ETM.....................................................................................................................................489
23.4 Pin Functions.......................................................................................................................490
23.5 Peripheral Functions in Halt Mode.....................................................................................491
23.6 Connection with a Debug Tool...........................................................................................492
23.6.1 About connection with debug tool................................................................................................................................492
23.6.2 Important points of using debug interface pins used as general-purpose ports...........................................................492
24. Port Section Equivalent Circuit Schematic
24.1 PA0 to 7, PB0 to 7, PC0 to 7, PD0 to 6, PE0 to 7, PF0 to 4, PG0 to 7, PL2, PN0 to 7....
493
24.2 PH0 to 7, PI0 to 1, PJ0 to 7................................................................................................493
24.3 PL0.......................................................................................................................................494
24.4 PM0 to 1, PP0 to 1..............................................................................................................494
24.5 X1, X2.................................................................................................................................495
24.6 XT1, XT2............................................................................................................................495
24.7 RESET.................................................................................................................................495
24.8 MODE..................................................................................................................................495
24.9 FTEST3................................................................................................................................496
24.10 VREFH, VREFL...............................................................................................................496
25. Electrical Characteristics
25.1 Absolute Maximum Ratings................................................................................................497
25.2 DC Electrical Characteristics (1/3).....................................................................................498
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