Toshiba TX03 Series User manual

32 Bit RISC Microcontroller
TX03 Series
TMPM3V6/M3V4

© 2019
Toshiba Electronic Devices & Storage Corporation

TMPM3V6/M3V4
*************************************************************************************************************************
Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
*************************************************************************************************************************

General precautions on the use of Toshiba MCUs
This Page explains general precautions on the use of Toshiba MCUs.
Note that if there is a difference between the general precautions and the description in the body of the docu-
ment, the description in the body of document has higher priority.
1. The MCUs’ operation at power-on
At power-on, internal state of the MCUs is unstable. Therefore, state of the pins is undefined until re-
set operation is completed.
When a reset is performed by an external reset pin, pins of the MCUs that use the reset pin are unde-
fined until reset operation by the external pin is completed.
Also, when a reset is performed by the internal power-on reset, pins of the MCUs that use the internal
power-on reset are undefined until power supply voltage reaches the voltage at which power-on reset is val-
id.
2. Unused pins
Unused input/output ports of the MCUs are prohibited to use. The pins are high-impedance.
Generally, if MCUs operate while the high-impedance pins left open, electrostatic damage or latch-up
may occur in the internal LSI due to induced voltage influenced from external noise.
Toshiba recommend that each unused pin should be connected to the power supply pins or GND pins
via resistors.
3. Clock oscillation stability
A reset state must be released after the clock oscillation becomes stable. If the clock is changed to anoth-
er clock while the program is in progress, wait until the clock is stable.
TMPM3V6/M3V4

Introduction: Notes on the description of SFR (Special Function Register) under this specification
An SFR (Special Function Register) is a control register for peripheral circuits (IP).
The SFR addresses of IPs are described in the chapter on memory map, and the details of SFR are given in
the chapter of each IP.
Definition of SFR used in this specification is in accordance with the following rules.
a. SFR table of each IP as an example
・SFR tables in each chapter of IP provides register names, addresses and brief descriptions.
・All registers have a 32-bit unique address and the addresses of the registers are defined as follows,
with some exceptions: "Base address + (Unique) address"
Base Address = 0x0000_0000
Register name Address(Base+)
Control register SAMCR 0x0004
0x000C
Note: SAMCR register address is 32 bits wide from the address 0x0000_0004 (Base Address(0x00000000) +
unique address (0x0004)).
Note: The register shown above is an example for explanation purpose and not for demonstration purpose.
This register does not exist in this microcontroller.
b. SFR(register)
・Each register basically consists of a 32-bit register (some exceptions).
・The description of each register provides bits, bit symbols, types, initial values after reset and func-
tions.
TMPM3V6/M3V4

1.2.2 SAMCR(Control register)
31 30 29 28 27 26 25 24
bit symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit symbol - - - - - - MODE
After reset 0 0 0 0 0 0 0 0
76543210
bit symbol MODE TDATA
After reset 0 0 0 1 0 0 0 0
Bit Bit Symbol Type Function
31-10 − R "0" can be read.
9-7 MODE[2:0] R/W Operation mode settings
000 : Sample mode 0
001 : Sample mode 1
010 : Sample mode 2
011 : Sample mode 3
The settings other than those above: Reserved
6-0 TDATA[6:0] W Transmitted data
Note: The Type is divided into three as shown below.
R / W READ WRITE
R READ
W WRITE
c. Data description
Meanings of symbols used in the SFR description are as shown below.
・x:channel numbers/ports
・n,m:bit numbers
d. Register description
Registers are described as shown below.
・Register name <Bit Symbol>
Example: SAMCR<MODE>="000" or SAMCR<MODE[2:0]>="000"
<MODE[2:0]> indicates bit 2 to bit 0 in bit symbol mode (3bit width).
・Register name [Bit]
Example: SAMCR[9:7]="000"
It indicates bit 9 to bit 7 of the register SAMCR (32 bit width).
TMPM3V6/M3V4

Revision History
Date Revision Comment
2019-02-06 1 First Release

Table of Contents
General precautions on the use of Toshiba MCUs
TMPM3V6/M3V4
1.1 Features......................................................................................................................................1
1.2 Block Diagram...........................................................................................................................5
1.3 Pin Layout (Top view)..............................................................................................................6
1.3.1 TMPM3V6FWFG.................................................................................................................................................................6
1.3.2 TMPM3V6FWDFG..............................................................................................................................................................6
1.3.3 TMPM3V4FWUG, TMPM3V4FSUG.................................................................................................................................7
1.3.4 TMPM3V4FWEFG, TMPM3V4FSEFG..............................................................................................................................7
1.4 Pin names and Functions...........................................................................................................8
1.4.1 Pin names and Functions for each peripheral function, control pin and
power supply pin...............................................................................................................................................................8
1.4.1.1 Peripheral functions
1.4.1.2 Debug function
1.4.1.3 Control function
1.4.1.4 Power supply pins
1.4.1.5 Capacitors between power supply pins
1.4.2 Pin names and Function of TMPM3V6/M3V4..................................................................................................................12
1.4.2.1 The detail for pin names and function list
1.4.2.2 PORT / Debug pin
1.4.2.3 Control pin
1.4.2.4 Power Supply pin
2. Product Information
2.1 Built-in Functions of the M3V6 and M3V4...........................................................................20
2.2 Information of Each Peripheral Function...............................................................................21
2.2.1 Exception...........................................................................................................................................................................21
2.2.1.1 Differences of the Interrupt Factors
2.2.2 16-bit Timer / Event Counters (TMRB)...........................................................................................................................22
2.2.3 Serial Channel (SIO/UART).............................................................................................................................................24
2.2.4 Universal Asynchronous Serial Communication Circuit (UART)...................................................................................24
2.2.5 I2C Bus (I2C/SIO)............................................................................................................................................................24
2.2.6 Synchronous Serial Interface (SSP)..................................................................................................................................25
2.2.7 Analog/Digital Converter (ADC)......................................................................................................................................25
2.2.8 Debug Interface.................................................................................................................................................................26
3. Processor Core
3.1 Information on the processor core..........................................................................................27
3.2 Configurable Options..............................................................................................................27
3.3 Exceptions/ Interruptions.........................................................................................................28
3.3.1 Number of Interrupt Inputs...............................................................................................................................................28
3.3.2 Number of Priority Level Interrupt Bits...........................................................................................................................28
3.3.3 SysTick..............................................................................................................................................................................28
3.3.4 SYSRESETREQ................................................................................................................................................................28
3.3.5 LOCKUP...........................................................................................................................................................................28
i

3.3.6 Auxiliary Fault Status register..........................................................................................................................................28
3.4 Events......................................................................................................................................29
3.5 Power Management.................................................................................................................29
3.6 Exclusive access......................................................................................................................29
4. Memory Map
4.1 Memory Map...........................................................................................................................31
4.2 Bus Matrix...............................................................................................................................34
4.2.1 Structure.............................................................................................................................................................................35
4.2.1.1 Single chip mode
4.2.1.2 Single boot mode
4.2.2 Connection table................................................................................................................................................................37
4.2.2.1 Code area / SRAM area
4.2.2.2 Peripheral area / External bus area
4.3 Address lists of peripheral functions.......................................................................................40
5. Reset Operation
5.1 Cold Reset...............................................................................................................................42
5.1.1 Reset by VLTD circuit (not using RESET pin)...............................................................................................................42
5.1.2 Reset by RESET pin.........................................................................................................................................................43
5.2 Warm-up..................................................................................................................................44
5.2.1 Reset Duration...................................................................................................................................................................44
5.3 After reset................................................................................................................................44
6. Clock/Mode control
6.1 Outline.....................................................................................................................................45
6.2 Registers..................................................................................................................................46
6.2.1 Register List.......................................................................................................................................................................46
6.2.2 CGSYSCR (System control register)................................................................................................................................47
6.2.3 CGOSCCR (Oscillation control register).........................................................................................................................48
6.2.4 CGSTBYCR (Standby control register)...........................................................................................................................50
6.2.5 CGPLLSEL (PLL Selection Register)..............................................................................................................................51
6.2.6 CGCKSEL (System clock selection register)...................................................................................................................52
6.3 Clock control...........................................................................................................................53
6.3.1 Clock Type........................................................................................................................................................................53
6.3.2 Initial Values after Reset...................................................................................................................................................53
6.3.3 Clock system Diagram......................................................................................................................................................54
6.3.4 Warm-up function..............................................................................................................................................................55
6.3.5 Clock Multiplication Circuit (PLL)..................................................................................................................................57
6.3.5.1 How to configure the PLL function
6.3.5.2 The sequence of PLL setting
6.3.6 System clock......................................................................................................................................................................59
6.3.6.1 The sequence of System clock setting
6.3.7 Prescaler Clock Control.....................................................................................................................................................61
6.3.8 System Clock Pin Output Function..................................................................................................................................61
6.4 Modes and Mode Transitions..................................................................................................62
6.4.1 Mode Transitions...............................................................................................................................................................62
6.5 Operation mode.......................................................................................................................63
6.5.1 NORMAL mode................................................................................................................................................................63
6.5.2 SLOW mode......................................................................................................................................................................63
6.6 Low Power Consumption Modes............................................................................................64
6.6.1 IDLE mode........................................................................................................................................................................64
6.6.2 SLEEP mode......................................................................................................................................................................64
ii