Toshiba TC9349AFG User manual

TC9349AFG
2006-02-24
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9349AFG
Single-Chip DTS Microcontroller (DTS-21)
The TC9349AFG is a single-chip DTS microcontroller for portable audio
incorporating a 30 MHz prescaler, PLL, and LCD driver. In addition to an
IF counter, serial interface and buzzer function, the device incorporates an
interrupt function, timer counter, pulse counter, electronic volume function
and A/D converter
The device also supports selection of 1/4-duty 1/2 bias or 1/4-duty 1/3
bias for the LCD driver, while a built-in 3 V voltage doubler boosting
circuit implements stable operation of the LCD monitor.
The power supply voltage ranges from 0.9 V to 1.8 V. Due to its
low-current consumption, the device is suitable for use in digital tuning
systems in portable equipment such as headphone stereos.
Features
• CMOS DTS microcontroller LSI with built-in prescaler PLL and LCD driver
• Operating voltage range: VDD =0.9 to 1.8 V (typ.: 1.5 V)
• Current dissipation: With CPU in operation: IDD =150 µA (typ.)
With PLL in operation: IDD =1 mA (typ. At inputting OSCin =30 MHz)
• Operating temperature range: Ta =−10 to 60°C
• Program memory (ROM): 16-bit ×8192 steps
• Data memory (RAM): 4-bit ×512 words
• Oscillator frequency: Crystal oscillator: 75 kHz (crystal oscillator)
High-speed oscillator: 300 to 600 kHz (ceramic oscillator or crystal oscillator)
• Instruction execution time: Crystal oscillator: 40 µs
High-speed oscillator: 5 to 10 µs
• Interrupt: External: 2 system (INTR1, INTR2 pin)
Internal: 4 system (serial-interface, timer-port, timer-counter, decreased voltage
detection)
• Interrupt stack: 4 level ×26 bit G-register, Data select, Carry flag, Data register
• Address stack: 16 level ×13 bit (program counter)
• I/O port: CMOS I/O port: 36 (max)
N-ch open-drain I/O port: 9 (max)
Exclusive output port: 2 (max), exclusive input port: 1 (max)
• LCD driver: 1/4 duty, 1/2 bias or 1/4 duty, 1/3 bias: 72 segments (max)
• Serial Interface: 1 system, 2 channel (N-ch open-drain, CMOS I/O port), 3 kinds (3-wired, 2-wired,
UART)
• Buzzer: 4 kinds of frequency (1 kHz, 1.56 kHz, 2.08 kHz, 3 kHz),
4 modes (continuous, single-shot, 10 Hz intermittent, 10 Hz intermittent 1 Hz interval)
• Timer counter: 8 bit, 2 kinds of timer clock (25 kHz, 1 kHz),
2 modes (timer counter, pulse width measure (INTR1 pin))
• Pulse counter: 8 bit up/down counter
• Electronic volume: 2 channel, 32 step (0 dB to −78 dB, −∞dB)
• A/D converter: 6 bit, 4 channel, conversion time: 240 µs
• Amplifier for LPF: 5.5 V output max. (Tout, Tin)
• DC/DC converter of VT: 2 stage (0.75 V, 1.0 V) voltage detected (VDET)
15 kinds of doubler clock, 2 types of doubler clock output
(CMOS output: DDCK2, N-ch output: DDCK1)
Weight: 0.32 g (typ.)

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• DC/DC converter for CPU: Charge-pump type
Two kinds of doubler clock: 75 kHz crystal oscillator,
high-speed oscillator clock (300 to 600 kHz),
setting doubler voltage for 3 stages (2.0 V, 2.5 V, 3.0 V)
• Programmable counter: 16-bit HF mode: 1/15 or 16-pulse swallow-type (1 to 30 MHz, Vin =0.1Vp-p (min))
LF mode: 12 bit direct divider type (0.5 to 4 MHz, Vin =0.1Vp-p (min))
• Reference frequency: 10 kinds (1 kHz, 1.3889 kHz, 1.5625 kHz, 2.7778 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25
kHz, 12.5 kHz, 25 kHz)
• Phase comparator: 2 (max), setting for “H”/“L” level, High-impedance and built-in output resistor by
program. two units (max); “H”/“L” level-setting, high-impedance setting, and built-in
output resistor setting (0 kΩ, 5 kΩ, 50 kΩ, 100 kΩ) possible through programming
(DO1/DO2); automatic change of output resistor according to phase difference is possible
through programming. (DO2)
• General-purpose IF counter: 20 bits, 0.03 to 12 MHz, Vin =0.1Vp-p (min)
• Backup function: three modes: clock stop (stoppage of crystal oscillator); hard wait, (crystal oscillator
operation only); soft wait (CPU intermittent operation)
• Reset function: Built-in power-on reset circuit
• Decreased voltage detection function: Voltage detection is possible in 25 mV steps in the range VDD =0.850 V to 1.225 V.
Decreased voltage detection enables selection of the CPU stop function.
• Package: QFP-64 (0.5 mm in pitch, 1.4 mm thick)
• EEPROM product: TC93E49FG
Note: This product is sensitive to electrostatic discharge. Handle with care.

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Pin Assignment
P15-1/S14
P15-0/S13
P14-3/S12
P14-2/S11
P14-1/S10
P14-0/S9
P13-3/S8
P13-2/S7
P13-1/S6
P13-0/S5
P12-3/S4
P12-2/S3
P12-1/S2
P12-0/S1
P10-3/COM4
P10-2/COM3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
IFin/IN
VPLL
OSCin
GND (PLL)
DO1/OT1/P
DO2/OT2/N/Tin
P9-0/Tou
t
MUTE/P9-1
P9-2/DDCK2/TES
T
P8-0/VDET (BRK13)
P8-1/SI2/DDCK1 (BRK14)
P8-2/SCK2/RX2 (BRK15)
P8-3/SDIO2/TX2 (BRK16)
RESET
GND
Xin1
33
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Xout1
VDD
C1 C2
VDB
C3 C4
VLCD
VEE
VCPU
P6-0/ADin1 (BRK9)
P6-1/ADin2 (BRK10) P6-2/ADin3 (BRK11) P6-3/ADin4 (BRK12)
P10-0/COM1 P10-1/COM2
16151413121110987654321
A/D (4ch)
N-ch open drain
I/O port (4)
SIO1
Pull-up/pull-down
P5-3/VRout2 P5-2/VRin2 P5-1/VRcom P5-0/VRin1 P4-3/VRout1 (BRK8) P4-2/BUZR (BRK7) P4-1/INTR2/INH (BRK6) P4-0/INTR1 (BRK5) P3-3/PCTRin (BRK4) P3-2/SI1 (BRK3) P3-1/SDIO1/TX1 (BRK2) P3-0/SCK1/RX1 (BRK1) P16-3/S18/Xout2 P16-2/S17/Xin2 P16-1/S16 P16-0/S15
Doubler/regular circuit
Oscillation
circuit
SIO2
N-ch open drain
I/O port (4)
CMOSI/O port (2)
N-ch open drain
I/O port (1)
PLL
Electronic volume
CMOS I/O port (34)
SVFP64
(0.5 mm pitch)
Top - view
LCD driver (1/4 duty, 1/3 or 1/2 bias: 72 segments max)

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Block Diagram
MUTE
MUTE
Port 8
VDD V
LCD
P8-0/VDET (BRK13)
P8-1/SI2/DDCK1 (BRK14)
P8-2/SCK2/RX2 (BRK15)
P8-3/SDIO2/TX2 (BRK16)
DDCK1 VDET
DDCK
Control
VCPU
G-Reg.
RAM
(4 ×512 Words)
Interrupt Stack Reg.
(4 Levels)
DDCK Data
Select
Data Reg (16 bits)
ROM
(16 ×8192 Steps)
VEE
VDB
Port 9
DDCK2 MUTE
P9-0/Tou
t
MUTE/P9-1
P9-2/DDCK2/TES
T
VDD VLCD
IF
Counter
IFin/IN
DDCK
PLL
OSCin
Phase
Comp.
DO1/OT1/P
DO2/OT2/NTin
GND
GND
VPLL
VDB
Reset
RESET
OSC1
Xin1
Xout1
VDD
Doubler
C1
C2
VDB
VEE
(1.5 V)
VEE
Doubler
VDB
C3
C4
VLCD
: N-ch Open drain
Program
Counter
Address Stack Reg.
(16 Levels)
R/WBuf.
Instruction
Decoder
Interrupt
Control
BUZR
VDB
Timer
Up/Down
Counter
Serial
Interface
Ca
Port 6
A/D
Conv.
VEE VDB
VLCD
VR
Port 5
Port 4
Port 3
VDD VLCD
VDD VLCD
OSC
Control
Reset
ALU
CPU
Clock
OSC2
Peripheral
LCD
Driver
Port 10 Port 12 Port 13 Port 15 Port 14 Port 16
VDD
VLCD
OSC2
VDD
OSC2
P6-3/ADin4 (BRK12)
P6-2/ADin3 (BRK11)
P6-1/ADin4 (BRK10)
P6-0/ADin4 (BRK9)
P5-3/VRout2
P5-2/VRin2
P5-1/VRcom
P5-0/VRin1
P4-3/VRout1 (BRK8)
P4-2/BUZR (BRL7)
P4-1/INTR2/INH (BRK6)
P4-0/INTR1 (BRK5)
P3-3/PCTRin (BRK4)
P3-2/S11 (BRL3)
P3-1/SDIO/TX1 (BRK2)
P3-0/SCK1/RX1 (BRK1)
P10-0/COM1 P10-3/COM4
P12-0/S1 P12-3/S4 P13-0/S5 P13-3/S8
P15-0/S13 P15-1/S14
P14-0/S9
P14-3/S12
P16-2/S17/Xin2
P16-3/S18/Xout2
P16-0/S15 P16-1/S16
VLCD
VDD VLCD

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Description of Pin Functions
PIN No. Symbol Pin Name Function and Operation Remarks
64 Xin1
1 Xout1
Crystal oscillator pin Crystal oscillator pins. A reference 75 kHz crystal resonator is
connected to the Xin1 and Xout1 pins.
68 GND
2 VDD
Power-supply pins
Power supply pin for the crystal oscillator
and doubler circuit for the CPU (VDB).
Normally, VDD =0.9 to 1.8 V is applied.
V
DD potential is detected in the 0.850 V to
1.225 V range in 25 mV steps using the
decreased voltage detection circuit. If VDD
potential falls below the voltage being set,
the CPU can be stopped to prevent
incorrect operation.
Note: After reset, the voltage set for the
decreased voltage detection is VDD
=0.85 V. CPU stop function is
enabled.
3 C1 ⎯
4 C2 ⎯
5 VDB
Doubler output pins for
CPU
Doubler output pins for CPU.
The doubler system is the charge-pump
system.
When a doubler clamp is permitted, a
voltage of 2.0 V, 2.5 V or 3.0 V can be
selected. A doubler clock can select either
one of 75 kHz, 37.5 kHz or high-speed
oscillator clock.
Usually, the VDB pin connected to the
capacitor for stabilization (0.1 µF, 10 µF
typ.) supplies voltage for the power supply
of the CPU only ( VCPU). The VDB potential
is supplied to the power supply of the A/D
converter, and a 1.5 V constant-voltage
circuit ( VEE).
The voltage is doubled by the doubler
capacitor between C1 and C2 (0.47 µF
typ.). When the doubler clamp is enabled,
the voltage is doubled below the voltage
being set.
Note: During reset or execution of the
clock stop instruction, the VDB pin is
set to VDD level. The LX pin is L
level for CMOS output, and at high
impedance for open-drain output.
Xout1
Xin1
Rout1
RfXT1
(Xin1, Xout1)
VDD
GND
VDD
VDB

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PIN No. Symbol Pin Name Function and Operation Remarks
6 C3 ⎯
7 C4 ⎯
8 VLCD
Doubler output pin for
LCD driver
Doubler output pin for the LCD driver.
The VLCD pin doubles the VEE pin
voltage to 3 V using the voltage doubler
capacitance between C3 and C4.
The doubled VLCD voltage is supplied to
the I/O port, the power supply of the LCD
driver, and the electronic volume power
supply.
Usually, the stabilizing capacitor (0.1 µF
typ.) is connected between the VLCD pin
and GND. The voltage doubler capacitor
(0.1 µF typ.) is connected between C3 and
C4.
Note: During reset or execution of a clock
stop instruction, the VLCD pin is set
to the VCPU power supply level.
9 VEE
Constant-voltage output
pin
Constant-voltage output pin.
The VEE pin outputs 1.5 V (typ.)
constant-voltage power supply.
The VEE potential is used for the voltage
doubler for the CPU, the clamp function of
the DC/DC converter and the reference
voltage of the A/D converter.
The stabilizing capacitor (0.47 µF typ.) is
connected to the VEE pin.
Note: During reset or execution of the
clock stop instruction, the VEE pin
is at high impedance.
10 VCPU CPU power supply pin
CPU power supply pin.
Normally, 1.2 to 3.6 V is applied. When
memory backup is required, VDB potential
is applied to this pin and this pin’s potential
is held.
In backup state (at execution of the
CKSTP instruction), current dissipation
drops (0.5 µA or less), and the power
supply voltage can be reduced to 0.75 V.
If voltage is applied to this pin, the device
system is reset and the program starts
from address “0” (power-on reset).
Note: To operate the power-on reset, the
power supply should start up in 10
to 100 ms.
Note: To be used with VCPU ≤VLCD.
11~14
P6-0/ADin1
(BRK9)
~
P6-3/ADin4
(BRK12)
I/O port 6
/AD analog input
4-bit N-ch open-drain I/O ports, allowing
input and output to be programmed in 1-bit
units.
If the ports are set as the input state of an
I/O port, these can be set to break pins.
The backup mode can be released by
changing the input state of the break pin in
the backup mode.
I/O ports are N-ch open-drain output. Up to
the VDB voltage can be applied to the AD
input pins.
Pins P6-0 to P6-3 can also be used for
analog input to the built-in 6-bit, 4-channel
A/D converter.
The conversion time of the built-in A/D
converter using the successive
comparison method is 240 µs.
The necessary pin can be programmed to
A/D analog input in 1-bit units.
Up to the doubled voltage VDB (VDD ×2)
can be input as the A/D input voltage.
VLCD
VEE
VCPU
To A/D
converter
Input instruction
Release enables
VDD

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PIN No. Symbol Pin Name Function and Operation Remarks
15 ~ 18 P10-0/COM1
~
P10-3/COM4
I/O port 10
/LCD common output
19 ~ 22 P12-0/S1
~
P12-3/S4
I/O port 12
/LCD segment output
23 ~ 26 P13-0/S6
~
P13-3/S8
I/O port 13
/LCD segment output
27 ~ 30 P14-0/S9
~
P14-3/S12
I/O port 14
/LCD segment output
31 ~ 32 P15-0/S13 /
P15-1/S14
I/O port 15
/LCD segment output
33 ~ 36
P16-0/S15
/Xin2
~
P16-3/S18
/Xout2
I/O port 16
/LCD segment output
/High speed oscillator
22-bit CMOS I/O ports, allowing input and
output to be programmed in 1-bit units.
It can be set as LCD driver output through
programming.
Through a matrix with pins COM1 to
COM4 and S1 to S18, a maximum of 72
segments can be displayed.
When the LCD OFF bit is set to “0”, all of 8
pins of P10-0 to P12-3 become the LCD
output of COM1 to COM4 and S1 to S4.
Other LCD driver pins (S5 to S18) can be
set to the LCD driver output for every pin.
Either of two drive systems can be
selected: 1/4 duty1/2 bias system (frame
frequency: 62.5 kHz) or 1/4 duty 1/3 bias
system (frame frequency: 125 kHz).
When 1/2 bias system is set, common
output is VLCD, 1/2 VLCD and GND, and
segment output is VLCD and GND. When
1/3 bias system is set, common output and
segment output are VLCD, 1/3 VLCD, 2/3
VLCD and GND.
If “1” is set to DISP OFF bit, common
output is non-selected waveform and LCD
display are all switched off.
Pins P16-2 and P16-3 can be set to the
high-speed oscillation pins Xin2 and Xout2
through programming.
A 300-600 kHz ceramic or crystal oscillator
is connected to Xin2 and Xout2 pins.
This oscillation clock can be changed to
CPU operation clock for high-speed CPU
operation. During execution of the clock
stop instruction, oscillation stops.
Note: When changing the CPU clock to a
high-speed oscillator clock, do so
100 ms or more after the
high-speed oscillator is enabled.
Xout2
Xin2
Rout2
RfXT2
(Xin2, Xout2)
VDD
LCD
potential
Input instruction
VDD
VDD

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PIN No. Symbol Pin Name Function and Operation Remarks
37
38
39
40
P3-0/SCK1
/RX1
(BRK1)
P3-1/SDIO1
/TX1
(BRK2)
P3-2/SI1
(BRK3)
P3-3/PCTin
(BRK4)
I/O port 3
/Serial clock input/
output 1/UART input 1
/Serial data input/
output 1/UART output 1
/Serial data input 1
/Pulse counter input
4-bit CMOS I/O Port, allowing input and
output to be programmed in 1-bit units.
When the I/O port is set as input, the
pull-up/pull-down state can be
programmed in 1-bit units.
If set as the input state of an I/O port and
a backup release enable state, the backup
state can be released by changing input
state in the clock stop and the wait modes.
Pins P3-0 to P3-2 are used as input/output
pins of a serial interface circuit.
The serial interface circuit corresponds to
2-wired, 3-wired and UART types. Serial
clock edge, serial clock input/output and
clock frequency are selectable, facilitating
the control of various LSIs and
communication between controllers.
When interruption of a serial interface
circuit is permitted, interruption occurs and
a program is jumped to the 3rd address
after the serial interface operation is
completed.
The P3-3 pin is used as 8-bit pulse
counter input PCTRin. Since it is possible
to select either or both of the rising edge
and falling edge of the input pin, as well as
count-up or count-down, the pin can be
used as an input to a tape count.
Input instruction
Release enables
VDD
VDD
VDD
RIN1

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PIN No. Symbol Pin Name Function and Operation Remarks
41
42
43
P4-0/INTR1
(BRK5)
P4-1/INTR2
INH (BRK6)
P4-2/BUZR
(BRK7)
I/O port 4
/External interrupt
input 1
/External interrupt
input 2
/PLL inhibit input
/Buzzer output
44
P4-3/VRout1 (BRK8)
I/O port 4
/Electronic volume
output1
45
46
47
48
P5-0/VRin1
P5-1/VRcom
P5-2/VRin2
P5-3/VRout2
I/O port 5
/Electronic volume
input1
/Electronic volume
reference voltage input
/Electronic volume
input 2
/Electronic volume
output 2
8-bit CMOS I/O Port, allowing input and
output to be programmed in 1-bit units.
When P4-0 to P4-3 ports are set as the
input and backup release enable states,
the backup state in the clock stop and wait
modes can be released by changing input
state.
Pins P4-0 and P4-1 are also used as
external interrupt input INTR1 and INTR2.
When external interrupt is enabled and a
3-clock pulse of CPU (40 µs: using 75 kHz
oscillator) or longer is input to the INTR1
or INTR2 pin, an interrupt is generated and
a program jumps to the 1st or 2nd
address.
For input interrupt, input logic or
rising/falling edge can be selected for each
pin. The signal input from the INTR1 pin
can measure the pulse width using the
8-bit internal timer. The signal can be used
to detecta remote control signal.
The P4-1 pin is used as the PLL inhibit
input INH .
If the INH pin is set to the PLL inhibit
enable state, the PLL is stopped during “L”
level of the INH pin.
The P4-2 pin is used as the buzzer output.
For the buzzer output it is possible to
select 4 frequencies, 1/1.56/2.08/3 kHz,
with 4 modes: continuous output,
single-shot output, 10-Hz intermittent
output, and 10-Hz intermittent 1-Hz
interval output.
Pins P4-3 and P5-0 to P5-3 are used as
input/output pins for electronic volume.
There are two electronic volume channels.
An I/O port or electronic volume is
selectable for every channel. Attenuation
can be controlled from 0 dB to –78 dB and
∞ dB in 32 steps.
Input instruction
Release enables
(P4-0 to P4-2)
VDD
VDD
Electronic
volume signal
Input instruction
(P5-0 to P5-3)
VDD
VDD
Electronic
volume signal
Input instruction
Release enables
(P4-3)
VDD
VDD

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PIN No. Symbol Pin Name Function and Operation Remarks
49 IFin/IN IF signal input
/Input port
IF signal input pin.
The input frequency is between 0.03 and
12 MHz. A built-in input amp and C
coupling allow small-amplitude operation.
The IF counter can store 20-bit data in
memory. In Manual mode, gate On/Off
control can be performed using an
instruction.
The input pin is used as an input port (IN
port). In this case, the pin is for CMOS
input, so that input clocks can be counted
using the IF counter.
Note: When a pin is set to IF input, the
input is at high impedance in
PLL-off mode.
Note: Since the VPLL power supply is used
in this circuit, an input state cannot
be read when the VPLL power
supply is in the OFF state.
50 VPLL
52 GND (PLL)
PLL
Power supply pin
Pin to which power is applied for the PLL
prescaler.
Normally, the supply voltage to be applied
is from 0.9 to 1.8 V.
Current dissipation becomes low in PLL-off
mode.
Usually, the pin is connected to the VDD
51 OSCin
Local oscillation signal
input
Programmable counter input pin.
It is possible to select the pulse-swallow
type (HF mode) or the direct divide type
(LF mode) through programming.
The localoscillation output of 1 to 30 MHz
is input in the HF mode; 0.5 to 4 MHz in
the LF mode.
A built-in input amp and C coupling allow
small-amplitude operation.
Note: The input is at high impedance in
PLL-off mode.
Rfin2
Input instruction
VPLL
VPLL
VPLL
Rfin1
VPLL

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PIN No. Symbol Pin Name Function and Operation Remarks
53
54
DO1/OT1/P
DO2/OT2/N
/Tin
Phase comparator
output
/output port
/P output
/Tr. Input for LPF
PLL phase comparator output pins.
Tristate output: When the program counter
divider output is higher than the reference
frequency, High level is output; when the
output is lower, Low level; and when they
match, high impedance.
The doubler voltage VDB is used for phase
comparator power supply. The VDB power
supply potential is output for High level.
The DO1 and DO2 pins incorporate 3
types of output resistance (5 kΩ, 50 kΩ,
100 kΩ), which can be changed for each
pin.
The DO2 pin can change output resistance
automatically according to the phase
difference of the PLL. Therefore, lock-up
time is improved.
The DO2 pin can be programmed to
high-impedance or as an output port (OT1,
OT2). The phase comparator charge pump
control signal (P/N), which is used to
configure an external charge pump, can be
output from the DO1/2 pin.
If the phase comparator charge pump
control signal (P/N) is set, when the
program counter divider output is higher
than the reference frequency, P/N is
output atH/L level; when the output is
lower, L/H level; and when they match, L/L
level.
55
56
57
P9-0/Tout
MUTE/P9-1
P9-2/DDCK2
/TEST
I/O port 9
/Tr. Output for LPF
/Mute output
/Clock output 2 for
doubler
/TEST mode input
Pins P9-1 to P9-2 is 2-bit CMOS I/O ports.
The P9-0 pin is a 1-bit N-ch open-drain
I/O, allowing input and output to be
programmed in 1-bit units.
The P9-1 pin is used as the MUTE output.
The MUTE output is usually used for
muting control signal output. The MUTE bit
can be set to “1” through change in the
input of the I/O port input release (BRK)
pin. The MUTE output logic can be set
through programming.
During system reset (RESET =“L”), the
P9-2 pin is pulled down and becomes the
test mode input.
Therefore, the pin is normally used at Low
level or in open state during the reset
condition.
Through programming, it is possible to use
the N-ch FET transistor for low path filter
amplifiers (5.5 V voltage).
As for FET transistors, Tin pin is set as
gate input and Tout pin is set as drain
output.
(DO1/OT1/P, DO2/OT2)
VDB
Rout1
(Tin, Tout)
Note: Tin/Tout setting
VDB
Rout1~4
Tin
Tout
Input instruction
(P9-0)
VDD
Input instruction
(MUTE/P9-1)
VDD
VDD
Input instruction,
VDD
VDD
(P9-2/DDCK2/TEST)
Rin2
Reset

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PIN No. Symbol Pin Name Function and Operation Remarks
58 ~ 61
P8-0/VDET
(BRK13)
P8-1/SI2
/DDCK1
(BRK14)
P8-2/SCK2
/RX2
(BRK15)
P8-3/SDIO2
/TX2
(BRK16)
I/O port 8
/Detected doubler
voltage input
/Serial data input 2
/Doubler clock output 1
/Serial clock input/
output 2
/UART input 2
/Serial clock input/
output 2
/UART output 2
The port 8 is a 4-bit N-ch open-drain I/O
port, allowing controlof ON/OFF for an
output transistor to be programmed in 1-bit
units When an output is set as OFF, the
pin can be used as an input port.
When the backup release enable state is
set, the backup state in the clock stop and
wait modes can be released by a change
in the input or output pin.
The I/O port is N-ch open-drain I/O. Up to
5.5 V can be input to or output from the I/O
port.
This pin is used to configure the switching
regulator for VT.
The voltage is doubled by the doubler
clock output DDCK1 (P8-1) or DDCK2
(P9-2). The divided voltage is input to the
detected doubler voltage VDET pin (P8-0)
to control the doubler clock.
The DDCK1 output is 5.5V N-ch output.
The VT doubled voltage is doubled to 5 V
through the use of an external transistor.
The DDCK2 output is CMOS output The
voltage can be doubled through the use of
an external transistor.
For the doubler clock, it is possible to
select from three types of dividing
frequency: crystal oscillator, high-speed
oscillator and OSCin input.
It is also possible to select through
programming the comparator reference
potential of the VDET input: either 0.75 V
or 1.0 V.
Pins P8-1 to P8-3 are used as serial
interface circuit (SIO) input/output pins.
The serial interface circuit corresponds to
2-wired type, 3-wired type, and UART.
Serial clock edge, serial clock input/output,
and clock frequency can be selected,
facilitating the control of various LSIs and
communication between controllers.
When interrupts of a serial interface circuit
are enabled, an interrupt is generated after
serial interface and the program jumps to
the 3rd address.
62 RESET Reset input
Input pin for system reset signals. The
input uses built-in Schmitt circuit.
RESET takes place while at Low level; at
High level, the program starts from
address “0” after 100 ms standby.
Normally, if voltage is applied to the VCPU
pin, the system is reset (power-on
reset).Therefore, this pin should be set to
High level during operation.
VDD
Detected
doubler
voltage input
Input instruction
Release enables
(P8-0)
VDD
Input instruction
Release enables
(P8-1, P8-3)
VCPU

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Description of Operations
CPU
The CPU consists of a program counter, a stack register, an ALU, program memory, data memory, a G-register, a data
register, a DAL address register, a carry flip-flop (F/F), a judge circuit, interrupt stack register and an interrupt circuit.
1. Program Counter (PC)
The program counter is a 14-bit binary up-counter used to address program memory (ROM). The program counter is
cleared by a system reset and starts from address 0.
The PC is normally incremented by 1 at the execution of each instruction. However, executing a Jump or Call instruction
loads the address specified in the operand of the instruction to the PC.
When an instruction with a skip function (the AIS, SLTI, TMT, RNS instructions, etc.) is executed and the result of the
instruction satisfies the skip condition, the PC is incremented by 2 and the next instruction is skipped.
When an interrupt is received, the system loads the vector address corresponding to the interrupt.
Note: The program memory (ROM) uses the address range 0000H to 1FFFH. Access to addresses outside this
range is prohibited.
Contents of program counter (PC)
Instruction PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
JUMP ADDR1 0
CALL ADDR2 0
DAL ADDR3, (r)
(DAL bit =0)
0 0 0 0
DAL (DA)
(DAL bit =1)
RN, RNS, RNI
When interrupt received
Power-on reset, reset by
RESET pin 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Interrupt source Vector address
INTR1 pin 0001H
INTR2 pin / Timer port 0002H
Serial interface / timer port / decreased voltage detection 0003H
Timer counter 0004H
DAL address register (AR)
Contents of stack register
Vector addresses for interrupt
Instruction operand (ADDR3) Contents of general
register (r)
Instruction operand (ADDR1)
Instruction operand (ADDR2)

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2. Address Stack Register (ASR)
The address stack register consists of 16 ×14 bits. When the subroutine call instruction is executed or an interrupt is
processed, this register stores a value equal to the contents of the program counter +1 (that is, the return address).
Executing the return instruction (RN, RNS, RNI) loads the contents of the address stack register to the program counter.
There are 16 stack levels available and nesting occurs for up to 16 levels. The address stack register is mapped to I/O and
can be read/written by the input and output instructions.
3. ALU
The arithmetic and logic unit (ALU) has binary 4-bit parallel addition/subtraction functions, logical operation,
comparison and multiple bit judge functions. The CPU does not include an accumulator; all operations use the contents of
the data memory directly.
4. Program Memory (ROM)
The program memory consists of 16 bits ×8192 steps and is used for storing programs. The usable address range consists
of 8192 steps between addresses 0000H and 1FFFH.
The program memory divides the 8192 into eight separate steps and consists of pages 0 to 7. The JUMP and CALL
instructions can be freely used throughout all 8192 steps. When the data refer DAL (DAL instruction) is executed, the
program memory addresses 0000H to 03FFH (page 0) are used as data areas; when the indirect refer DAL instruction
(DALR instruction) is executed, the program memory addresses 0000H to 0FFFFH (pages 0 to 3) are used as data areas.
Execution of these instructions enables their 16-bit contents to be loaded into the data register.
Note: Set the data area in program memory to addresses outside the program loop.
Note: The program counter used to set the program memory has 14 bits and can specify a program memory up
to address 3FFF. Do not specify non-existing addresses from 2000H to 3FFFH.
0000H Jump destination address at initialization
0001H INTR1 pin
0002H INTR2 pin / timer port
0003H Serial interface / timer port /
decreased voltage detection
0004H
Interrupt vector
address
Timer counter
Area available to CALL instruction
Vector addresses at interrupt
0000H
Page 0
(1-k steps)
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
0400H
0800H
0C00H
1000H
1400H
1800H
1C00H
1FFFH
Area available to JUMP instruction
ROM
16 bits
Area available to DALR instruction
Area available to DAL instruction

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5. Data Memory (RAM)
The data memory consisting of 4 bits ×512 words is used to store data. These 512 words are expressed in a row address
(4 bits) and column address (4 bits). 348 words (row address =04H to 1FH) within the data memory are addressed
indirectly by the G-register. Therefore it is necessary to specify the row address with the G-register before the data in this
area can be processed.
The addresses 00H to 0FH within the data memory are known as general registers, and can be used simply by specifying
the relevant column address (4 bit). These sixteen general registers can be used for operations and transfers with the data
memory, and may also be used as normal data memories.
Note: The column address (4 bits) that specifies the general register is the register number of the general
register.
Note: All row addresses (00H to 1FH) can be specified indirectly with the G-register.
Note: The LD and ST instructions can directly address 256 words of data memory (row address area 00H to
0FH).
General register
(any register within 000H to 00FH)
The LD and ST instructions can
directly specify row addresses
(00H to 0FH).
Row addresses (04H to
2FH) indirectly specified
b
y
G-re
g
ister
Row address area
00H to 1FH can be
indirectl
y
s
p
ecified.
*
COLUMN ADDRESS: DC
ROW ADDRESS: DR
*
0 1 2 3456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
1D
1E
1F

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6. G-register (G-REG)
The G-register is a 5-bit register used for addressing the row address (DR = 00H to 1FH) of the data memory’s 512 words.
This register is located on the I/O map and accessed by input-and-output instruction. The 5-bit contents can be directly set
by execution of the STIG instruction. (Refer to Register Ports.)
The contents of this register are effective when the MVGD or MVGS instruction is executed, and are not affected
through execution of any other instructions. The contents of the G-register are evacuated to the interrupt stack register when
an interrupt request is generated, and returned to the G-register during execution of the RNI instruction. (Refer to Interrupt
Stack Register.)
7. Data Register (DATA REG)
The data register consists of 16 bits and loads 16 bits of data from any address in the program memory on execution of
the DAL instruction. This register is used as one of the ports. The contents of the register are loaded into the data memory in
4-bit units when the IN1 instruction among the I/O instructions is executed. (Refer to Register Ports.) The contents of data
register are evacuated to the interrupt stack register when an interrupt request is generated, and returned to the data register
during execution of the RNI instruction. (Refer to Interrupt Stack Register.)
8. DAL Address Register (AR)
The DAL address register consists of 14 bits. When the DALR instruction is executed, 16 bits of the data of the program
memory on the address specified by the DAL address register is loaded to the data register. The contents in the DAL address
register are automatically increased by one whenever the DALR instruction is executed.
The contents of the data register can be transferred to the DAL address register by execution of the MVAR instruction.
The DAL address register is located on the I/O map and accessed by input and output instructions.
(Refer to Register Ports.)
9. Carry Flag (Ca Flag)
The carry flag register is set when either Carry or Borrow is issued in the result of calculation instruction execution, and
is reset if neither of these is issued. The flag is located on the I/O map and can be accessed by the input and output
instructions. (Refer to Register Port.)
The contents of a carry flag are changed by execution of only the addition, subtraction, CLT, CLTC, SHRC or RORC
instruction and are not affected by execution of other instructions. The contents of carry flag are evacuated to the interrupt
stack register when an interrupt request is generated, and returned to the carry flag during execution of the RNI instruction.
(Refer to Stack Register.)
10. Interrupt Stack Register (ISR)
This register consists of 4 levels and 26 bits. When an interrupt occurs, the contents of the G-register (5 bits), data select
(4 bits), carry flag (1 bit) and data register (16 bits) are automatically evacuated to the interrupt stack register. After interrupt
processing has been completed, these contents are returned to each register by the RIN instruction. Four levels of stack and
nesting are allowed in the interrupt stack register. (Refer to Interrupt Stack Register.)
11. Judge Circuit (J)
This circuit judges the skip conditions when an instruction with the skip function is executed. The program counter is
increased by two when the skip conditions are satisfied, and the subsequent instruction is skipped. There are 15 instructions
with a wide variety of skip functions available. (Refer to the items marked with a “*” symbol in Instruction Function and
Operation Table.)
12. Interrupt Circuit
An interrupt circuit branches to the various vector addresses according to the demands from peripheral hardware and
performs different types of interrupt processing. (Refer to Interrupt Function.)

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13. Instruction Set Table
A total of 59 instruction sets are available, and all of these are single-word instructions. These instructions are expressed
with a 6-bit instruction code.
00 01 10 11Upper 2 bits
Lower 4 bits 0 1 2 3
0000 0 AI M, I TMTR r, M SLTI M, I
0001 1 AIC M, I TMFR r, M SGEI M, I
0010 2 SI M, I SEQ r, M SEQI M, I
0011 3 SIB M, I SNE r, M SNEI M, I
0100 4 ORIM M, I TMTN M, N
0101 5 ANIM M, I TMT M, N
0110 6 XORIM M, I TMFN M, N
0111 7 MVIM M, I
LD r, M*
JUMP ADDR1
TMF M, N
1000 8 AD r, M IN1 M, C
1001 9 AC r, M IN2 M, C
1010 A SU r, M IN3 M, C
1011 B SB r, M
ST M*, r
OUT1 M, C
1100 C ORR r, M CLT r, M OUT2 M, C
1101 D ANDR r, M CLTC r, M OUT3 M, C
1110 E XORR r, M MVGD r, M DAL ADDR3, r
1111 F MVSR M1, M2 MVGS M, r
CAL ADDR2
SHRC M
RORC M
STIG I*
SKP, SKPN
RN, RNS
WAIT P
CKSTP
XCH M
DI, EI, RNI
DALR
MVAR
NOOP

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14. Instruction Function and Operation Table
(Description of the symbols used in the table)
M Data memory address
Normally, an address within 000H to 03FH in the data memory.
M* Data memory address (256 words)
An address within 000H to 0FFH in the data memory.
(Effective only during execution of the ST or LD instruction)
r General register
An address within 000H to 00FH in the data memory.
PC Program counter (14 bits)
ASP Address stack pointer (14 bits)
ASR Address stack register (14 bits)
ISP Interrupt stack pointer (2 bits)
ISR Interrupt stack register (26 bits)
G G-register (5 bits)
DATA Data register (16 bits)
I Immediate data (4 bits)
I* Immediate data (6 bits, effective only during execution of the STIG instruction)
N Bit position (4 bits)
−All “0”
C Port code number (4 bits)
CN Port code number (4 bits)
RN General register number (4 bits)
ADDR1 Program memory address (13 bits)
ADDR2 Upper 6 bits of program memory address within page 0
AR DAL address register (14 bit)
Ca Carry
CY Carry flag
P Wait condition
b Borrow
IN1~IN3 Ports used during execution of the IN1 to IN3 instructions
OUT1 ~ OUT3 Ports used during execution of the OUT1 to OUT3 instructions
( ) Contents of registers or data memory
[ ] C Contents of the port indicated by the code number C (4 bits)
[ ] Contents of data memory indicated by the register or data memory
[ ] P Contents of program memory (16 bits)
IC Instruction code (6 bits)
* Command with skip function
DC Data memory column address (4 bits)
DR Data memory row address (2 bits)
DR* Data memory row address
(4 bits, effective only during execution of the ST or LD instruction)
(M) b0 ~ (M) b3 Bit data of data memory contents (1 bit)

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Machine Language (16 Bits)
Instruction
Set
Mnemonic Skip
Functio n Function Operation
IC
(6 Bits)
A
(2 Bits)
B
(4 Bits)
C
(4 Bits)
AI M, I
Add immediate data
to memory M ←(M) +I 000000 DR DC I
AIC M, I
Add immediate data
to memory with
carry
M ←(M) +I +ca 000001 DR DC I
AD r, M Add memory to
general register r ←(r) +(M) 001000 DR DC RN
Addition instruction
AC r, M
Add memory to
general register with
carry
r ←(r) +(M) +ca 001001 DR DC RN
SI M,I Subtract immediate
data from memory M ←(M) −I 000010 DR DC I
SIB M, I
Subtract immediate
data from memory
with borrow
M ←(M) −I −b 000011 DR DC I
SU r, M
Subtract memory
from general
register
r ←(r) −(M) 001010 DR DC RN
Subtraction instruction
SB r, M
Subtract memory
from general
register with borrow
r ←(r) −(M) −b 001011 DR DC RN
SLTI M, I *
Skip if memory is
less than immediate
data
Skip if (M) <I 110000 DR DC I
SGEI M, I *
Skip if memory is
greater than or
equal to immediate
data
Skip if (M)
>
=
I 110001 DR DC I
SEQI M, I *
Skip if memory is
equal to immediate
data
Skip if (M) =I 110010 DR DC I
SNEI M, I *
Skip if memory is
not equal to
immediate data
Skip if (M) ≠I 110011 DR DC I
SEQ r, M *
Skip if general
register is equal to
memory
Skip if (r) =(M) 010010 DR DC RN
SNE r, M *
Skip if general
register is not equal
to memory
Skip if (r) ≠(M) 010011 DR DC RN
CLT r, M
Set carry flag if
general register is
less than memory,
or reset if not
(CY) ← 1 if (r) <(M)
or
(CY) ← 0 if (r)
>
=
(M)
011100 DR DC RN
Compare instruction
CLTC r, M
Set carry flag if
general register is
less than memory
with carry or reset if
not
(CY) ←1 if (r) <(M) +
(ca) or
(CY) ← 0 if (r)
>
=
(M) +
(Ca)
011101 DR DC RN

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Machine Language (16 Bits)
Instruction
Set
Mnemonic Skip
Functio n Function Operation
IC
(6 Bits)
A
(2 Bits)
B
(4 Bits)
C
(4 Bits)
LD r, M*
Load memory to
general register r ←(M*) 0101 DR* (4 bits) DC RN
ST M*, r Store memory to
general register M*←(r) 0110 DR* (4 bits) DC RN
MVSR M1, M2
Move memory to
memory in same
row
(DR, DC1) ←(DR,
DC2) 001111 DR DC1 DC2
MVIM M, I Move immediate
data to memory M ←I 000111 DR DC I
MVGD r, M
Move memory to
destination memory
referring to
G-register and
general register
[(G), (r)] ←(M) 011110 DR DC RN
MVGS M, r
Move source
memory referring to
G-register and
general register to
memory
(M) ←[(G), (r)] 011111 DR DC RN
STIG I*
Move immediate
data to G-register G ←I*111111 I*0010
Transfer instruction
MVAR
Move DATA register
data to DAL
address register
AR←(DATA) 111111 ⎯⎯1001
IN1 M, C Input IN1 port data
to memory M ←[IN1] C 111000 DR DC CN
OUT1 M, C
Output contents of
memory to OUT1
port
[OUT1] C ←(M) 111011 DR DC CN
IN2 M, C Input IN2 port data
to memory M ←[IN2] C 111001 DR DC CN
OUT2 M, C
Output contents of
memory to OUT2
port
[OUT2] C ←(M) 111100 DR DC CN
IN3 M, C Input IN3 port data
to memory M ←[IN3] C 111010 DR DC CN
I/O instruction
OUT3 M, C
Output contents of
memory to OUT3
port
[OUT3] C ←(M) 111101 DR DC CN
ORR r, M
Logical OR of
general register and
memory
r ←(r) ∨(M) 001100 DR DC RN
ANDR r, M
Logical AND of
general register and
memory
r ←(r) ∧(M) 001101 DR DC RN
ORIM M, I
Logical OR of
memory and
immediate data
M ←(M) ∨I 000100 DR DC I
ANIM M, I
Logical AND of
memory and
immediate data
M ←(M) ∧I 000101 DR DC I
XORIM M, I
Logical exclusive
OR of memory and
immediate data
M ←(M) ∀I 000110 DR DC I
Logical Operation instruction
XORR r, M
Logical exclusive
OR of general
register and
memory
r ←(r) ∀(M) 001110 DR DC RN