Ublox NORA-W30 Series Quick setup guide

UBX-22021119 - R02
C1-Public www.u-blox.com
NORA-W30 series
Stand-alone dual-band Wi-Fi and Bluetooth modules
System integration manual
Abstract
This manual provides a functional overview combined with best-practice design guidelines for
integrating NORA-W30 series stand-alone, dual-band Wi-Fi and Bluetooth Low Energy modules in
customer applications. It also describes open CPU application development solutions using the
Realtek SDK. The multi-radio modules are ultra-compact, cost-efficient, and designed in the NORA
form factor for a wide range of industrial applications. The module series also includes variants with
or without an internal antenna.

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Document information
Title
NORA-W30 series
Subtitle
Stand-alone dual-band Wi-Fi and Bluetooth modules
Document type
System integration manual
Document number
UBX-22021119
Revision and date
R02
24-Mar-2023
Disclosure restriction
C1-Public
Product status
Corresponding content status
Functional sample
Draft
For functional testing. Revised and supplementary data will be published later.
In development /
Prototype
Objective specification
Target values. Revised and supplementary data will be published later.
Engineering sample
Advance information
Data based on early testing. Revised and supplementary data will be published later.
Initial production
Early production information
Data from product verification. Revised and supplementary data may be published later.
Mass production /
End of life
Production information
Document contains the final product specification.
This document applies to the following products:
Product name
Document status
Comment
NORA-W301
Objective specification
NORA-W306
Objective specification
☞For information about the related hardware, software, and status of listed product types, refer to
the data sheet [2].
u--blox or third parties may hold intellectual property rights in the products, names, logos, and designs included in this
document. Copying, reproduction, or modification of this document or any part thereof is only permitted with the express
written permission of u-blox. Disclosure to third parties is permitted for clearly public documents only.
The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability, and fitness for a particular
purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent
documents, visit www.u blox.com.
Copyright © u-blox AG.

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Contents
Document information ......................................................................................................................2
Contents ..............................................................................................................................................3
1Module overview ..........................................................................................................................6
1.1 Module architecture .......................................................................................................................................... 6
1.1.1 Block diagram ............................................................................................................................................. 6
1.2 Pin layout............................................................................................................................................................... 7
1.3 Pin assignment ................................................................................................................................................... 7
1.4 Pin multiplexing.................................................................................................................................................10
2Module integration ................................................................................................................... 12
2.1 CPU and memory..............................................................................................................................................12
2.2 Power modes......................................................................................................................................................12
2.2.1 Power on.....................................................................................................................................................12
2.2.2 Tickless.......................................................................................................................................................12
2.2.3 Sleep ............................................................................................................................................................12
2.2.4 Deep sleep..................................................................................................................................................12
2.3 Wake sources ....................................................................................................................................................12
2.4 Power management.........................................................................................................................................13
2.4.1 SPS, digital I/O and system supply (VDD) ........................................................................................13
2.4.2 Power supply configuration..................................................................................................................13
2.4.3 VDD application circuits ........................................................................................................................13
2.5 Module reset .....................................................................................................................................................14
2.5.1 nRESET pin................................................................................................................................................14
2.6 Bootstrap pins...................................................................................................................................................14
2.7 Real-time clock..................................................................................................................................................14
2.7.1 External low-frequency clock source .................................................................................................14
2.8 Antenna integration ........................................................................................................................................15
2.8.1 External RF antenna interface.............................................................................................................15
2.8.2 Internal antenna.......................................................................................................................................15
2.9 Data interfaces..................................................................................................................................................15
2.9.1 Universal Asynchronous Receiver Transmitter (UART) ..............................................................16
2.9.2 Serial Peripheral Interface (SPI) ..........................................................................................................16
2.9.3 Inter-IC (I2C) interface............................................................................................................................16
2.9.4 Inter-IC Sound (I2S).................................................................................................................................16
2.9.5 Universal Serial Interface (USI)............................................................................................................17
2.10Digital interfaces ..............................................................................................................................................17
2.10.1 Pulse Width Modulation (PWM)..........................................................................................................17
2.10.2 Key-scan.....................................................................................................................................................17
2.10.3 Quadrature Decoder (Q-Decoder or QDEC)......................................................................................17
2.11Analog ..................................................................................................................................................................17
2.12Debug ...................................................................................................................................................................17

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2.13No-connect pins (n/c)......................................................................................................................................17
2.14Ground (GND) pins............................................................................................................................................17
3Design-in..................................................................................................................................... 18
3.1 Overview ..............................................................................................................................................................18
3.2 Antenna interface ............................................................................................................................................18
3.2.1 RF transmission line design (NORA-W301)....................................................................................18
3.2.2 Antenna design (NORA-W301)...........................................................................................................20
3.2.3 On-board antenna design (NORA-W306) ........................................................................................23
3.3 Data communication interfaces ..................................................................................................................25
3.3.1 Asynchronous serial interface (UART) design................................................................................25
3.4 General high-speed layout guidelines ........................................................................................................25
3.4.1 Considerations for schematic design and PCB floor-planning..................................................25
3.4.2 Component placement ..........................................................................................................................25
3.4.3 Layout and manufacturing...................................................................................................................25
3.5 Module footprint and paste mask...............................................................................................................26
3.6 Thermal guidelines...........................................................................................................................................27
3.7 ESD guidelines...................................................................................................................................................27
3.8 Design-in checklists.........................................................................................................................................28
3.8.1 Schematic checklist................................................................................................................................28
3.8.2 Layout checklist.......................................................................................................................................28
4Open CPU software .................................................................................................................. 29
4.1 Wi-Fi MAC and Bluetooth device addresses and other production data ........................................29
4.2 Realtek SDK .......................................................................................................................................................29
4.2.1 FreeRTOS...................................................................................................................................................29
4.2.2 SDK setup ..................................................................................................................................................29
4.2.3 GCC setup ..................................................................................................................................................29
4.2.4 IAR Workbench setup.............................................................................................................................30
4.2.5 Board configuration................................................................................................................................31
5Handling and soldering ............................................................................................................ 32
5.1 ESD handling precautions .............................................................................................................................32
5.2 Packaging, shipping, storage, and moisture preconditioning ............................................................32
5.3 Reflow soldering process ...............................................................................................................................33
5.3.1 Cleaning......................................................................................................................................................34
5.3.2 Other notes................................................................................................................................................34
6Regulatory compliance ............................................................................................................ 35
6.1 General requirements .....................................................................................................................................35
6.2 FCC/ISED End-product regulatory compliance (pending)....................................................................35
6.2.1 Referring to the u-blox FCC/ISED certification ID..........................................................................36
6.2.2 Obtaining own FCC/ISED certification ID .........................................................................................36
6.2.3 Antenna requirements...........................................................................................................................37
6.2.4 Software configuration and control...................................................................................................37
6.2.5 Operating frequencies ...........................................................................................................................38

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6.2.6 End product labeling requirements....................................................................................................39
6.3 European Union regulatory compliance (pending) .................................................................................40
6.3.1 Safety standard.......................................................................................................................................40
6.3.2 ETSI Equipment classes........................................................................................................................40
6.4 Great Britain regulatory compliance (pending) .......................................................................................41
6.4.1 UK Conformity Assessed (UKCA) .......................................................................................................41
6.5 Japan radio equipment compliance (pending) ........................................................................................41
6.5.1 Compliance statement ..........................................................................................................................41
6.5.2 End product labelling requirement ....................................................................................................41
6.5.3 End product user manual requirement.............................................................................................41
6.6 NCC Taiwan compliance (pending).............................................................................................................42
6.6.1 Taiwan NCC warning statement.........................................................................................................42
6.6.2 Labeling requirements for end product ............................................................................................42
6.7 KCC South Korea compliance (pending) ...................................................................................................42
6.8 Brazil compliance (pending)..........................................................................................................................43
6.9 Australia and New Zealand regulatory compliance (pending)............................................................43
6.10South Africa regulatory compliance (pending)........................................................................................44
6.11Bluetooth qualification (pending)................................................................................................................44
7Product testing ......................................................................................................................... 45
7.1 u-blox in-line production test........................................................................................................................45
7.2 OEM manufacturer production test...........................................................................................................46
7.2.1 “Go/No go” tests for integrated devices...........................................................................................46
Appendix ........................................................................................................................................... 47
AGlossary ...................................................................................................................................... 47
BAntenna references.................................................................................................................. 49
B.1 NORA-W301 U.FL reference design...........................................................................................................49
B.2 Approved antennas..........................................................................................................................................49
B.2.1 Antenna accessories ..............................................................................................................................49
B.2.2 Pre-approved antenna list.....................................................................................................................50
Related documentation.................................................................................................................. 52
Revision history ............................................................................................................................... 52
Contact.............................................................................................................................................. 52

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1Module overview
NORA-W30 series are small, stand-alone dual-band Wi-Fi and Bluetooth Low Energy microcontroller
unit (MCU) modules, perfect for integrating wireless connectivity in end products.
With Wi-Fi 4 (802.11a/b/g/n) in the 2.4 and 5 GHz bands it can be a Wi-Fi station connecting to a
remote access point or act as an access point. NORA-W30 is Bluetooth 5 qualified and can assume
peripheral or central roles, or both simultaneously. It can be a GATT client or server.
The module embeds a dual-core MCU with a powerful Arm Cortex-M33 compatible processor for the
main application and an Arm Cortex-M23 compatible core for low power operation.
The NORA-W30 series include hardware security features like secure boot, trusted execution
environment with Arm TrustZone™, encrypted flash, protection of debug port, and a crypto
acceleration engine. Wireless communication is secure with WPA2/WPA3 authentication, TLS
1.2/1.3 encryption, Bluetooth LE secure connection pairing, and HTTPS.
NORA-W30 modules have the same size and position of critical pads and interfaces as other NORA
modules. This offers maximum flexibility for the development of similar end-devices with different
radio technologies. The modules support operation in an extended temperature range of –40°C to
+105°C and are qualified for professional grade applications.
1.1 Module architecture
NORA-W30 series are the first-generation u-blox modules based on the Realtek RTL8720DF chip.
Module variants allow developers to select either an external antenna with NORA-W301 or an on-
module antenna with NORA-W306.
These compact modules include the MCU, flash memory, crystal, and other components for
matching, filtering, antenna, decoupling, and antenna operation.
The two variants of NORA-W30 series are described in Table 1.
Variant / Ordering code
Antenna configuration
Antenna type
NORA-W301-00B
RF_ANT0: 2.4 GHz / 5 GHz Wi-Fi, 2.4 GHz Bluetooth LE
Antenna pad
NORA-W306-00B
Combined 2.4 GHz / 5 GHz Wi-Fi, 2.4 GHz Bluetooth LE
Single embedded PCB antenna
Table 1: Supported configurations of the NORA-W30 series
1.1.1 Block diagram
Figure 1: NORA-W30 series block diagram

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1.2 Pin layout
Figure 2: NORA-W301/W306 pin layout (top view)
☞All grey pins are ground (VSS).
☞Several pins are used for bootstrap settings. It is important that these signals, shown in Table 2
and Table 7, have the correct state during startup. See also Module reset.
1.3 Pin assignment
No
Name
I/O1
Bootstrap
Alternate functions
A1
VSS
Power
A2
n/c
-
A3
n/c
-
A4
n/c
-
A5
PA[7]
I/O, PU
UART_DL
UART_LOG_TXD, ANT_SEL_P
A6
PA[8]
I/O, PU
UART_LOG_RXD, ANT_SEL_N
A7
VDD
Power
A8
VDD
Power
A9
VSS
Power
B1
PA[30]
I/O, PU
SPS_SEL
HS_USI_SPI_CLK, HS_PWM7, LP_PWM1, EXTBT_UART_RTS
B2
VSS
Power
B3
PA[28]
I/O
LP_UART_CTS, HS_USI_SPI_CS, HS_PWM6, LP_PWM0, RREF, BT_CK
1
I/O notations: I=Input only, I/O=Input or Output, PU=Pull Up, AI=Analog Input, n/c=Not Connected

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No
Name
I/O1
Bootstrap
Alternate functions
B4
n/c
-
B5
n/c
-
B6
n/c
-
B7
VDD
Power
B8
VSS
Power
B9
n/c
-
C1
PA[26]
I/O
LP_UART_TXD, HS_USI_SPI_MISO, IR_RX, LP_I2C_SDA, HS_PWM5, LP_PWM5,
HSDP, BT_ACT
C2
PA[25]
I/O
LP_UART_RXD, HS_USI_SPI_MOSI, IR_TX, LP_I2C_SCL, HS_PWM4, LP_PWM4,
HSDM, MBOX_I2C_INT
C4
n/c
-
C5
n/c
-
C6
n/c
-
C8
PB[23]
I/O
LP_TIM5_TRIG, SPI_DATA2, SD_D1, HS_PWM15, LP_PWM3, I2S_MCLK,
QDEC_PHA, EXT_32K
C9
n/c
-
D1
n/c
-
D2
n/c
-
D3
n/c
-
D7
n/c
-
D8
PB[1]
I/O, AI
LP_UART_TXD, ANT_SEL_N, BT_STE, EN_EXLNA, HS_TIM4_TRIG
D9
n/c
-
E1
n/c
-
E2
n/c
-
E3
n/c
-
E4
VSS
Power
E5
VSS
Power
E7
n/c
-
E8
PB[2]
I/O, AI
LP_UART_RXD, ANT_SEL_P, PCM_CLK, EN_EXPA, HS_TIM5_TRIG
E9
PB[22]
I/O
LP_TIM4_TRIG, SPI_DATA3, SD_D0, HS_PWM14, LP_PWM2, I2S_SD_RX,
QDEC_PHB, EXTBT_UART_CTS
F1
n/c
-
F2
n/c
-
F3
n/c
-
F4
VSS
Power
F5
VSS
Power
F7
n/c
-
F8
PB[21]
I/O
HS_USI_UART_RXD, HS_UART0_RTS, SPI0_CS, SPI_CLK, HS_USI_I2C_SDA,
SD_CLK, HS_PWM13, LP_PWM1, I2S_WS, QDEC_IDX
F9
PB[20]
I/O
HS_USI_UART_TXD, HS_UART0_CTS, SPI0_CLK, SPI_DATA0, HS_USI_I2C_SCL,
SD_CMD, HS_PWM12, LP_PWM0, I2S_CLK
G1
n/c
-
G2
n/c
-
G3
n/c
-
G4
n/c
-
G5
n/c
-
G7
n/c
-

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No
Name
I/O1
Bootstrap
Alternate functions
G8
PB[19]
I/O
HS_UART0_TXD, HS_USI_UART_CTS, SPI0_MISO, SPI_DATA1, SD_D3,
HS_PWM11, LP_PWM5, SWD_DATA, I2S_SD_TX0
G9
PB[18]
I/O
HS_UART0_RXD, HS_USI_UART_RTS, SPI0_MOSI, SPI_CS, SD_D2, HS_PWM10,
LP_PWM4, SWD_CL
H1
n/c
-
H2
PA[27]
I/O, PU
BL_EN
SWD_DATA (Default), LP_UART_RTS, WLAN_ACT
H3
n/c
-
H7
n/c
-
H8
PA[15]
I/O
LP_UART_CTS, SPI1_CS, ANT_SEL_P, BT_WAKE_HOST, KEY_ROW2,
KEY_COL6
H9
PA[14]
I/O
LP_UART_RTS, SPI1_CLK, I2S_SD_TX2, ANT_SEL_N, BT_DIS, KEY_ROW2
J1
n/c
-
J2
PB[3]
I/O, AI
SWD_CLK (Default), PCM_SYNC
J3
nRESET
I, PU
J4
n/c
-
J5
n/c
-
J7
n/c
-
J8
PA[13]
I/O
LP_UART_RXD, SPI1_MISO, HS_PWM1, LP_PWM1, I2S_SD_TX1, ANT_SEL_P,
GRANT_BT_N, EN_EXPA, KEY_ROW1
J9
PA[12]
I/O
LP_UART_TXD, SPI1_MOSI, HS_PWM0, LP_PWM0, I2S_MCLK, ANT_SEL_N,
GRANT_BT, EN_EXLNA, KEY_ROW0
K1
n/c
-
K2
VSS
Power
K3
VSS
Power
K5
VSS
Power
K7
VSS
Power
K8
VSS
Power
K9
ANT
I/O
L1
VSS
Power
L9
VSS
Power
M1
VSS
Power
M2
VSS
Power
M8
VSS
Power
M9
VSS
Power
Table 2: NORA-W30 pin assignment
Peripheral assignments are performed through the e-fuse and application loaded onto the module.
When a pin is assigned to one function, it cannot be used for another function. For functions not
selected through the eFuse, changing assignments on-the-fly is available. Assignments cannot
conflict with other existing assignments (e.g., LP_UART and LP_I2C can use the same pins. Both
functions cannot be active at the same time unless the LP_UART is assigned to an alternate set of
pins.)
☞Alternate pin function descriptions are defined in the NORA-W30 data sheet [2]. Only certain
functions may be enabled at one time. See the Table 3.

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1.4 Pin multiplexing
Only certain functions may be enabled at one time. Table 3 describes the pin multiplexing options.
Table 3: Pin multiplexing table
UBXDOC-39674697-1341 C2-Restricted NORA-W30 GPIO pin-mux
Port Name Bootstrap Internal pull Module pull FUNC_ID0 FUNC_ID1 FUNC_ID2 FUNC_ID3 FUNC_ID4 FUNC_ID5 FUNC_ID6 FUNC_ID7 FUNC_ID8 FUNC_ID9 FUNC_ID10 FUNC_ID11 FUNC_ID12
FUNC_ID1
4
FUNC_ID1
5FUNC_ID18 FUNC_ID20 FUNC_ID2 1FUNC_ID22 FUNC_ID23 FUNC_ID28
FUNC_ID2
9
FUNC_ID30
FUNC_ID3
1
default
RTK9720DF
pull
gpio UART DATA
LOG UART
RTS/CTS
SPI RTC IR SPI f lash I2C SDIO HS pwm LP pwm SWD I2S/DMIC USB
HEADPHO
NE
Wif ionly
RFE control
Ext. BT
Combo
RFE
control
HS timer trig Debug Port Ext32K
key scan
ROW
key scan
COL
WAKEUP default function
shutdown3
3 group
PA[7] uart_download
Internal UP 50 kΩ pull-up PA[7] UART_LOG_TXD ANT_SEL_P PA[7] 5
PA[8]
Internal UP PA[8] UART_LOG_RXD ANT_SEL_N PA[8] 5
PA[12] icfg0
PA[12] LP_UART_TXD SPI1_MOSI HS_PWM0 LP_PWM0 I2S_MCLK ANT_SEL_N GRANT_BT EN_EXLNA KEY_ROW0 LGPIO[0] PA[12] 2
PA[13] icfg1
EfusePullCtrl0 PA[13] LP_UART_RXD SPI1_MISO HS_PWM1 LP_PWM1 I2S_SD_TX1 ANT_SEL_P GRANT_BT_N EN_EXPA KEY_ROW1 LGPIO[1] PA[13] 2
PA[14] icfg2
PA[14] LP_UART_RTS SPI1_CLK I2S_SD_TX2 ANT_SEL_N BT_DIS RTC_OUT KEY_ROW2 LGPIO[2] PA[14] 2
PA[15] icfg3
EfusePullCtrl1 PA[15] LP_UART_CTS SPI1_CS ANT_SEL_P BT_WAKE_HOST RTC EXT_32K KEY_ROW3 KEY_COL6 LGPIO[3] PA[15] 2
PA[25]
EfusePullCtrl2 PA[25] LP_UART_RXD HS_USI_SPI_MOSI IR_TX LP_I2C_SCL HS_PWM4 LP_PWM4 HSDM MBOX_I2C_INT wlmac_dbggpio[0] KEY_COL1 PA[25] 2
PA[26]
PA[26] LP_UART_TXD HS_USI_SPI_MISO IR_RX LP_I2C_SDA HS_PWM5 LP_PWM5 HSDP BT_ACT wlmac_dbggpio[1] KEY_COL0 PA[26] 2
PA[27] normal_mode_sel
Internal UP 50 kΩ pull-up PA[27] LP_UART_RTS SWD_DATA WLAN_ACT wlmac_dbggpio[2]
SWD_DATA when efuse
enable
5
PA[28]
EfusePullCtrl3 PA[28] LP_UART_CTS HS_USI_SPI_CS HS_PWM6 LP_PWM0 RREF BT_CK wlmac_dbggpio[3] PA[28] 5
PA[30] sps_sel
External UP 10 kΩ pull-up PA[30] HS_USI_SPI_CLK HS_PWM7 LP_PWM1 EXTBT_UART_RTS wlmac_dbggpio[4] PA[30] 5
PB[1]
EfusePullCtrl4 PB[1] LP_UART_TXD DMIC_CLK ANT_SEL_N BT_STE EN_EXLNA HS_TIM4_TRIG wlmac_dbggpio[5] PB[1] 5
PB[2]
PB[2] LP_UART_RXD DMIC_DATA ANT_SEL_P PCM_CLK EN_EXPA HS_TIM5_TRIG wlmac_dbggpio[6] PB[2] 5
PB[3]
PB[3] SWD_CLK PCM_SYNC wlmac_dbggpio[7]
SWD_CLK when efuse
enable
5
PB[18]
PB[18] HS_UART0_RXD HS_USI_UART_RTS SPI0_MOSI SPI_CS SD_D2 HS_PWM10 LP_PWM4 SWD_CLK
SWD_CLK when efuse
enable, or SD_D2 when
efuse enable SDIO
1
PB[19]
EfusePullCtrl6 PB[19] HS_UART0_TXD HS_USI_UART_CTS SPI0_MISO SPI_DATA1 SD_D3 HS_PWM11 LP_PWM5 SWD_DATA I2S_SD_TX0
SWD_DATA when efuse
enable,or SD_D3 when
efuse enable SDIO
1
PB[20]
PB[20] HS_USI_UART_TXD HS_UART0_CTS SPI0_CLK SPI_DATA0 HS_USI_I2C_SCL SD_CMD HS_PWM12 LP_PWM0 I2S_CLK
SD_CMD when efuse
enable SDIO
1
PB[21]
PB[21] HS_USI_UART_RXD HS_UART0_RTS SPI0_CS SPI_CLK HS_USI_I2C_SDA SD_CLK HS_PWM13 LP_PWM1 I2S_WS QDEC_IDX
SD_CLK when efuse
enable SDIO
1
PB[22]
EfusePullCtrl7 PB[22] LP_TIM4_TRIG IR_RX SPI_DATA3 SD_D0 HS_PWM14 LP_PWM2 I2S_SD_RX QDEC_PHB EXTBT_UART_CTS wlmac_dbggpio[8]
SD_D0 when efuse enable
SDIO
1
PB[23]
PB[23] LP_TIM5_TRIG IR_TX SPI_DATA2 SD_D1 HS_PWM15 LP_PWM3 I2S_MCLK QDEC_PHA EXT_32K wlmac_dbggpio[9]
SD_D1 when efuse enable
SDIO
1

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Table 4 describes the pin multiplexing for Always ON (AON) power domain.
Table 4: AON pin multiplexing
Table 5 describes the external I2S multiplexing pins.
Symbol
Type
Pin name
Function ID
Description
I2S_MCLK
O
PB[12]
12
External I2S main clock
PB[23]
12
I2S_CLK
O
PB[20]
12
External I2S clock
I2S_WS
O
PB[21]
12
External I2S Word Select
I2S_SD_TX0
O
PB[19]
12
External I2S data Tx0
I2S_SD_TX1
O
PA[13]
12
External I2S data Tx1
I2S_SD_TX2
O
PA[14]
12
External I2S data Tx2
I2S_SD_RX
I
PB[22]
12
External I2S data Rx
Table 5: External I2S pin multiplexing
UBXDOC-39674697-1341 C2-Restricted NORA-W30 AON pin-mux
Port Name Trap FUNC_ID0 FUNC_ID28 FUNC_ID29 FUNC_ID30 FUNC_ID31
gpio Ext32K
key scan
row
key scan
col wakeup gpio port name default pull
PA[7] uart_download
PA[7] UP
PA[8]
PA[8] UP
PA[12] icfg0
GPIOC_LP[0] KEY_ROW0 LGPIO[0] GPIOC_LP[0] PA[12]
PA[13] icfg1
GPIOC_LP[1] KEY_ROW1 LGPIO[1] GPIOC_LP[1] PA[13]
PA[14] icfg2
GPIOC_LP[2] RTC_OUT KEY_ROW2 LGPIO[2] GPIOC_LP[2] PA[14]
PA[15] icfg3
GPIOC_LP[3] RTC EXT_32K KEY_ROW3 KEY_COL6 LGPIO[3] GPIOC_LP[3] PA[15]
PA[25]
GPIOC_LP[10] KEY_COL1 LGPIO[2] GPIOC_LP[10] PA[25]
PA[26]
GPIOC_LP[11] KEY_COL0 LGPIO[3] GPIOC_LP[11] PA[26]

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2Module integration
2.1 CPU and memory
NORA-W30 series modules embed a dual-core MCU with a powerful Arm Cortex-M33 compatible
processor for the main application (KM4 core) and an Arm Cortex-M23 compatible core for low power
operation (KM0 core). The open CPU architecture allows custom, advanced applications running on
the CPU.
The NORA-W30 architecture includes the following memories:
•RAM –main core: 512 kB
•RAM –low-power core: 64 kB
•Flash –accessible to both cores: 4 MB
•512-byte eFuse (non-erasable memory) for MAC addresses, Wi-Fi calibration, module
configuration, flash encryption, and chip ID
2.2 Power modes
NORA-W30 series modules are power efficient devices capable of operating in different power saving
modes and configurations. Different sections of the module can be powered off when they are not
needed, and complex wake up events can be generated from different external and internal inputs.
For more information about power modes, see the Realtek RTL8720DF data sheet [3] and application
note [5].
2.2.1 Power on
This is the normal operating mode when running applications.
2.2.2 Tickless
Tickless is a FreeRTOS™low-power feature which halts the CPU when no task is scheduled.
2.2.3 Sleep
The dual-core design of KM0 and KM4 is largely for saving power. KM4 is used for the main application
while KM0 is used for power-save, Wi-Fi firmware, and power/clock control. There are two sleep
modes, clock-gating (CG) and power-gating (PG). CG will disable the generation or routing of certain
clocks. PG will turn off select power domains of the NORA-W30 module. All RAM is retained.
2.2.4 Deep sleep
Deep sleep mode enables power only to the AON power domain (deep sleep wake sources). MCU clocks
are turned off. Real-time clock (RTC) is on. 1 kB of RAM is retained.
See also Real-time clock.
2.3 Wake sources
NORA-W30 can be awakened from sleep mode by the following sources:
•Analog comparator or ADC
•Low-power I2C address match (I2C slave mode only)
•Low-power or high-speed UART activity
•Brown-out detector
•Wi-Fi beacon interval

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•GPIO input
•Timers
NORA-W30 can be awakened from deep sleep mode by the following sources:
•Power-down event
•Real-time clock
•Key press
•Low-power timers
•GPIO input
2.4 Power management
2.4.1 SPS, digital I/O and system supply (VDD)
NORA-W30 series have a single power supply input –VDD –which is also the I/O voltage reference.
Nominal voltage is 3.3 VDC ±10%.
2.4.2 Power supply configuration
The RTL8720DF within NORA-W30 series can be configured for operating the MCU cores in switch
mode power supply (SMPS, or SPS) or low drop-out (LDO) linear mode. Default is SPS. LDO may be
selected by changing the strapping, though is not recommended for normal operation. See also
Bootstrap pins.
2.4.3 VDD application circuits
The power for NORA-W30 series modules is applied through the VDD pins. These supplies are taken
from either of the following sources:
•Switch Mode Power Supply (SMPS)
•Low dropout linear regulator (LDO)
An SMPS is the ideal design choice when the available primary supply source is significantly higher
than the operating supply voltage of the module. This offers the best power efficiency for the
application design and minimizes the amount of current drawn from the main supply source.
⚠When taking VDD supplies from an SMPS make sure that the AC ripple voltage is kept as low as
possible at the switching frequency. Design layouts should focus on minimizing the impact of any
high-frequency ringing.
Use an LDO linear regulator for primary VDD supplies that have a relatively low voltage. As LDO
regulators dissipate power linearly related to the step-down voltage, LDOs are not recommended for
step down of high voltages.
DC-DC efficiency should be regarded as a trade-off between the active and idle duty cycles of an
application. Although some DC-DC devices achieve high efficiency at light loads, these efficiencies
typically degrade as soon as the idle current drops below a few milliamps. This can have a negative
impact on the life of a battery.
If decoupling capacitors are needed on the supply rails, it is best practice to position these as close as
possible to the NORA-W30 series module. The power routing of some host system designs makes
decoupling capacitance unnecessary.
For electrical specifications, see also the appropriate NORA-W30 series data sheet [2].

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2.5 Module reset
NORA-W30 series modules can be reset (rebooted) with a low-level input on the nRESET pin. The logic
level of this pin is normally set high using an internal pull-up resistor. The low-level input triggers a
“hardware reset” of the module. The nRESET signal should be driven by an open drain, open collector,
or contact switch. The chip works at the minimum power when nRESET is low (off). Table 6 shows the
reset pin characteristics.
2.5.1 nRESET pin
Pin name
Parameter
Min
Typ
Max
Unit
nRESET
Low-level input
0
0.2*VDD
V
Internal pull-up resistance
10
kΩ
tSTARTUP
Startup time after release of reset
203.1
203.5
ms
tRESET
Minimum nRESET low pulse
1
1
ms
Table 6: nRESET pin characteristics
2.6 Bootstrap pins
Several module pins related to the boot configuration can be configured as shown in Table 7. Internal
pull-up values are the default states for NORA-W30 on boot.
⚠Use of boot strap pins as I/O should be avoided if other GPIO pins can be used instead.
Pin
State during boot
Internal pull-up/down
Behavior
Description
B1
(PA30)
0
Internal regulator operates in LDO mode
Internal power
selection
1
10 kΩpull-up
Internal regulator operates in SPS mode
H2
(SWD_DATA)
0
Boot to test mode
Test Mode
1
50 kΩpull-up
Normal boot
A5
(PA7)
0
Bootloader –download image from UART
Booting Mode
1
50 kΩpull-up
Boot from internal flash
Table 7: NORA-W30 series boot strap pins
2.7 Real-time clock
The real-time clock (RTC) runs when NORA-W30 is powered, regardless of power mode. The RTC
maintains time with seconds, minutes, hours, and days (12- or 24-hour format). Daylight saving
compensation is programmable by the application. An alarm output on a GPIO may be enabled –
RTC_OUT.
2.7.1 External low-frequency clock source
If additional power savings are required, an external low-frequency clock source –EXT_32K –can be
provided on a GPIO pin. EXT_32K is a logic level input referenced to VDD and operates at 32.768 kHz.

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2.8 Antenna integration
Antenna interfaces are different for each module variant in the NORA-W30 series. The modules
support either an internal antenna (NORA-W306) or external antennas connected through a
dedicated antenna pin (NORA-W301).
2.8.1 External RF antenna interface
The NORA-W301 module is equipped with an antenna signal (ANT) pin. The pin has a nominal
characteristic impedance of 50 and must be connected to the antenna through a 50 transmission
line.
Choose an antenna with optimal radiating characteristics for the best electrical performance and
overall module functionality. An internal antenna, integrated on the application board or an external
antenna connected to the application board through a proper 50 connector, can be used.
When using an external antenna, the PCB-to-RF-cable transition must be implemented using either
a suitable 50 connector, or an RF-signal solder pad (including GND) that is optimized for 50 
characteristic impedance.
2.8.1.1 Antenna matching
The antenna return loss should be as low as possible across bothboth bands to provide optimal
performance. The enclosure, shields, other components, and surrounding environment might impact
the return loss that is seen at the antenna port. Matching components are often required to retune
the antenna to 50 characteristic impedance.
It is difficult to predict the actual matching values for the antenna in the final form factor. Therefore,
it is good practice to have a placeholder in the circuit with a “pi” network, with two shunt components
and a series component in the middle. This allows maximum flexibility while tuning the matching to
the antenna feed.
2.8.1.2 Approved antenna designs
NORA-W301 modules come with a pre-certified design that utilizes a U.FL connector for an external
antenna. The certification can be used to save costs and time during the certification process. See
Approved antennas.
The designer integrating a u-blox reference design into an end-product is solely responsible for any
unintentional RF emission generated by the end product.
The module may be integrated with other antennas. In which case, the OEM installer must certify the
design with respective regulatory agencies.
2.8.2 Internal antenna
NORA-W306 modules have an internal antenna that is specifically designed and optimized for u-blox
Wi-Fi, and Bluetooth LE modules. With NORA-W306, designers only need to consider the module
placement and GND clearance in antenna area.
2.9 Data interfaces
NORA-W30 modules have 20 I/O pins. The pins can be assigned to the data interfaces listed below;
however, assignments cannot be in conflict. To visualize the available pin assignments for the
interfaces, see Table 3.

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2.9.1 Universal Asynchronous Receiver Transmitter (UART)
NORA-W30 modules have up to five UART interfaces for data communication and firmware upgrade:
•HS_UART0: high-speed UART with a maximum baud rate of TBD kbps.
•HS_USI_UART: high-speed UART with a maximum baud rate of TBD kbps. See also Universal
Serial Interface (USI).
•IR_UART: high-speed UART capable of transmitting and decoding modulated infrared signals
compatible with the Infrared Data Association (IrDA) specification.
•LP_UART1: low-power UART with a maximum baud rate of TBD kbps. Can wake MCU from sleep.
•LP_UART0: low power UART with a maximum baud rate of TBD kbps. Can wake MCU from sleep.
Used for firmware updates and debug logging.
Each interface provides asynchronous communication support for RS232, RS485 standards (with
external drivers). Each UART supports the following signals:
•Data lines (RXD as input, TXD as output)
•Hardware flow control lines (CTS as input, RTS as output)
You can use the UARTs in 4-wire mode with hardware flow control, or in 2-wire mode with TXD and
RXD only.
☞2-wire mode is not recommended at higher speeds (e.g., 115.2 kbps), because it is prone to buffer
overruns.
When used in infrared mode, the maximum modulation frequency is 500 kHz.
The LP_UART0 interface can also be used for firmware upgrade. See also Open CPU software. It is
recommended that this UART is either connected to a header for firmware upgrade or made available
with test points.
2.9.2 Serial Peripheral Interface (SPI)
NORA-W30 modules have up to three SPI interfaces. Each SPI interface consists of four signals –
SCLK, nSPI_CS, MOSI, and MISO. The Motorola SPI protocol is supported. Data speeds and modes
are:
•HS_SPI0: ≤50 Mbps, master or slave mode
•HS_SPI1: ≤25 Mbps, master mode only
•HS_USI_SPI: ≤25 Mbps, master or slave mode. See also Universal Serial Interface (USI).
2.9.3 Inter-IC (I2C) interface
NORA-W30 modules have up to two I2C interfaces. Each I2C interface consists of two signals –SCL
and SDA. Data speeds and modes are:
•LP_I2C: standard (≤100 kbps), fast (≤400 kbps), master or slave mode
•HS_USI_I2C: standard (≤100 kbps), fast (≤400 kbps), high-speed (≤3.4 Mbps), master or slave
mode. See also Universal Serial Interface (USI).
2.9.4 Inter-IC Sound (I2S)
NORA-W30 modules have up to one high-speed I2S interface for communication with digital audio
devices. In mono or stereo mode, the interface consists of the following signals –MCK, SCK, WS,
SD_o, and SD_i. In 5.1 channel (surround sound) mode, the interface consists of the following signals
–MCK, SCK, WS, SD0, SD1, and SD2.

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2.9.5 Universal Serial Interface (USI)
NORA-W30 modules have up to one USI. The USI can be used as a high-speed I2C, UART, or SPI
interface –in addition other high-speed communications interfaces listed above. See also Inter-IC
(I2C) interface, Serial Peripheral Interface (SPI), and Universal Asynchronous Receiver Transmitter
(UART).
2.10 Digital interfaces
NORA-W30 modules have 20 I/O pins. The pins can be assigned to the digital interfaces listed below;
however, assignments cannot be in conflict. To visualize the available pin assignments for the
interfaces, see the Table 3.
2.10.1 Pulse Width Modulation (PWM)
NORA-W30 modules support up to 18 PWM outputs. There are 12 high-speed outputs –
HS_PWM[0,1,4..7,10..15] –and 6 low-power outputs –LP_PWM[0..5].The PWM module enables the
generation of pulse width modulated signals on GPIO. The module implements 16-bit up counters that
drive assigned GPIOs.
2.10.2 Key-scan
NORA-W30 modules support a keypad interface, consisting of up to 5 row x 2 column or 4 row x 3
column matrices. The key-scan can be used to wake NORA-W30 from deep-sleep.
2.10.3 Quadrature Decoder (Q-Decoder or QDEC)
NORA-W30 modules have up to one Q-Decoder to determine the position and speed of a rotary device.
The interface consists of the following signals –IDX, PHA, and PHB.
2.11 Analog
NORA-W30 modules have up to three analog inputs –ADC_4, ADC_5, and ADC_6. The pins
assignments cannot be in conflict with data and digital interfaces. To visualize the available pin
assignments for the interfaces, see Table 3.
2.12 Debug
NORA-W30 series uses the Arm® Serial Wire Debug (SWD) interface –SWD_DATA and SWD_CLK –
for programming and debugging both cores of the Realtek RTL8720DF within the module.
2.13 No-connect pins (n/c)
Do not connect n/c pins. No-Connect pins are allocated for future interfaces and functionality.
2.14 Ground (GND) pins
Good electrical connection of all module GND pins, using solid ground layer of the host application
board, is required for correct RF performance. Firm connections provide a thermal heat sink for the
module and significantly reduce EMC issues.

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3Design-in
Follow the design guidelines stated in this chapter to optimize the integration of NORA-W30 series
modules in the final application board.
3.1 Overview
Although all application circuits must be properly designed, there are several points that require
special attention during application design. A list of these points, in order of importance, follows:
•Module antenna connection: ANT Pad (NORA-W301 only)
Antenna circuits affect the RF compliance of all applications that include the certification
schemes related to the module. To maintain compliance and subsequent certification of the
application design, it is important to observe the applicable parts of antenna schematic and layout
design described in Antenna interface.
•Module supply: VDD and GND pins.
Supply circuits can affect the RF performance. It is important to observe the schematic and layout
design for these supplies. See also VDD application circuits. Modules normally include several
supply pins described in the pin out of the NORA-W30 data sheet [2].
•High-speed data interfaces: UART, SPI, and I2C pins.
High-speed data interfaces are a potential source of radiated noise that can affect the regulatory
compliance standards for radiated emissions. It is important to follow the schematic and layout
design recommendations described in the General high-speed layout guidelines.
•System functions: nRESET, GPIO and other System input and output pins
Careful utilization of these pins in the application design is required to guarantee correct boot up
and system operation. Ensure that the voltage level is correctly defined during module boot. It is
important to follow the schematic and layout design recommendations described in the General
high-speed layout guidelines.
•Other pins: ADC and NC pins.
Careful utilization of these pins is required to guarantee proper functionality. It is important to
follow the schematic and layout design recommendations described in the General high-speed
layout guidelines.
3.2 Antenna interface
As the unit cannot be mounted arbitrarily, the placement should be chosen with consideration so that
it does not interfere with radio communication. NORA-W306 modules that include an internal PCB
trace antenna cannot be mounted in a metal enclosure. No metal casing or plastics using metal flakes
should be used. Avoid metallic based paint or lacquer as well. NORA-W301 modules offer more
freedom as an external antenna can be mounted further away from the module.
⚠According to the FCC regulations, the transmission line from the module’s antenna pin to the
antenna or antenna connectoron the host PCB is considered part of the approved antenna design.
Therefore, module integrators must either follow exactly one of the antenna reference designs
used in the module’s FCC type approval or certify their own designs.
3.2.1 RF transmission line design (NORA-W301)
RF transmission lines, such as the ones from the ANT pad up to the related internal antenna pad,
must be designed so that the characteristic impedance is as close as possible to 50 .
Design options and the most important parameters for implementing a transmission line on a PCB
are described below:
•Microstrip: track separated with dielectric material and coupled to a single ground plane.

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•Coplanar microstrip: track separated with dielectric material and coupled to both the ground plane
and side conductor.
•Stripline: track separated by dielectric material and sandwiched between two parallel ground
planes.
Figure 3: Transmission line trace design
Follow these recommendations to design a 50 transmission line correctly:
•The designer should provide enough clearance from surrounding traces and ground in the same
layer; in general, a trace to ground clearance of at least two times the trace width should be
considered. The transmission line should also be ‘guarded’ by ground plane area on each side.
•The characteristic impedance can be calculated as first iteration using tools provided by the layout
software. It is advisable to ask the PCB manufacturer to provide the final values that are usually
calculated using dedicated software and available stack-ups from production. It could also be
possible to request an impedance coupon on panel’s side to measure the real impedance of the
traces.
•FR-4 dielectric material, although it has high losses at high frequencies, can be considered in RF
designs provided that:
oRF trace length must be minimized to reduce dielectric losses.
oIf traces longer than a few centimeters are needed, it is recommended to use a coaxial
connector and cable to reduce losses
oStack-up should allow for thick 50 traces and at least 200 µm trace width is recommended
to assure good impedance control over the PCB manufacturing process.
oFR-4 material exhibits poor thickness stability and thus less control of impedance over the
trace length. Contact the PCB manufacturer for specific tolerance of controlled impedance
traces.
•The transmission lines width and spacing to the GND must be uniform and routed as smoothly as
possible: route RF lines in arcs (preferred) or 45° angles.
•Add GND stitching vias around transmission lines.
•Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground
layer, providing enough vias on the adjacent metal layer.
•Route RF transmission lines far from any noise source (e.g., switching supplies and digital lines)
and from any sensitive circuit to avoid crosstalk between RF traces and high impedance or analog
signals.
•Avoid stubs on the transmission lines, any component on the transmission line should be placed
with the connected pad over the trace. Also avoid any unnecessary components on RF traces.

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3.2.2 Antenna design (NORA-W301)
NORA-W301 is suited for designs when an external antenna is needed due to mechanical integration
or placement of the module.
Designers must take care of the antennas from all perspective at the beginning of the design phase
when the physical dimensions of the application board are under analysis/decision, as the RF
compliance of the device integrating NORA-W301 module with all the applicable required certification
schemes heavily depends on the radiating performance of the antennas. The designer is encouraged
to consider one of the u-blox suggested antenna part numbers and follow the layout requirements.
•External antennas such as those listed at Approved antennas:
oExternal antennas basically do not imply physical restriction to the design of the PCB where
the module is mounted.
oThe radiation performance mainly depends on the antennas. It is required to select antennas
with optimal radiating performance in the operating bands.
oRF cables should carefully be selected with minimum insertion losses. Additional insertion loss
will be introduced by low quality or long cable. Large insertion loss reduces radiation
performance.
oA high quality 50 coaxial connector provides proper PCB-to-RF-cable transition.
•Integrated antennas such as patch-like antennas:
oInternal integrated antennas imply physical restriction to the PCB design:
Integrated antenna excites RF currents on its counterpoise, typically the PCB ground plane of
the device that becomes part of the antenna; its dimension defines the minimum frequency
that can be radiated. Therefore, the ground plane can be reduced to a minimum size that
should be similar to the quarter of the wavelength of the minimum frequency that has to be
radiated, given that the orientation of the ground plane related to the antenna element must
be considered.
The RF isolation between antennas in the system must be as high as possible and the
correlation between the 3D radiation patterns of the two antennashas to be as low as possible.
In general, an RF separation of at least a quarter wavelength between the two antennas is
required to achieve a maximum isolation and low pattern correlation; increased separation
should be considered, if possible, to maximize the performance and fulfil the requirements
described in Table 8. As a numerical example, the physical restriction to the PCB design can be
considered as shown below:
Frequency = 2.4 GHz →Wavelength = 12.5 cm →Quarter wavelength = 3.125 cm
2
oRadiation performance depends on the whole product and antenna system design, including
product mechanical design and usage. Antennas should be selected with optimal radiating
performance in the operating bands according to the mechanical specifications of the PCB and
the whole product.
2
Wavelength referred to a signal propagating over the air.