Abov A96G140 User manual

Global Top Smart MCU Innovator
www.abovsemi.com
A96G140/A96G148/A96A148
User’s Manual
16 MHz 8-bit A96G140/A96G148/A96A148 Microcontroller
64/32 Kbyte Flash memory, 12-bit ADC, 6 Timers, USART,
USI, High Current Port
Version 1.29
Introduction
This user’s manual targets application developers who use A96G140/A96G148/A96A148 for their
specific needs. It provides complete information of how to use A96G140/A96G148/A96A148 device.
Standard functions and blocks including corresponding register information of A96G140/ A96G148/
A96A148 are introduced in each chapter, while instruction set is in Appendix.
A96G140/A96G148/A96A148 is based on M8051 core and provides standard features of 8051 such as
8-bit ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit
data bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
64Kbytes of FLASH, 256bytes of IRAM, 2304bytes of XRAM, general purpose I/O, basic interval timer,
watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 16-bit PWM output, watch
timer, buzzer driving port, USI, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator and
clock circuitry.
As a field proven best seller, A96G140/A96G148/A96A148 has been sold more than 3 billion units up
to now, and introduces rich features such as excellent noise immunity, code optimization, cost
effectiveness, and so on.
Reference document
A96G140/A96G148/A96A148 programming tools and manuals released by ABOV: They are
available at ABOV website, www.abovsemi.com.
SDK-51 User’s guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel’s 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentorwebsite: https://www.mentor.com/products/ip/peripheral/microcontroller/

Contents A96G140/A96G148/A96A148 User’s manual
2
Contents
1Description..................................................................................................................................................... 18
1.1 Device overview ............................................................................................................................... 18
1.2 A96G140/A96G148/A96A148 block diagram ..................................................................... 21
2Pinouts and pin description................................................................................................................... 22
2.1 Pinouts ................................................................................................................................................. 22
2.2 Pin description.................................................................................................................................. 27
3Port structures.............................................................................................................................................. 32
4Memory organization................................................................................................................................ 34
4.1 Program memory ............................................................................................................................ 34
4.2 Data memory .................................................................................................................................... 35
4.3 External data memory................................................................................................................... 37
4.4 SFR map .............................................................................................................................................. 38
4.4.1 SFR map summary........................................................................................................... 38
4.4.2 SFR map................................................................................................................................ 40
4.4.3 Compiler compatible SFR ............................................................................................. 45
5I/O ports ......................................................................................................................................................... 47
5.1 Port register....................................................................................................................................... 47
5.1.1 Data register (Px).............................................................................................................. 47
5.1.2 Direction register (PxIO) ................................................................................................ 47
5.1.3 Pull-up register selection register (PxPU).............................................................. 47
5.1.4 Open-drain Selection Register (PxOD) ................................................................... 47
5.1.5 De-bounce Enable Register (PxDB) .......................................................................... 47
5.1.6 Port Function Selection Register (PxFSR)............................................................... 47
5.1.7 Register Map ...................................................................................................................... 48
5.2 P0 port ................................................................................................................................................. 49
5.2.1 P0 port description.......................................................................................................... 49
5.2.2 Register description for P0........................................................................................... 49
5.3 P1 port ................................................................................................................................................. 52
5.3.1 P1 port description.......................................................................................................... 52
5.3.2 Register description for P1........................................................................................... 52
5.4 P2 port ................................................................................................................................................. 56

A96G140/A96G148/A96A148 User’s manual Contents
3
5.4.1 P2 port description.......................................................................................................... 56
5.4.2 Register description for P2........................................................................................... 56
5.5 P3 port ................................................................................................................................................. 58
5.5.1 P3 port description.......................................................................................................... 58
5.5.2 Register description for P3........................................................................................... 58
5.6 P4 port ................................................................................................................................................. 60
5.6.1 P4 port description.......................................................................................................... 60
5.6.2 Register description for P4........................................................................................... 60
5.7 P5 port ................................................................................................................................................. 62
5.7.1 P5 port description.......................................................................................................... 62
5.7.2 Register description for P5........................................................................................... 62
6Interrupt controller..................................................................................................................................... 64
6.1 External interrupt............................................................................................................................. 65
6.2 Block diagram................................................................................................................................... 66
6.3 Interrupt vector table .................................................................................................................... 68
6.4 Interrupt sequence ......................................................................................................................... 69
6.5 Effective timing after controlling interrupt bit................................................................... 70
6.6 Multi-interrupt .................................................................................................................................. 71
6.7 Interrupt enable accept timing ................................................................................................. 72
6.8 Interrupt service routine address............................................................................................. 73
6.9 Saving/restore general purpose registers............................................................................ 73
6.10 Interrupt timing................................................................................................................................ 74
6.11 Interrupt register overview.......................................................................................................... 74
6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3)................................................... 74
6.11.2 Interrupt Priority Register (IP and IP1).................................................................... 74
6.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1) ................................ 75
6.11.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, and EIPOL1) ...... 75
6.11.5 Register map....................................................................................................................... 75
6.11.6 Interrupt register description...................................................................................... 75
7Clock generator ........................................................................................................................................... 82
7.1 Clock generator block diagram ................................................................................................ 82
7.2 Register map ..................................................................................................................................... 83
7.3 Register description ....................................................................................................................... 83
8Basic interval timer..................................................................................................................................... 86
8.1 BIT block diagram........................................................................................................................... 86

Contents A96G140/A96G148/A96A148 User’s manual
4
8.2 BIT register map .............................................................................................................................. 86
8.3 BIT register description................................................................................................................. 87
9Watchdog timer........................................................................................................................................... 88
9.1 WDT interrupt timing waveform .............................................................................................. 88
9.2 WDT block diagram ....................................................................................................................... 89
9.3 Register map ..................................................................................................................................... 89
9.4 Register description ....................................................................................................................... 89
10 Watch timer................................................................................................................................................... 91
10.1 WT block diagram........................................................................................................................... 91
10.2 Register map ..................................................................................................................................... 91
10.3 Watch timer register description ............................................................................................. 92
11 Timer 0/1/2/3/4/5....................................................................................................................................... 94
11.1 Timer 0................................................................................................................................................. 94
11.1.1 8-bit timer/counter mode............................................................................................. 94
11.1.2 8-bit PWM mode.............................................................................................................. 96
11.1.3 8-bit capture mode ......................................................................................................... 98
11.1.4 Timer 0 block diagram.................................................................................................100
11.1.5 Register map.....................................................................................................................100
11.1.6 Register description.......................................................................................................100
11.2 Timer 1...............................................................................................................................................102
11.2.1 16-bit timer/counter mode........................................................................................102
11.2.2 16-bit capture mode.....................................................................................................104
11.2.3 16-bit PPG mode............................................................................................................105
11.2.4 16-bit timer 1 block diagram....................................................................................108
11.2.5 Register map.....................................................................................................................108
11.2.6 Register description.......................................................................................................108
11.3 Timer 2...............................................................................................................................................111
11.3.1 16-bit timer/counter mode........................................................................................112
11.3.2 16-bit capture mode.....................................................................................................114
11.3.3 16-bit PPG mode............................................................................................................116
11.3.4 16-bit timer 2 block diagram....................................................................................118
11.3.5 Register map.....................................................................................................................118
11.3.6 Register description.......................................................................................................118

A96G140/A96G148/A96A148 User’s manual Contents
5
11.4 Timer 3...............................................................................................................................................121
11.4.1 16-bit timer/counter mode........................................................................................121
11.4.2 16-bit capture mode.....................................................................................................123
11.4.3 16-bit PPG mode............................................................................................................125
11.4.4 16-bit timer 3 block diagram....................................................................................127
11.4.5 Register map.....................................................................................................................127
11.4.6 Register description.......................................................................................................127
11.5 Timer 4...............................................................................................................................................130
11.5.1 16-bit timer/counter mode........................................................................................131
11.5.2 16-bit capture mode.....................................................................................................133
11.5.3 16-bit PPG mode............................................................................................................135
11.5.4 16-bit timer 4 block diagram....................................................................................137
11.5.5 Register map.....................................................................................................................137
11.5.6 Register description.......................................................................................................137
11.6 Timer 5...............................................................................................................................................140
11.6.1 16-bit timer/counter mode........................................................................................140
11.6.2 16-bit capture mode.....................................................................................................142
11.6.3 16-bit PPG mode............................................................................................................144
11.6.4 16-bit timer 5 block diagram....................................................................................146
11.6.5 Register map.....................................................................................................................146
11.6.6 Register description.......................................................................................................146
12 Buzzer driver ...............................................................................................................................................149
12.1 Buzzer driver block diagram ....................................................................................................149
12.2 Register map ...................................................................................................................................149
12.3 Register description .....................................................................................................................150
13 12-bit ADC ...................................................................................................................................................151
13.1 Conversion timing.........................................................................................................................151
13.2 Block diagram.................................................................................................................................151
13.3 ADC operation................................................................................................................................153
13.4 Register map ...................................................................................................................................154
13.5Register description .....................................................................................................................154
14 USI (USART + SPI + I2C).......................................................................................................................157
14.1 USIn UART mode...........................................................................................................................157

Contents A96G140/A96G148/A96A148 User’s manual
6
14.2 USIn UART block diagram.........................................................................................................158
14.3 USIn clock generation.................................................................................................................159
14.4 USIn external clock (SCKn)........................................................................................................160
14.5 USIn synchronous mode operation ......................................................................................160
14.6 USIn UART data format..............................................................................................................160
14.7 USIn UART parity bit....................................................................................................................161
14.8 USIn UART transmitter................................................................................................................162
14.8.1 USIn UART sending TX data......................................................................................162
14.8.2 USIn UART transmitter flag and interrupt...........................................................162
14.8.3 USIn UART parity generator ......................................................................................163
14.8.4 USIn UART disabling transmitter.............................................................................163
14.9 USIn UART receiver ......................................................................................................................163
14.9.1 USIn UART receiver RX data......................................................................................163
14.9.2 USIn UART receiver flag and interrupt .................................................................164
14.9.3 USIn UART parity checker...........................................................................................164
14.9.4 USIn UART disabling receiver ...................................................................................164
14.9.5 USIn Asynchronous data reception........................................................................164
14.10 USIn SPI mode................................................................................................................................166
14.11 USIn SPI clock formats and timing .......................................................................................167
14.12 USIn SPI block diagram..............................................................................................................169
14.13 USIn I2C mode ...............................................................................................................................169
14.14 USIn I2C bit transfer.....................................................................................................................170
14.15 USIn I2C start/ repeated start/ stop.....................................................................................170
14.16 USIn I2C data transfer.................................................................................................................171
14.17 USIn I2C acknowledge ................................................................................................................171
14.18 USIn I2C synchronization/ arbitration..................................................................................172
14.19 USIn I2C operation .......................................................................................................................173
14.19.1USIn I2C master transmitter ......................................................................................174
14.19.2USIn I2C master receiver.............................................................................................176
14.19.3USIn I2C slave transmitter..........................................................................................177
14.19.4USIn I2C slave receiver.................................................................................................178
14.20 USIn I2C block diagram..............................................................................................................180
14.21 Register map ...................................................................................................................................180
14.22 USIn register description ...........................................................................................................181
14.23 Baud rate settings (example) ...................................................................................................189
15 USART2..........................................................................................................................................................192

A96G140/A96G148/A96A148 User’s manual Contents
7
15.1 Block diagram.................................................................................................................................193
15.2 Clock generation............................................................................................................................194
15.3 External clock (XCK)......................................................................................................................195
15.4 Synchronous mode operation.................................................................................................195
15.5 Data format......................................................................................................................................196
15.6 Parity bit ............................................................................................................................................197
15.7 USART2 transmitter ......................................................................................................................197
15.7.1 Sending Tx data ..............................................................................................................197
15.7.2 Transmitter flag and interrupt ..................................................................................197
15.7.3 Parity generator...............................................................................................................198
15.7.4 Disabling transmitter.....................................................................................................198
15.8 USART2 receiver.............................................................................................................................198
15.8.1 Receiving Rx data...........................................................................................................198
15.8.2 Receiver flag and interrupt ........................................................................................199
15.8.3 Parity checker...................................................................................................................199
15.8.4 Disabling receiver ...........................................................................................................199
15.8.5 Asynchronous data reception ...................................................................................200
15.9 SPI mode...........................................................................................................................................201
15.9.1 SPI clock formats and timing....................................................................................202
15.10 Receiver time out (RTO).............................................................................................................204
15.11 Register map ...................................................................................................................................205
15.12 Register description .....................................................................................................................205
15.13 Baud rate settings (example) ...................................................................................................212
15.14 0% error baud rate.......................................................................................................................213
16 Power down operation...........................................................................................................................215
16.1 Peripheral operation in IDLE/ STOP mode ........................................................................215
16.2 IDLE mode........................................................................................................................................216
16.3 STOP mode......................................................................................................................................216
16.4 Released operation of STOP mode.......................................................................................217
16.5 Register map ...................................................................................................................................218
16.6 Register description .....................................................................................................................218
17 Reset...............................................................................................................................................................220
17.1 Reset block diagram ....................................................................................................................220
17.2 Power on reset ...............................................................................................................................220
17.3 External resetb input....................................................................................................................223
17.4 Low voltage reset process.........................................................................................................224
17.5 LVI block diagram.........................................................................................................................226

Contents A96G140/A96G148/A96A148 User’s manual
8
17.6 Register Map...................................................................................................................................227
17.7 Reset Operation Register Description..................................................................................227
18 Memory programming...........................................................................................................................230
18.1 Flash control and status registers..........................................................................................230
18.1.1 Register map.....................................................................................................................230
18.1.2 Register description.......................................................................................................230
18.2 Memory map...................................................................................................................................237
18.2.1 Flash memory map........................................................................................................237
18.3 Serial in-system program mode.............................................................................................238
18.3.1 Flash operation................................................................................................................238
18.4 Mode entrance method of ISP mode..................................................................................244
18.4.1 Mode entrance method for ISP ...............................................................................244
18.5 Security ..............................................................................................................................................245
18.6 Configure option ...........................................................................................................................245
19 Electrical characteristics..........................................................................................................................248
19.1 Absolute maximum ratings.......................................................................................................248
19.2 Recommended operating conditions...................................................................................249
19.3 A/D converter characteristics...................................................................................................249
19.4 Power on reset characteristics.................................................................................................250
19.5 Low voltage reset and low voltage indicator characteristics ....................................250
19.6 High Speed Internal RC oscillator characteristics...........................................................251
19.7 Low Speed Internal RC oscillator characteristics.............................................................251
19.8 DC characteristics..........................................................................................................................252
19.9 AC characteristics ..........................................................................................................................253
19.10 USART characteristics ..................................................................................................................255
19.11 SPI0/1 characteristics...................................................................................................................258
19.12 UART0/1 characteristics..............................................................................................................259
19.13 I2C0/1 characteristics...................................................................................................................260
19.14 Data retention voltage in stop mode ..................................................................................261
19.15 Internal flash ROM characteristics .........................................................................................262
19.16 Main clock oscillator characteristics .....................................................................................263
19.17 Sub-clock oscillator characteristics........................................................................................264
19.18 Main oscillation stabilization characteristics .....................................................................265
19.19 Sub-oscillation characteristics..................................................................................................265
19.20 Operating voltage range............................................................................................................266
19.21 Recommended circuit and layout..........................................................................................267
19.22 Typical characteristics..................................................................................................................267
20 Development tools...................................................................................................................................270

A96G140/A96G148/A96A148 User’s manual Contents
9
20.1 Compiler............................................................................................................................................270
20.2 OCD (On-chip debugger) emulator and debugger.......................................................270
20.3 Programmers...................................................................................................................................271
20.3.1 E-PGM+...............................................................................................................................271
20.3.2 OCD emulator ..................................................................................................................271
20.3.3 Gang programmer .........................................................................................................271
20.4 Flash programming ......................................................................................................................272
20.4.1 On-board programming..............................................................................................272
20.4.2 Circuit design guide ......................................................................................................272
20.5 On-chip debug system ...............................................................................................................273
20.5.1 Two-pin external interface..........................................................................................274
21 Package information................................................................................................................................279
21.1 48 LQFP package information.................................................................................................279
21.2 48 QFN package information ..................................................................................................280
21.3 44 MQFP package information...............................................................................................281
21.4 32 LQFP package information.................................................................................................282
21.5 32 SOP package information...................................................................................................283
21.6 28 SOP package information...................................................................................................284
21.7 28 TSSOP package information..............................................................................................285
22 Ordering information..............................................................................................................................286
Appendix................................................................................................................................................................288
Instruction table.........................................................................................................................................288
Revision history...................................................................................................................................................294

List of figures A96G140/A96G148/A96A148 User’s manual
10
List of figures
Figure 1. A96G140/A96G148/A96A148 Block Diagram.......................................................................................... 21
Figure 2. A96G140/A96G148 48LQFP/48QFN Pin Assignment........................................................................... 22
Figure 3. A96G140/A96G148 44MQFP-1010 Pin Assignment............................................................................. 23
Figure 4. A96G140/A96G148 32LQFP Pin Assignment ........................................................................................... 24
Figure 5. A96G140/A96G148 32SOP Pin Assignment............................................................................................. 25
Figure 6. A96G140/A96G148 28SOP Pin Assignment............................................................................................. 25
Figure 7. A96A148 28SOP Pin Assignment .................................................................................................................. 26
Figure 8. General Purpose I/O Port ................................................................................................................................. 32
Figure 9. External Interrupt I/O Port................................................................................................................................ 33
Figure 10. Program Memory Map.................................................................................................................................... 35
Figure 11. Data Memory Map............................................................................................................................................ 36
Figure 12. Lower 128bytes of RAM ................................................................................................................................. 37
Figure 13. XDATA Memory Area........................................................................................................................................ 38
Figure 14. Interrupt Group Priority Level ...................................................................................................................... 65
Figure 15. External Interrupt Description ...................................................................................................................... 66
Figure 16. Interrupt Controller Block Diagram ........................................................................................................... 67
Figure 17. Interrupt Sequence Flow ................................................................................................................................ 70
Figure 18. Effective Timing of Interrupt Enable Register....................................................................................... 71
Figure 19. Effective Timing of Interrupt Flag Register ............................................................................................ 71
Figure 20. Effective Timing of Multi-Interrupt ............................................................................................................ 72
Figure 21. Interrupt Response Timing Diagram......................................................................................................... 73
Figure 22. Correspondence between Vector Table Address and the Entry Address of ISR .................. 73
Figure 23. Saving/Restore Process Diagram and Sample Source...................................................................... 73
Figure 24. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction................................. 74
Figure 25. Clock Generator Block Diagram.................................................................................................................. 83
Figure 26. Basic Interval Timer Block Diagram........................................................................................................... 86
Figure 27. Watch Dog Timer Interrupt Timing Waveform .................................................................................... 88
Figure 28. Watch Dog Timer Block Diagram............................................................................................................... 89
Figure 29. Watch Timer Block Diagram ......................................................................................................................... 91
Figure 30. 8-bit Timer/Counter Mode for Timer 0................................................................................................... 95
Figure 31. 8-bit Timer/Counter 0 Example................................................................................................................... 95
Figure 32. 8-bit PWM Mode for Timer 0...................................................................................................................... 96
Figure 33. PWM Output Waveforms in PWM Mode for Timer 0...................................................................... 97
Figure 34. 8-bit Capture Mode for Timer 0................................................................................................................. 98
Figure 35. Input Capture Mode Operation for Timer 0 ......................................................................................... 99
Figure 36. Express Timer Overflow in Capture Mode ............................................................................................. 99
Figure 37. 8-bit Timer 0 Block Diagram ......................................................................................................................100