Abov A96G140 User manual

Global Top Smart MCU Innovator
www.abovsemi.com
A96G140/A96G148/A96A148
User’s Manual
16 MHz 8-bit A96G140/A96G148/A96A148 Microcontroller
64/32 Kbyte Flash memory, 12-bit ADC, 6 Timers, USART,
USI, High Current Port
Version 1.29
Introduction
This user’s manual targets application developers who use A96G140/A96G148/A96A148 for their
specific needs. It provides complete information of how to use A96G140/A96G148/A96A148 device.
Standard functions and blocks including corresponding register information of A96G140/ A96G148/
A96A148 are introduced in each chapter, while instruction set is in Appendix.
A96G140/A96G148/A96A148 is based on M8051 core and provides standard features of 8051 such as
8-bit ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit
data bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
64Kbytes of FLASH, 256bytes of IRAM, 2304bytes of XRAM, general purpose I/O, basic interval timer,
watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 16-bit PWM output, watch
timer, buzzer driving port, USI, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator and
clock circuitry.
As a field proven best seller, A96G140/A96G148/A96A148 has been sold more than 3 billion units up
to now, and introduces rich features such as excellent noise immunity, code optimization, cost
effectiveness, and so on.
Reference document
A96G140/A96G148/A96A148 programming tools and manuals released by ABOV: They are
available at ABOV website, www.abovsemi.com.
SDK-51 User’s guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel’s 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentorwebsite: https://www.mentor.com/products/ip/peripheral/microcontroller/

Contents A96G140/A96G148/A96A148 User’s manual
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Contents
1Description..................................................................................................................................................... 18
1.1 Device overview ............................................................................................................................... 18
1.2 A96G140/A96G148/A96A148 block diagram ..................................................................... 21
2Pinouts and pin description................................................................................................................... 22
2.1 Pinouts ................................................................................................................................................. 22
2.2 Pin description.................................................................................................................................. 27
3Port structures.............................................................................................................................................. 32
4Memory organization................................................................................................................................ 34
4.1 Program memory ............................................................................................................................ 34
4.2 Data memory .................................................................................................................................... 35
4.3 External data memory................................................................................................................... 37
4.4 SFR map .............................................................................................................................................. 38
4.4.1 SFR map summary........................................................................................................... 38
4.4.2 SFR map................................................................................................................................ 40
4.4.3 Compiler compatible SFR ............................................................................................. 45
5I/O ports ......................................................................................................................................................... 47
5.1 Port register....................................................................................................................................... 47
5.1.1 Data register (Px).............................................................................................................. 47
5.1.2 Direction register (PxIO) ................................................................................................ 47
5.1.3 Pull-up register selection register (PxPU).............................................................. 47
5.1.4 Open-drain Selection Register (PxOD) ................................................................... 47
5.1.5 De-bounce Enable Register (PxDB) .......................................................................... 47
5.1.6 Port Function Selection Register (PxFSR)............................................................... 47
5.1.7 Register Map ...................................................................................................................... 48
5.2 P0 port ................................................................................................................................................. 49
5.2.1 P0 port description.......................................................................................................... 49
5.2.2 Register description for P0........................................................................................... 49
5.3 P1 port ................................................................................................................................................. 52
5.3.1 P1 port description.......................................................................................................... 52
5.3.2 Register description for P1........................................................................................... 52
5.4 P2 port ................................................................................................................................................. 56

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5.4.1 P2 port description.......................................................................................................... 56
5.4.2 Register description for P2........................................................................................... 56
5.5 P3 port ................................................................................................................................................. 58
5.5.1 P3 port description.......................................................................................................... 58
5.5.2 Register description for P3........................................................................................... 58
5.6 P4 port ................................................................................................................................................. 60
5.6.1 P4 port description.......................................................................................................... 60
5.6.2 Register description for P4........................................................................................... 60
5.7 P5 port ................................................................................................................................................. 62
5.7.1 P5 port description.......................................................................................................... 62
5.7.2 Register description for P5........................................................................................... 62
6Interrupt controller..................................................................................................................................... 64
6.1 External interrupt............................................................................................................................. 65
6.2 Block diagram................................................................................................................................... 66
6.3 Interrupt vector table .................................................................................................................... 68
6.4 Interrupt sequence ......................................................................................................................... 69
6.5 Effective timing after controlling interrupt bit................................................................... 70
6.6 Multi-interrupt .................................................................................................................................. 71
6.7 Interrupt enable accept timing ................................................................................................. 72
6.8 Interrupt service routine address............................................................................................. 73
6.9 Saving/restore general purpose registers............................................................................ 73
6.10 Interrupt timing................................................................................................................................ 74
6.11 Interrupt register overview.......................................................................................................... 74
6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3)................................................... 74
6.11.2 Interrupt Priority Register (IP and IP1).................................................................... 74
6.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1) ................................ 75
6.11.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, and EIPOL1) ...... 75
6.11.5 Register map....................................................................................................................... 75
6.11.6 Interrupt register description...................................................................................... 75
7Clock generator ........................................................................................................................................... 82
7.1 Clock generator block diagram ................................................................................................ 82
7.2 Register map ..................................................................................................................................... 83
7.3 Register description ....................................................................................................................... 83
8Basic interval timer..................................................................................................................................... 86
8.1 BIT block diagram........................................................................................................................... 86

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8.2 BIT register map .............................................................................................................................. 86
8.3 BIT register description................................................................................................................. 87
9Watchdog timer........................................................................................................................................... 88
9.1 WDT interrupt timing waveform .............................................................................................. 88
9.2 WDT block diagram ....................................................................................................................... 89
9.3 Register map ..................................................................................................................................... 89
9.4 Register description ....................................................................................................................... 89
10 Watch timer................................................................................................................................................... 91
10.1 WT block diagram........................................................................................................................... 91
10.2 Register map ..................................................................................................................................... 91
10.3 Watch timer register description ............................................................................................. 92
11 Timer 0/1/2/3/4/5....................................................................................................................................... 94
11.1 Timer 0................................................................................................................................................. 94
11.1.1 8-bit timer/counter mode............................................................................................. 94
11.1.2 8-bit PWM mode.............................................................................................................. 96
11.1.3 8-bit capture mode ......................................................................................................... 98
11.1.4 Timer 0 block diagram.................................................................................................100
11.1.5 Register map.....................................................................................................................100
11.1.6 Register description.......................................................................................................100
11.2 Timer 1...............................................................................................................................................102
11.2.1 16-bit timer/counter mode........................................................................................102
11.2.2 16-bit capture mode.....................................................................................................104
11.2.3 16-bit PPG mode............................................................................................................105
11.2.4 16-bit timer 1 block diagram....................................................................................108
11.2.5 Register map.....................................................................................................................108
11.2.6 Register description.......................................................................................................108
11.3 Timer 2...............................................................................................................................................111
11.3.1 16-bit timer/counter mode........................................................................................112
11.3.2 16-bit capture mode.....................................................................................................114
11.3.3 16-bit PPG mode............................................................................................................116
11.3.4 16-bit timer 2 block diagram....................................................................................118
11.3.5 Register map.....................................................................................................................118
11.3.6 Register description.......................................................................................................118

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11.4 Timer 3...............................................................................................................................................121
11.4.1 16-bit timer/counter mode........................................................................................121
11.4.2 16-bit capture mode.....................................................................................................123
11.4.3 16-bit PPG mode............................................................................................................125
11.4.4 16-bit timer 3 block diagram....................................................................................127
11.4.5 Register map.....................................................................................................................127
11.4.6 Register description.......................................................................................................127
11.5 Timer 4...............................................................................................................................................130
11.5.1 16-bit timer/counter mode........................................................................................131
11.5.2 16-bit capture mode.....................................................................................................133
11.5.3 16-bit PPG mode............................................................................................................135
11.5.4 16-bit timer 4 block diagram....................................................................................137
11.5.5 Register map.....................................................................................................................137
11.5.6 Register description.......................................................................................................137
11.6 Timer 5...............................................................................................................................................140
11.6.1 16-bit timer/counter mode........................................................................................140
11.6.2 16-bit capture mode.....................................................................................................142
11.6.3 16-bit PPG mode............................................................................................................144
11.6.4 16-bit timer 5 block diagram....................................................................................146
11.6.5 Register map.....................................................................................................................146
11.6.6 Register description.......................................................................................................146
12 Buzzer driver ...............................................................................................................................................149
12.1 Buzzer driver block diagram ....................................................................................................149
12.2 Register map ...................................................................................................................................149
12.3 Register description .....................................................................................................................150
13 12-bit ADC ...................................................................................................................................................151
13.1 Conversion timing.........................................................................................................................151
13.2 Block diagram.................................................................................................................................151
13.3 ADC operation................................................................................................................................153
13.4 Register map ...................................................................................................................................154
13.5Register description .....................................................................................................................154
14 USI (USART + SPI + I2C).......................................................................................................................157
14.1 USIn UART mode...........................................................................................................................157

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14.2 USIn UART block diagram.........................................................................................................158
14.3 USIn clock generation.................................................................................................................159
14.4 USIn external clock (SCKn)........................................................................................................160
14.5 USIn synchronous mode operation ......................................................................................160
14.6 USIn UART data format..............................................................................................................160
14.7 USIn UART parity bit....................................................................................................................161
14.8 USIn UART transmitter................................................................................................................162
14.8.1 USIn UART sending TX data......................................................................................162
14.8.2 USIn UART transmitter flag and interrupt...........................................................162
14.8.3 USIn UART parity generator ......................................................................................163
14.8.4 USIn UART disabling transmitter.............................................................................163
14.9 USIn UART receiver ......................................................................................................................163
14.9.1 USIn UART receiver RX data......................................................................................163
14.9.2 USIn UART receiver flag and interrupt .................................................................164
14.9.3 USIn UART parity checker...........................................................................................164
14.9.4 USIn UART disabling receiver ...................................................................................164
14.9.5 USIn Asynchronous data reception........................................................................164
14.10 USIn SPI mode................................................................................................................................166
14.11 USIn SPI clock formats and timing .......................................................................................167
14.12 USIn SPI block diagram..............................................................................................................169
14.13 USIn I2C mode ...............................................................................................................................169
14.14 USIn I2C bit transfer.....................................................................................................................170
14.15 USIn I2C start/ repeated start/ stop.....................................................................................170
14.16 USIn I2C data transfer.................................................................................................................171
14.17 USIn I2C acknowledge ................................................................................................................171
14.18 USIn I2C synchronization/ arbitration..................................................................................172
14.19 USIn I2C operation .......................................................................................................................173
14.19.1USIn I2C master transmitter ......................................................................................174
14.19.2USIn I2C master receiver.............................................................................................176
14.19.3USIn I2C slave transmitter..........................................................................................177
14.19.4USIn I2C slave receiver.................................................................................................178
14.20 USIn I2C block diagram..............................................................................................................180
14.21 Register map ...................................................................................................................................180
14.22 USIn register description ...........................................................................................................181
14.23 Baud rate settings (example) ...................................................................................................189
15 USART2..........................................................................................................................................................192

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15.1 Block diagram.................................................................................................................................193
15.2 Clock generation............................................................................................................................194
15.3 External clock (XCK)......................................................................................................................195
15.4 Synchronous mode operation.................................................................................................195
15.5 Data format......................................................................................................................................196
15.6 Parity bit ............................................................................................................................................197
15.7 USART2 transmitter ......................................................................................................................197
15.7.1 Sending Tx data ..............................................................................................................197
15.7.2 Transmitter flag and interrupt ..................................................................................197
15.7.3 Parity generator...............................................................................................................198
15.7.4 Disabling transmitter.....................................................................................................198
15.8 USART2 receiver.............................................................................................................................198
15.8.1 Receiving Rx data...........................................................................................................198
15.8.2 Receiver flag and interrupt ........................................................................................199
15.8.3 Parity checker...................................................................................................................199
15.8.4 Disabling receiver ...........................................................................................................199
15.8.5 Asynchronous data reception ...................................................................................200
15.9 SPI mode...........................................................................................................................................201
15.9.1 SPI clock formats and timing....................................................................................202
15.10 Receiver time out (RTO).............................................................................................................204
15.11 Register map ...................................................................................................................................205
15.12 Register description .....................................................................................................................205
15.13 Baud rate settings (example) ...................................................................................................212
15.14 0% error baud rate.......................................................................................................................213
16 Power down operation...........................................................................................................................215
16.1 Peripheral operation in IDLE/ STOP mode ........................................................................215
16.2 IDLE mode........................................................................................................................................216
16.3 STOP mode......................................................................................................................................216
16.4 Released operation of STOP mode.......................................................................................217
16.5 Register map ...................................................................................................................................218
16.6 Register description .....................................................................................................................218
17 Reset...............................................................................................................................................................220
17.1 Reset block diagram ....................................................................................................................220
17.2 Power on reset ...............................................................................................................................220
17.3 External resetb input....................................................................................................................223
17.4 Low voltage reset process.........................................................................................................224
17.5 LVI block diagram.........................................................................................................................226

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17.6 Register Map...................................................................................................................................227
17.7 Reset Operation Register Description..................................................................................227
18 Memory programming...........................................................................................................................230
18.1 Flash control and status registers..........................................................................................230
18.1.1 Register map.....................................................................................................................230
18.1.2 Register description.......................................................................................................230
18.2 Memory map...................................................................................................................................237
18.2.1 Flash memory map........................................................................................................237
18.3 Serial in-system program mode.............................................................................................238
18.3.1 Flash operation................................................................................................................238
18.4 Mode entrance method of ISP mode..................................................................................244
18.4.1 Mode entrance method for ISP ...............................................................................244
18.5 Security ..............................................................................................................................................245
18.6 Configure option ...........................................................................................................................245
19 Electrical characteristics..........................................................................................................................248
19.1 Absolute maximum ratings.......................................................................................................248
19.2 Recommended operating conditions...................................................................................249
19.3 A/D converter characteristics...................................................................................................249
19.4 Power on reset characteristics.................................................................................................250
19.5 Low voltage reset and low voltage indicator characteristics ....................................250
19.6 High Speed Internal RC oscillator characteristics...........................................................251
19.7 Low Speed Internal RC oscillator characteristics.............................................................251
19.8 DC characteristics..........................................................................................................................252
19.9 AC characteristics ..........................................................................................................................253
19.10 USART characteristics ..................................................................................................................255
19.11 SPI0/1 characteristics...................................................................................................................258
19.12 UART0/1 characteristics..............................................................................................................259
19.13 I2C0/1 characteristics...................................................................................................................260
19.14 Data retention voltage in stop mode ..................................................................................261
19.15 Internal flash ROM characteristics .........................................................................................262
19.16 Main clock oscillator characteristics .....................................................................................263
19.17 Sub-clock oscillator characteristics........................................................................................264
19.18 Main oscillation stabilization characteristics .....................................................................265
19.19 Sub-oscillation characteristics..................................................................................................265
19.20 Operating voltage range............................................................................................................266
19.21 Recommended circuit and layout..........................................................................................267
19.22 Typical characteristics..................................................................................................................267
20 Development tools...................................................................................................................................270

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20.1 Compiler............................................................................................................................................270
20.2 OCD (On-chip debugger) emulator and debugger.......................................................270
20.3 Programmers...................................................................................................................................271
20.3.1 E-PGM+...............................................................................................................................271
20.3.2 OCD emulator ..................................................................................................................271
20.3.3 Gang programmer .........................................................................................................271
20.4 Flash programming ......................................................................................................................272
20.4.1 On-board programming..............................................................................................272
20.4.2 Circuit design guide ......................................................................................................272
20.5 On-chip debug system ...............................................................................................................273
20.5.1 Two-pin external interface..........................................................................................274
21 Package information................................................................................................................................279
21.1 48 LQFP package information.................................................................................................279
21.2 48 QFN package information ..................................................................................................280
21.3 44 MQFP package information...............................................................................................281
21.4 32 LQFP package information.................................................................................................282
21.5 32 SOP package information...................................................................................................283
21.6 28 SOP package information...................................................................................................284
21.7 28 TSSOP package information..............................................................................................285
22 Ordering information..............................................................................................................................286
Appendix................................................................................................................................................................288
Instruction table.........................................................................................................................................288
Revision history...................................................................................................................................................294

List of figures A96G140/A96G148/A96A148 User’s manual
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List of figures
Figure 1. A96G140/A96G148/A96A148 Block Diagram.......................................................................................... 21
Figure 2. A96G140/A96G148 48LQFP/48QFN Pin Assignment........................................................................... 22
Figure 3. A96G140/A96G148 44MQFP-1010 Pin Assignment............................................................................. 23
Figure 4. A96G140/A96G148 32LQFP Pin Assignment ........................................................................................... 24
Figure 5. A96G140/A96G148 32SOP Pin Assignment............................................................................................. 25
Figure 6. A96G140/A96G148 28SOP Pin Assignment............................................................................................. 25
Figure 7. A96A148 28SOP Pin Assignment .................................................................................................................. 26
Figure 8. General Purpose I/O Port ................................................................................................................................. 32
Figure 9. External Interrupt I/O Port................................................................................................................................ 33
Figure 10. Program Memory Map.................................................................................................................................... 35
Figure 11. Data Memory Map............................................................................................................................................ 36
Figure 12. Lower 128bytes of RAM ................................................................................................................................. 37
Figure 13. XDATA Memory Area........................................................................................................................................ 38
Figure 14. Interrupt Group Priority Level ...................................................................................................................... 65
Figure 15. External Interrupt Description ...................................................................................................................... 66
Figure 16. Interrupt Controller Block Diagram ........................................................................................................... 67
Figure 17. Interrupt Sequence Flow ................................................................................................................................ 70
Figure 18. Effective Timing of Interrupt Enable Register....................................................................................... 71
Figure 19. Effective Timing of Interrupt Flag Register ............................................................................................ 71
Figure 20. Effective Timing of Multi-Interrupt ............................................................................................................ 72
Figure 21. Interrupt Response Timing Diagram......................................................................................................... 73
Figure 22. Correspondence between Vector Table Address and the Entry Address of ISR .................. 73
Figure 23. Saving/Restore Process Diagram and Sample Source...................................................................... 73
Figure 24. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction................................. 74
Figure 25. Clock Generator Block Diagram.................................................................................................................. 83
Figure 26. Basic Interval Timer Block Diagram........................................................................................................... 86
Figure 27. Watch Dog Timer Interrupt Timing Waveform .................................................................................... 88
Figure 28. Watch Dog Timer Block Diagram............................................................................................................... 89
Figure 29. Watch Timer Block Diagram ......................................................................................................................... 91
Figure 30. 8-bit Timer/Counter Mode for Timer 0................................................................................................... 95
Figure 31. 8-bit Timer/Counter 0 Example................................................................................................................... 95
Figure 32. 8-bit PWM Mode for Timer 0...................................................................................................................... 96
Figure 33. PWM Output Waveforms in PWM Mode for Timer 0...................................................................... 97
Figure 34. 8-bit Capture Mode for Timer 0................................................................................................................. 98
Figure 35. Input Capture Mode Operation for Timer 0 ......................................................................................... 99
Figure 36. Express Timer Overflow in Capture Mode ............................................................................................. 99
Figure 37. 8-bit Timer 0 Block Diagram ......................................................................................................................100

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Figure 38. 16-bit Timer/Counter Mode of Timer 1 ................................................................................................103
Figure 39. 16-bit Timer/Counter Mode Operation Example..............................................................................103
Figure 40. 16-bit Capture Mode of Timer 1..............................................................................................................104
Figure 41. 16-bit Capture Mode Operation Example............................................................................................105
Figure 42. 16-bit PPG Mode of Timer 1......................................................................................................................106
Figure 43. 16-bit PPG Mode Operation Example....................................................................................................107
Figure 44. 16-bit Timer 1 Block Diagram....................................................................................................................108
Figure 45. 16-bit Timer/Counter Mode of Timer 2 ................................................................................................113
Figure 46. 16-bit Timer/Counter Mode Operation Example..............................................................................113
Figure 47. 16-bit Capture Mode of Timer 2..............................................................................................................114
Figure 48. 16-bit Capture Mode Operation Example............................................................................................115
Figure 49. Express Timer Overflow in Capture Mode ...........................................................................................115
Figure 50. 16-bit PPG Mode of Timer 2......................................................................................................................116
Figure 51. 16-bit PPG Mode Operation Example....................................................................................................117
Figure 52. 16-bit Timer 2 Block Diagram....................................................................................................................118
Figure 53. 16-bit Timer/Counter Mode of Timer 3 ................................................................................................122
Figure 54. 16-bit Timer/Counter Mode Operation Example..............................................................................122
Figure 55. 16-bit Capture Mode of Timer 3..............................................................................................................123
Figure 56. 16-bit Capture Mode Operation Example............................................................................................124
Figure 57. Express Timer Overflow in Capture Mode ...........................................................................................124
Figure 58. 16-bit PPG Mode of Timer 3......................................................................................................................125
Figure 59. 16-bit PPG Mode Operation Example....................................................................................................126
Figure 60. 16-bit Timer 3 Block Diagram....................................................................................................................127
Figure 61. 16-bit Timer/Counter Mode of Timer 4 ................................................................................................132
Figure 62. 16-bit Timer/Counter Mode Operation Example..............................................................................132
Figure 63. 16-bit Capture Mode of Timer 4..............................................................................................................133
Figure 64. 16-bit Capture Mode Operation Example............................................................................................134
Figure 65. Express Timer Overflow in Capture Mode ...........................................................................................134
Figure 66. 16-bit PPG Mode of Timer 4......................................................................................................................135
Figure 67. 16-bit PPG Mode Operation Example....................................................................................................136
Figure 68. 16-bit Timer 4 Block Diagram....................................................................................................................137
Figure 69. 16-bit Timer/Counter Mode of Timer 5 ................................................................................................141
Figure 70. 16-bit Timer/Counter Mode Operation Example..............................................................................141
Figure 71. 16-bit Capture Mode of Timer 5..............................................................................................................142
Figure 72. 16-bit Capture Mode Operation Example............................................................................................143
Figure 73. Express Timer Overflow in Capture Mode ...........................................................................................143
Figure 74. 16-bit PPG Mode of Timer 5......................................................................................................................144
Figure 75. 16-bit PPG Mode Operation Example....................................................................................................145
Figure 76. 16-bit Timer 5 Block Diagram....................................................................................................................146

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Figure 77. Buzzer Driver Block Diagram ......................................................................................................................149
Figure 78. 12-bit ADC Block Diagram ..........................................................................................................................152
Figure 79. A/D Analog Input Pin with a Capacitor.................................................................................................152
Figure 80. A/D Power (AVREF) Pin with a Capacitor..............................................................................................152
Figure 81. Control Registers and Align Bits...............................................................................................................153
Figure 82. ADC Operation Flow Sequence.................................................................................................................154
Figure 83. USIn USART Block Diagram (n = 0 and 1)...........................................................................................158
Figure 84. Clock Generation Block Diagram (USIn) ...............................................................................................159
Figure 85. Synchronous Mode SCKn Timing (USIn)...............................................................................................160
Figure 86. Frame Formats (USIn) ....................................................................................................................................161
Figure 87. Asynchronous Start Bit Sampling (USIn)...............................................................................................165
Figure 88. Asynchronous Sampling of Data and Parity Bit (USIn) ..................................................................166
Figure 89. Stop Bit Sampling and Next Start Bit Sampling (USIn)..................................................................166
Figure 90. USIn SPI Clock Formats when CPHAn = 0 ..........................................................................................167
Figure 91. USIn SPI Clock Formats when CPHAn = 1 ..........................................................................................168
Figure 92. USIn SPI Block Diagram (n = 0 and 1) ..................................................................................................169
Figure 93. Bit Transfer on the I2C-Bus (USIn) ...........................................................................................................170
Figure 94. START and STOP Condition (USIn)...........................................................................................................171
Figure 95. Data Transfer on the I2C-Bus (USIn).......................................................................................................171
Figure 96. Acknowledge on the I2C-Bus (USIn).......................................................................................................172
Figure 97. Clock Synchronization during Arbitration Procedure (USIn) .......................................................173
Figure 98. Arbitration Procedure of Two Masters (USIn).....................................................................................173
Figure 99. USIn I2C Block Diagram................................................................................................................................180
Figure 100. USART2 Block Diagram...............................................................................................................................193
Figure 101. Clock Generation Block Diagram ...........................................................................................................194
Figure 102. Synchronous Mode XCK Timing.............................................................................................................195
Figure 103. A Frame Format .............................................................................................................................................196
Figure 104. Start Bit Sampling .........................................................................................................................................200
Figure 105. Sampling of Data and Parity Bit .............................................................................................................201
Figure 106. Stop Bit Sampling and Next Start Bit Sampling .............................................................................201
Figure 107. SPI Clock Formats when UCPHA = 0...................................................................................................202
Figure 108. SPI Clock Formats when UCPHA = 1...................................................................................................203
Figure 109. Example for RTO in USART2.....................................................................................................................204
Figure 110. 0% Error Baud Rate Block Diagram ......................................................................................................214
Figure 111. IDLE Mode Release Timing by an External Interrupt....................................................................216
Figure 112. STOP Mode Release Timing by External Interrupt.........................................................................217
Figure 113. STOP Mode Release Flow..........................................................................................................................218
Figure 114. Reset Block Diagram....................................................................................................................................220
Figure 115. Fast VDD Rising Time ..................................................................................................................................221

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Figure 116. Internal RESET Release Timing On Power-Up ..................................................................................221
Figure 117. Configuration Timing when Power-on ................................................................................................222
Figure 118. Boot Process Waveform .............................................................................................................................222
Figure 119. Timing Diagram after RESET ....................................................................................................................224
Figure 120. Oscillator generating waveform example ..........................................................................................224
Figure 121. Block Diagram of LVR..................................................................................................................................225
Figure 122. Internal Reset at Power Fail Situation ..................................................................................................225
Figure 123. Configuration Timing When LVR RESET .............................................................................................226
Figure 124. LVI Block Diagram .........................................................................................................................................226
Figure 125. Read Device Internal Checksum (Full Size) .......................................................................................235
Figure 126. Read Device Internal Checksum (User Define Size) ......................................................................236
Figure 127. Flash Memory Map ......................................................................................................................................238
Figure 128. Address Configuration of Flash Memory ...........................................................................................238
Figure 129. The Sequence of Page Program and Erase of Flash Memory .................................................239
Figure 130. The Sequence of Bulk Erase of Flash Memory................................................................................240
Figure 131. ISP Mode...........................................................................................................................................................244
Figure 132. AC Timing .........................................................................................................................................................254
Figure 133. SPI master mode timing (UCPHA = 0, MSB first) ..........................................................................256
Figure 134. SPI/Synchronous master mode timing (UCPHA = 1, MSB first) .............................................256
Figure 135 SPI slave mode timing (UCPHA = 0, MSB first)...............................................................................257
Figure 136 SPI/Synchronous slave mode timing (UCPHA = 1, MSB first) ..................................................257
Figure 137. SPI0/1/2 Timing..............................................................................................................................................259
Figure 138. Waveform for UART0/1 Timing Characteristics ...............................................................................260
Figure 139. Timing Waveform for the UART0/1 Module.....................................................................................260
Figure 140. I2C0/1 Timing..................................................................................................................................................261
Figure 141. Stop Mode Release Timing when Initiated by an Interrupt......................................................262
Figure 142. Stop Mode Release Timing when Initiated by RESETB................................................................262
Figure 143. Crystal/Ceramic Oscillator .........................................................................................................................264
Figure 144. External Clock..................................................................................................................................................264
Figure 145. Crystal Oscillator............................................................................................................................................264
Figure 146. External Clock..................................................................................................................................................265
Figure 147. Clock Timing Measurement at XIN.......................................................................................................265
Figure 148. Clock Timing Measurement at SXIN ....................................................................................................266
Figure 149. Operating Voltage Range..........................................................................................................................266
Figure 150. Recommended Voltage Range................................................................................................................267
Figure 151. RUN (IDD1) Current......................................................................................................................................268
Figure 152. IDLE (IDD2) Current ......................................................................................................................................268
Figure 153. STOP1 (IDD3) Current..................................................................................................................................269
Figure 154. Stop2 (IDD4) Current ...................................................................................................................................269

List of figures A96G140/A96G148/A96A148 User’s manual
14
Figure 155. Debugger (OCD1/OCD2) and Pinouts.................................................................................................270
Figure 156. E-PGM+ (Single Writer) and Pinouts ...................................................................................................271
Figure 157. E-Gang4 and E-Gang6 (for Mass Production) .................................................................................272
Figure 158. PCB Design Guide for On-Board Programming .............................................................................273
Figure 159. On-Chip Debugging System in Block Diagram...............................................................................274
Figure 160. 10-bit Transmission Packet........................................................................................................................275
Figure 161. Data Transfer on Twin Bus ........................................................................................................................276
Figure 162. Bit Transfer on Serial Bus...........................................................................................................................276
Figure 163. Start and Stop Condition...........................................................................................................................276
Figure 164. Acknowledge on Serial Bus ......................................................................................................................277
Figure 165. Clock Synchronization during Wait Procedure ................................................................................277
Figure 166. Connection of Transmission .....................................................................................................................278
Figure 167 48 LQFP Package Outline ...........................................................................................................................279
Figure 168 48 QFN Package Outline.............................................................................................................................280
Figure 169 44 MQFP Package Outline .........................................................................................................................281
Figure 170 32 LQFP Package Outline ...........................................................................................................................282
Figure 171 32 SOP Package Outline .............................................................................................................................283
Figure 172 28 SOP Package Outline .............................................................................................................................284
Figure 173 28 TSSOP Package Outline ........................................................................................................................285
Figure 174. A96G140/A96G148/A96A148 Device Numbering Nomenclature...........................................287

A96G140/A96G148/A96A148 User’s manual List of tables
15
List of tables
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts ......................................... 18
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued)................ 19
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued)................ 20
Table 2. Normal Pin Description........................................................................................................................................ 27
Table 2. Normal Pin Description (Continue) ................................................................................................................ 28
Table 2. Normal Pin Description (Continue) ................................................................................................................ 29
Table 2. Normal Pin Description (Continue) ................................................................................................................ 30
Table 2. Normal Pin Description (Continue) ................................................................................................................ 31
Table 3. SFR Map Summary ................................................................................................................................................ 38
Table 3. SFR Map Summary (Continued) ...................................................................................................................... 39
Table 4. XSFR Map Summary.............................................................................................................................................. 39
Table 5. SFR Map...................................................................................................................................................................... 40
Table 5. SFR Map (continued) ............................................................................................................................................ 41
Table 5. SFR Map (continued) ............................................................................................................................................ 42
Table 5. SFR Map (continued) ............................................................................................................................................ 43
Table 6. XSFR Map ................................................................................................................................................................... 44
Table 7. Port Register Map................................................................................................................................................... 48
Table 8. Interrupt Vector Address Table......................................................................................................................... 68
Table 9. Interrupt Register Map......................................................................................................................................... 75
Table 10. Clock Generator Register Map....................................................................................................................... 83
Table 11. Basic Interval Timer Register Map................................................................................................................ 86
Table 12. Watchdog Timer Register Map...................................................................................................................... 89
Table 13. Watch Timer Register Map .............................................................................................................................. 92
Table 14. Timer 0 Operating Mode ................................................................................................................................. 94
Table 15. Timer 0 Register Map.......................................................................................................................................100
Table 16. TIMER 1 Operating Modes ............................................................................................................................102
Table 17. TIMER 1 Register Map .....................................................................................................................................108
Table 18. TIMER 2 Operating Modes ............................................................................................................................112
Table 19. TIMER 2 Register Map .....................................................................................................................................118
Table 20. TIMER 3 Operating Modes ............................................................................................................................121
Table 21. TIMER 3 Register Map .....................................................................................................................................127
Table 22. TIMER 4 Operating Modes ............................................................................................................................131
Table 23. TIMER 4 Register Map .....................................................................................................................................137
Table 24. TIMER 5 Operating Modes ............................................................................................................................140
Table 25. TIMER 5 Register Map .....................................................................................................................................146
Table 26. Buzzer Frequency at 8MHz............................................................................................................................149
Table 27. Buzzer Driver Register Map...........................................................................................................................150

List of tables A96G140/A96G148/A96A148 User’s manual
16
Table 28. ADC Register Map .............................................................................................................................................154
Table 29. Equations for Calculating USIn Baud Rate Register Setting ..........................................................159
Table 30. CPOLn Functionality..........................................................................................................................................167
Table 31. USI Register Map................................................................................................................................................180
Table 32. Example1 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies ..190
Table 33. Example2 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies ..191
Table 34. Equations for Calculating Baud Rate Register Setting......................................................................194
Table 35. CPOL Functionality ............................................................................................................................................202
Table 36. Example Condition of RTO.............................................................................................................................204
Table 37. USART2 Register Map......................................................................................................................................205
Table 38. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies............................212
Table 39. Peripheral Operation Status during Power Down Mode.................................................................215
Table 40. Power Down Operation Register Map .....................................................................................................218
Table 41. Hardware Setting Values in Reset State ..................................................................................................220
Table 42. Boot Process Description................................................................................................................................223
Table 43. Reset Operation Register Map.....................................................................................................................227
Table 44. Flash Control and Status Register Map ...................................................................................................230
Table 45. Program and Erase Time ................................................................................................................................237
Table 46. Operation Mode .................................................................................................................................................244
Table 47. Mode entrance method for ISP ..................................................................................................................244
Table 48. Security Policy using Lock Bits.....................................................................................................................245
Table 49. Absolute Maximum Ratings ..........................................................................................................................248
Table 50. Recommended Operating Conditions......................................................................................................249
Table 51. A/D Converter Characteristics ......................................................................................................................249
Table 52. Power-on Reset Characteristics....................................................................................................................250
Table 53. LVR and LVI Characteristics............................................................................................................................250
Table 54. High Speed Internal RC Oscillator Characteristics ..............................................................................251
Table 55. Low Speed Internal RC Oscillator Characteristics ...............................................................................251
Table 56. DC Characteristics ..............................................................................................................................................252
Table 57. AC Characteristics...............................................................................................................................................253
Table 58. USART Timing Characteristics in SYNC. Or SPI Mode Operations .............................................255
Table 59. SPI0/1/2 Characteristics...................................................................................................................................258
Table 60. UART0/1 Characteristics ..................................................................................................................................259
Table 61. I2C0/1 Characteristics.......................................................................................................................................260
Table 62. Data Retention Voltage in Stop Mode.....................................................................................................261
Table 63. Internal Flash Rom Characteristics .............................................................................................................262
Table 64. Main Clock Oscillator Characteristics........................................................................................................263
Table 65. Sub Clock Oscillator Characteristics ..........................................................................................................264
Table 66. Main Oscillation Stabilization Characteristics........................................................................................265

A96G140/A96G148/A96A148 User’s manual List of tables
17
Table 67. Sub Oscillation Stabilization Characteristics ..........................................................................................266
Table 68. Pins for Flash Programming..........................................................................................................................272
Table 69. OCD Features .......................................................................................................................................................274
Table 70. A96G140/A96G148/A96A148 Device Ordering Information..........................................................286
Table 71. Instruction Table .................................................................................................................................................288

1. Description A96G140/A96G148/A96A148 User’s manual
18
1Description
A96G140/A96G148/A96A148 is an advanced CMOS 8-bit microcontroller with 64/32Kbytes of FLASH.
This is a powerful microcontroller which provides a highly flexible and cost-effective solution to many
embedded control applications.
1.1 Device overview
In this section, features of A96G140/A96G148/A96A148 and peripheral counts are introduced.
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts
Peripherals
Description
Core
CPU
8-bit CISC core (M8051, 2 clocks per cycle)
Interrupt
Up to 23 peripheral interrupts supported.
EINT0 to 7, EINT8, EINT10, EINT11, EINT12 (5)
Timer (0/1/2/3/4/5) (6)
WDT (1)
BIT (1)
WT (1)
USART Rx/Tx (2)
USI 2-ch. *Rx/Tx/I2C (6)
ADC (1)
LVI (1)
Memory
ROM (FLASH)
capacity
64/32 Kbytes FLASH with self-read and write capability
In-system programming (ISP)
Endurance: 30,000times
IRAM
256Bytes
XRAM
2304Bytes
Programmable pulse generation
Pulse generation (by T1/T2/T3/T4/T5)
8-bit PWM (by T0)
Buzzer
8-bit ×1-ch
Minimum instruction execution
time
125ns (@ 16MHz main clock)
61us (@ 32.768kHz sub clock)
Power down mode
STOP mode
IDLE mode
General Purpose I/O (GPIO)
Normal I/O: 46ports
High sink current port: 8ports P3[7:0]

A96G140/A96G148/A96A148 User’s manual 1. Description
19
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued)
Peripherals
Description
Reset
Power
on reset
Reset release level: 1.2V
Low voltage
reset
16 levels detect
1.61/1.68/1.77/1.88/2.00/2.13/2.28/2.46/2.68/2.81/3.06/
3.21/3.56/3.73/3.91/4.25V
Low voltage indicator
13 levels detect
1.88/2.00/2.13/2.28/2.46/2.68/2.81/3.06/3.21/3.56/3.73/
3.91/4.25V
Watch Timer (WT)
3.91ms/0.25s/0.5s/1s/1min interval at 32.768kHz
Timer/counter
Basic interval timer (BIT) 8-bit x 1-ch.
Watchdog timer (WDT) 8-bit x 1-ch.
8-bit x 1-ch (T0), 16-bit x 5-ch (T1/T2/ T3/T4/T5)
Communication
function
USART2
8-bit USART x 1-ch or 8-bit SPI x 1-ch
Receiver timer out (RTO)
0% error baud rate
USI0/1
USART + SPI + I2C
8-bit USART x 2-ch or 8-bit SPI x 2-ch or I2C x 2-ch
12-bit A/D converter
16 input channels
Oscillator type
4MHz to 12MHz crystal or ceramic for main clock
32.768kHz Crystal for sub clock
Internal RC oscillator
HSI 32MHz ±1.5% (TA= 0~ +50°C)
HSI 32MHz ±2.0% (TA=-10~ +70°C)
HSI 32MHz ±2.5% (TA=-40~ +85°C)
HSI 32MHz ±5.0% (TA=-40~ +105°C)
LSI 128kHz ±20% (TA= -40~ +85°C)
LSI 128kHz ±30% (TA= -40~ +105°C)
Operating voltage
and frequency
1.8V to 5.5V @ 32.768kHz with crystal
2.2V to 5.5V @ 4MHz to 10MHz with crystal
2.4V to 5.5V @ 4MHz to 12MHz with crystal
1.8V to 5.5V @ 0.5MHz to 8.0MHz with internal RC
2.0V to 5.5V @ 0.5MHz to 16.0MHz with internal RC
Operating temperature
-40℃to +85℃, -40℃to +105℃

1. Description A96G140/A96G148/A96A148 User’s manual
20
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued)
Peripherals
Description
Package
Pb-free packages
48 LQFP 7x7 mm, 48 QFN 6x6 mm
44 MQFP 10x10 mm
32 LQFP, 32 SOP
28 SOP, 28 TSSOP