Abov A96G140 User manual

Global Top Smart MCU Innovator
www.abovsemi.com
A96G140/A96G148/A96A148
User’s Manual
16 MHz 8-bit A96G140/A96G148/A96A148 Microcontroller
64/32 Kbyte Flash memory, 12-bit ADC, 6 Timers, USART,
USI, High Current Port
Version 1.30
Introduction
This user’s manual targets application developers who use A96G140/A96G148/A96A148 for their
specific needs. It provides complete information of how to use A96G140/A96G148/A96A148 device.
Standard functions and blocks including corresponding register information of A96G140/ A96G148/
A96A148 are introduced in each chapter, while instruction set is in Appendix.
A96G140/A96G148/A96A148 is based on M8051 core and provides standard features of 8051 such as
8-bit ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit
data bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
64Kbytes of FLASH, 256bytes of IRAM, 2304bytes of XRAM, general purpose I/O, basic interval timer,
watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 16-bit PWM output, watch
timer, buzzer driving port, USI, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator and
clock circuitry.
As a field proven best seller, A96G140/A96G148/A96A148 has been sold more than 3 billion units up
to now, and introduces rich features such as excellent noise immunity, code optimization, cost
effectiveness, and so on.
Reference document
A96G140/A96G148/A96A148 programming tools and manuals released by ABOV: They are
available at ABOV website, www.abovsemi.com.
SDK-51 User’s guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel’s 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentorwebsite: https://www.mentor.com/products/ip/peripheral/microcontroller/

Contents A96G140/A96G148/A96A148 User’s manual
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Contents
Introduction..............................................................................................................................................1
Reference document...............................................................................................................................1
1Description ...................................................................................................................................13
1.1 Device overview................................................................................................................13
1.2 A96G140/A96G148/A96A148 block diagram ...................................................................16
2Pinouts and pin description..........................................................................................................17
2.1 Pinouts ..............................................................................................................................17
2.2 Pin description...................................................................................................................22
3Port structures..............................................................................................................................27
4Central Processing Unit (CPU) ....................................................................................................29
4.1 Architecture and registers .................................................................................................29
4.2 Addressing ........................................................................................................................31
4.3 Instruction set....................................................................................................................32
5Memory organization....................................................................................................................34
5.1 Program memory...............................................................................................................34
5.2 Data memory.....................................................................................................................35
5.3 External data memory.......................................................................................................37
5.4 SFR map...........................................................................................................................38
5.4.1 SFR map summary...............................................................................................38
5.4.2 SFR map...............................................................................................................40
5.4.3 Compiler compatible SFR.....................................................................................45
6I/O ports .......................................................................................................................................47
6.1 Port register.......................................................................................................................47
6.1.1 Data register (Px) .................................................................................................47
6.1.2 Direction register (PxIO).......................................................................................47
6.1.3 Pull-up register selection register (PxPU) ............................................................47
6.1.4 Open-drain Selection Register (PxOD) ................................................................47
6.1.5 De-bounce Enable Register (PxDB).....................................................................47
6.1.6 Port Function Selection Register (PxFSR)...........................................................47
6.1.7 Register Map ........................................................................................................48
6.2 P0 port...............................................................................................................................49
6.2.1 P0 port description................................................................................................49
6.2.2 Register description for P0...................................................................................49
6.3 P1 port...............................................................................................................................52
6.3.1 P1 port description................................................................................................52
6.3.2 Register description for P1...................................................................................52
6.4 P2 port...............................................................................................................................56
6.4.1 P2 port description................................................................................................56
6.4.2 Register description for P2...................................................................................56
6.5 P3 port...............................................................................................................................58
6.5.1 P3 port description................................................................................................58
6.5.2 Register description for P3...................................................................................58
6.6 P4 port...............................................................................................................................60
6.6.1 P4 port description................................................................................................60
6.6.2 Register description for P4...................................................................................60
6.7 P5 port...............................................................................................................................62
6.7.1 P5 port description................................................................................................62
6.7.2 Register description for P5...................................................................................62

A96G140/A96G148/A96A148 User’s manual Contents
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7Interrupt controller........................................................................................................................64
7.1 External interrupt...............................................................................................................65
7.2 Block diagram....................................................................................................................66
7.3 Interrupt vector table .........................................................................................................68
7.4 Interrupt sequence ............................................................................................................69
7.5 Effective timing after controlling interrupt bit.....................................................................70
7.6 Multi-interrupt ....................................................................................................................71
7.7 Interrupt enable accept timing...........................................................................................72
7.8 Interrupt service routine address.......................................................................................73
7.9 Saving/restore general purpose registers.........................................................................73
7.10 Interrupt timing ..................................................................................................................74
7.11 Interrupt register overview.................................................................................................74
7.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) .................................................74
7.11.2 Interrupt Priority Register (IP and IP1) .................................................................74
7.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1)..................................75
7.11.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, and EIPOL1) .............75
7.11.5 Register map ........................................................................................................75
7.11.6 Interrupt register description.................................................................................75
8Clock generator............................................................................................................................82
8.1 Clock generator block diagram .........................................................................................82
8.2 Register map.....................................................................................................................83
8.3 Register description ..........................................................................................................83
9Basic interval timer.......................................................................................................................86
9.1 BIT block diagram .............................................................................................................86
9.2 BIT register map................................................................................................................86
9.3 BIT register description .....................................................................................................87
10 Watchdog timer............................................................................................................................88
10.1 WDT interrupt timing waveform.........................................................................................88
10.2 WDT block diagram...........................................................................................................89
10.3 Register map.....................................................................................................................89
10.4 Register description ..........................................................................................................89
11 Watch timer..................................................................................................................................91
11.1 WT block diagram .............................................................................................................91
11.2 Register map.....................................................................................................................91
11.3 Watch timer register description........................................................................................92
12 Timer 0/1/2/3/4/5..........................................................................................................................94
12.1 Timer 0 ..............................................................................................................................94
12.1.1 8-bit timer/counter mode.......................................................................................94
12.1.2 8-bit PWM mode...................................................................................................96
12.1.3 8-bit capture mode................................................................................................98
12.1.4 Timer 0 block diagram........................................................................................100
12.1.5 Register map ......................................................................................................100
12.1.6 Register description............................................................................................100
12.2 Timer 1 ............................................................................................................................102
12.2.1 16-bit timer/counter mode...................................................................................102
12.2.2 16-bit capture mode............................................................................................104
12.2.3 16-bit PPG mode................................................................................................105
12.2.4 16-bit timer 1 block diagram...............................................................................108
12.2.5 Register map ......................................................................................................108
12.2.6 Register description............................................................................................108

Contents A96G140/A96G148/A96A148 User’s manual
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12.3 Timer 2 ............................................................................................................................111
12.3.1 16-bit timer/counter mode...................................................................................112
12.3.2 16-bit capture mode............................................................................................114
12.3.3 16-bit PPG mode................................................................................................116
12.3.4 16-bit timer 2 block diagram...............................................................................118
12.3.5 Register map ......................................................................................................118
12.3.6 Register description............................................................................................118
12.4 Timer 3 ............................................................................................................................121
12.4.1 16-bit timer/counter mode...................................................................................121
12.4.2 16-bit capture mode............................................................................................123
12.4.3 16-bit PPG mode................................................................................................125
12.4.4 16-bit timer 3 block diagram...............................................................................128
12.4.5 Register map ......................................................................................................128
12.4.6 Register description............................................................................................128
12.5 Timer 4 ............................................................................................................................131
12.5.1 16-bit timer/counter mode...................................................................................132
12.5.2 16-bit capture mode............................................................................................134
12.5.3 16-bit PPG mode................................................................................................136
12.5.4 16-bit timer 4 block diagram...............................................................................138
12.5.5 Register map ......................................................................................................138
12.5.6 Register description............................................................................................138
12.6 Timer 5 ............................................................................................................................141
12.6.1 16-bit timer/counter mode...................................................................................141
12.6.2 16-bit capture mode............................................................................................143
12.6.3 16-bit PPG mode................................................................................................144
12.6.4 16-bit timer 5 block diagram...............................................................................147
12.6.5 Register map ......................................................................................................147
12.6.6 Register description............................................................................................147
13 Buzzer driver..............................................................................................................................150
13.1 Buzzer driver block diagram............................................................................................150
13.2 Register map...................................................................................................................150
13.3 Register description ........................................................................................................151
14 12-bit ADC..................................................................................................................................152
14.1 Conversion timing............................................................................................................152
14.2 Block diagram..................................................................................................................152
14.3 ADC operation.................................................................................................................154
14.4 Register map...................................................................................................................155
14.5 Register description ........................................................................................................155
15 USI (USART + SPI + I2C)..........................................................................................................158
15.1 USIn UART mode............................................................................................................158
15.2 USIn UART block diagram..............................................................................................159
15.3 USIn clock generation.....................................................................................................160
15.4 USIn external clock (SCKn) ............................................................................................161
15.5 USIn synchronous mode operation.................................................................................161
15.6 USIn UART data format ..................................................................................................161
15.7 USIn UART parity bit.......................................................................................................162
15.8 USIn UART transmitter ...................................................................................................163
15.8.1 USIn UART sending TX data..............................................................................163
15.8.2 USIn UART transmitter flag and interrupt...........................................................163
15.8.3 USIn UART parity generator...............................................................................164

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15.8.4 USIn UART disabling transmitter .......................................................................164
15.9 USIn UART receiver........................................................................................................164
15.9.1 USIn UART receiver RX data.............................................................................164
15.9.2 USIn UART receiver flag and interrupt...............................................................165
15.9.3 USIn UART parity checker .................................................................................165
15.9.4 USIn UART disabling receiver............................................................................165
15.9.5 USIn Asynchronous data reception....................................................................165
15.10 USIn SPI mode................................................................................................................167
15.11 USIn SPI clock formats and timing..................................................................................168
15.12 USIn SPI block diagram..................................................................................................170
15.13USIn I2C mode................................................................................................................170
15.14 USIn I2C bit transfer........................................................................................................171
15.15 USIn I2C start/ repeated start/ stop.................................................................................171
15.16 USIn I2C data transfer ....................................................................................................172
15.17USIn I2C acknowledge....................................................................................................172
15.18 USIn I2C synchronization/ arbitration .............................................................................173
15.19 USIn I2C operation..........................................................................................................174
15.19.1USIn I2C master transmitter...............................................................................175
15.19.2USIn I2C master receiver...................................................................................177
15.19.3USIn I2C slave transmitter..................................................................................178
15.19.4USIn I2C slave receiver......................................................................................179
15.20 USIn I2C block diagram ..................................................................................................181
15.21 Register map...................................................................................................................181
15.22 USIn register description.................................................................................................182
15.23 Baud rate settings (example) ..........................................................................................190
16 USART2.....................................................................................................................................193
16.1 Block diagram..................................................................................................................194
16.2 Clock generation .............................................................................................................195
16.3 External clock (XCK).......................................................................................................196
16.4 Synchronous mode operation.........................................................................................196
16.5 Data format......................................................................................................................197
16.6 Parity bit ..........................................................................................................................198
16.7 USART2 transmitter........................................................................................................198
16.7.1 Sending Tx data .................................................................................................198
16.7.2 Transmitter flag and interrupt .............................................................................198
16.7.3 Parity generator..................................................................................................199
16.7.4 Disabling transmitter...........................................................................................199
16.8 USART2 receiver ............................................................................................................199
16.8.1 Receiving Rx data ..............................................................................................199
16.8.2 Receiver flag and interrupt .................................................................................200
16.8.3 Parity checker.....................................................................................................200
16.8.4 Disabling receiver...............................................................................................200
16.8.5 Asynchronous data reception.............................................................................201
16.9 SPI mode.........................................................................................................................202
16.9.1 SPI clock formats and timing..............................................................................203
16.10 Receiver time out (RTO) .................................................................................................205
16.11 Register map...................................................................................................................206
16.12 Register description ........................................................................................................206
16.13 Baud rate settings (example) ..........................................................................................214
16.14 0% error baud rate ..........................................................................................................215

Contents A96G140/A96G148/A96A148 User’s manual
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17 Power down operation ...............................................................................................................217
17.1 Peripheral operation in IDLE/ STOP mode.....................................................................217
17.2 IDLE mode ......................................................................................................................218
17.3 STOP mode.....................................................................................................................218
17.4 Released operation of STOP mode................................................................................219
17.5 Register map...................................................................................................................220
17.6 Register description ........................................................................................................220
18 Reset..........................................................................................................................................222
18.1 Reset block diagram .......................................................................................................222
18.2 Power on reset................................................................................................................222
18.3 External resetb input .......................................................................................................225
18.4 Low voltage reset process ..............................................................................................226
18.5 LVI block diagram............................................................................................................228
18.6 Register Map...................................................................................................................229
18.7 Reset Operation Register Description.............................................................................229
19 Memory programming................................................................................................................232
19.1 Flash control and status registers...................................................................................232
19.1.1 Register map ......................................................................................................232
19.1.2 Register description............................................................................................233
19.2 Memory map ...................................................................................................................239
19.2.1 Flash memory map.............................................................................................239
19.3 Serial in-system program mode......................................................................................240
19.3.1 Flash operation...................................................................................................240
19.4 Mode entrance method of ISP mode ..............................................................................246
19.4.1 Mode entrance method for ISP ..........................................................................246
19.5 Security ...........................................................................................................................247
19.6 Configure option..............................................................................................................247
20 Development tools .....................................................................................................................250
20.1 Compiler..........................................................................................................................250
20.2 Core and debug tool information.....................................................................................251
20.2.1 Feature of 94/96/97 series core .........................................................................251
20.2.2 OCD type of 94/96/97 series core......................................................................253
20.2.3 Interrupt priority of 94/96/97 series core.............................................................254
20.2.4 Extended stack pointer of 94/96/97 series core.................................................255
20.3 OCD (On-chip debugger) emulator and debugger..........................................................256
20.3.1 On-chip debug system........................................................................................258
20.3.2 Two-wire communication protocol......................................................................260
20.4 Programmers...................................................................................................................264
20.4.1 E-PGM+..............................................................................................................264
20.4.2 OCD emulator.....................................................................................................264
20.4.3 Gang programmer ..............................................................................................265
20.5 Flash programming .........................................................................................................266
20.5.1 On-board programming......................................................................................266
20.6 Connection of transmission.............................................................................................267
20.7 Circuit design guide.........................................................................................................268
Appendix .............................................................................................................................................270
Instruction table..........................................................................................................................270
Revision history...................................................................................................................................276

A96G140/A96G148/A96A148 User’s manual List of figures
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List of figures
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued)..............15
Figure 1. A96G140/A96G148/A96A148 Block Diagram .......................................................................16
Figure 2. A96G140/A96G148 48LQFP/48QFN Pin Assignment...........................................................17
Figure 3. A96G140/A96G148 44MQFP-1010 Pin Assignment .............................................................18
Figure 4. A96G140/A96G148 32LQFP Pin Assignment .......................................................................19
Figure 5. A96G140/A96G148 32SOP Pin Assignment .........................................................................20
Figure 6. A96G140/A96G148 28SOP Pin Assignment .........................................................................20
Figure 7. A96A148 28SOP Pin Assignment..........................................................................................21
Figure 8. General Purpose I/O Port ......................................................................................................27
Figure 9. External Interrupt I/O Port ......................................................................................................28
Figure 10. M8051EW Architecture ........................................................................................................29
Figure 11. Program Memory Map .........................................................................................................35
Figure 12. Data Memory Map ...............................................................................................................36
Figure 13. Lower 128bytes of RAM ......................................................................................................37
Figure 14. XDATA Memory Area ...........................................................................................................38
Figure 15. Interrupt Group Priority Level...............................................................................................65
Figure 16. External Interrupt Description ..............................................................................................66
Figure 17. Interrupt Controller Block Diagram ......................................................................................67
Figure 18. Interrupt Sequence Flow......................................................................................................70
Figure 19. Effective Timing of Interrupt Enable Register ......................................................................71
Figure 20. Effective Timing of Interrupt Flag Register...........................................................................71
Figure 21. Effective Timing of Multi-Interrupt ........................................................................................72
Figure 22. Interrupt Response Timing Diagram ....................................................................................73
Figure 23. Correspondence between Vector Table Address and the Entry Address of ISR .................73
Figure 24. Saving/Restore Process Diagram and Sample Source.......................................................73
Figure 25. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction ...............................74
Figure 26. Clock Generator Block Diagram ..........................................................................................83
Figure 27. Basic Interval Timer Block Diagram.....................................................................................86
Figure 28. Watch Dog Timer Interrupt Timing Waveform......................................................................88
Figure 29. Watch Dog Timer Block Diagram.........................................................................................89
Figure 30. Watch Timer Block Diagram ................................................................................................91
Figure 31. 8-bit Timer/Counter Mode for Timer 0..................................................................................95
Figure 32. 8-bit Timer/Counter 0 Example ............................................................................................95
Figure 33. 8-bit PWM Mode for Timer 0................................................................................................96
Figure 34. PWM Output Waveforms in PWM Mode for Timer 0 ...........................................................97
Figure 35. 8-bit Capture Mode for Timer 0............................................................................................98
Figure 36. Input Capture Mode Operation for Timer 0 ..........................................................................99
Figure 37. Express Timer Overflow in Capture Mode ...........................................................................99
Figure 38. 8-bit Timer 0 Block Diagram ..............................................................................................100
Figure 39. 16-bit Timer/Counter Mode of Timer 1 ...............................................................................103
Figure 40. 16-bit Timer/Counter Mode Operation Example ................................................................103
Figure 41. 16-bit Capture Mode of Timer 1 .........................................................................................104
Figure 42. 16-bit Capture Mode Operation Example ..........................................................................105
Figure 43. 16-bit PPG Mode of Timer 1 ..............................................................................................106
Figure 44. 16-bit PPG Mode Operation Example ...............................................................................107
Figure 45. 16-bit Timer 1 Block Diagram ............................................................................................108
Figure 46. 16-bit Timer/Counter Mode of Timer 2 ...............................................................................113
Figure 47. 16-bit Timer/Counter Mode Operation Example ................................................................113

List of figures A96G140/A96G148/A96A148 User’s manual
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Figure 48. 16-bit Capture Mode of Timer 2 .........................................................................................114
Figure 49. 16-bit Capture Mode Operation Example ..........................................................................115
Figure 50. Express Timer Overflow in Capture Mode .........................................................................115
Figure 51. 16-bit PPG Mode of Timer 2 ..............................................................................................116
Figure 52. 16-bit PPG Mode Operation Example ...............................................................................117
Figure 53. 16-bit Timer 2 Block Diagram ............................................................................................118
Figure 54. 16-bit Timer/Counter Mode of Timer 3 ...............................................................................122
Figure 55. 16-bit Timer/Counter Mode Operation Example ................................................................122
Figure 56. 16-bit Capture Mode of Timer 3 .........................................................................................123
Figure 57. 16-bit Capture Mode Operation Example ..........................................................................124
Figure 58. Express Timer Overflow in Capture Mode .........................................................................124
Figure 59. 16-bit PPG Mode of Timer 3 ..............................................................................................125
Figure 60. 16-bit PPG Mode Operation Example ...............................................................................126
Figure 61. 16-bit Timer 3 Block Diagram ............................................................................................128
Figure 62. 16-bit Timer/Counter Mode of Timer 4 ...............................................................................133
Figure 63. 16-bit Timer/Counter Mode Operation Example ................................................................133
Figure 64. 16-bit Capture Mode of Timer 4 .........................................................................................134
Figure 65. 16-bit Capture Mode Operation Example ..........................................................................135
Figure 66. Express Timer Overflow in Capture Mode .........................................................................135
Figure 67. 16-bit PPG Mode of Timer 4 ..............................................................................................136
Figure 68. 16-bit PPG Mode Operation Example ...............................................................................137
Figure 69. 16-bit Timer 4 Block Diagram ............................................................................................138
Figure 70. 16-bit Timer/Counter Mode of Timer 5 ...............................................................................142
Figure 71. 16-bit Timer/Counter Mode Operation Example ................................................................142
Figure 72. 16-bit Capture Mode of Timer 5 .........................................................................................143
Figure 73. 16-bit Capture Mode Operation Example ..........................................................................144
Figure 74. Express Timer Overflow in Capture Mode .........................................................................144
Figure 75. 16-bit PPG Mode of Timer 5 ..............................................................................................145
Figure 76. 16-bit PPG Mode Operation Example ...............................................................................146
Figure 77. 16-bit Timer 5 Block Diagram ............................................................................................147
Figure 78. Buzzer Driver Block Diagram.............................................................................................150
Figure 79. 12-bit ADC Block Diagram .................................................................................................153
Figure 80. A/D Analog Input Pin with a Capacitor ...............................................................................153
Figure 81. A/D Power (AVREF) Pin with a Capacitor..........................................................................153
Figure 82. Control Registers and Align Bits ........................................................................................154
Figure 83. ADC Operation Flow Sequence.........................................................................................155
Figure 84. USIn USART Block Diagram (n = 0 and 1)........................................................................159
Figure 85. Clock Generation Block Diagram (USIn) ...........................................................................160
Figure 86. Synchronous Mode SCKn Timing (USIn) ..........................................................................161
Figure 87. Frame Formats (USIn) .......................................................................................................162
Figure 88. Asynchronous Start Bit Sampling (USIn) ...........................................................................166
Figure 89. Asynchronous Sampling of Data and Parity Bit (USIn)......................................................167
Figure 90. Stop Bit Sampling and Next Start Bit Sampling (USIn) .....................................................167
Figure 91. USIn SPI Clock Formats when CPHAn = 0 .......................................................................168
Figure 92. USIn SPI Clock Formats when CPHAn = 1 .......................................................................169
Figure 93. USIn SPI Block Diagram (n = 0 and 1) ..............................................................................170
Figure 94. Bit Transfer on the I2C-Bus (USIn)....................................................................................171
Figure 95. START and STOP Condition (USIn) ..................................................................................172
Figure 96. Data Transfer on the I2C-Bus (USIn).................................................................................172
Figure 97. Acknowledge on the I2C-Bus (USIn) .................................................................................173

A96G140/A96G148/A96A148 User’s manual List of figures
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Figure 98. Clock Synchronization during Arbitration Procedure (USIn)..............................................174
Figure 99. Arbitration Procedure of Two Masters (USIn) ....................................................................174
Figure 100. USIn I2C Block Diagram ..................................................................................................181
Figure 101. USART2 Block Diagram ..................................................................................................194
Figure 102. Clock Generation Block Diagram.....................................................................................195
Figure 103. Synchronous Mode XCK Timing......................................................................................196
Figure 104. A Frame Format ...............................................................................................................197
Figure 105. Start Bit Sampling ............................................................................................................201
Figure 106. Sampling of Data and Parity Bit.......................................................................................202
Figure 107. Stop Bit Sampling and Next Start Bit Sampling...............................................................202
Figure 108. SPI Clock Formats when UCPHA = 0..............................................................................203
Figure 109. SPI Clock Formats when UCPHA = 1..............................................................................204
Figure 110. Example for RTO in USART2 ..........................................................................................205
Figure 111. 0% Error Baud Rate Block Diagram.................................................................................216
Figure 112. IDLE Mode Release Timing by an External Interrupt.......................................................218
Figure 113. STOP Mode Release Timing by External Interrupt ..........................................................219
Figure 114. STOP Mode Release Flow...............................................................................................220
Figure 115. Reset Block Diagram .......................................................................................................222
Figure 116. Fast VDD Rising Time......................................................................................................223
Figure 117. Internal RESET Release Timing On Power-Up ...............................................................223
Figure 118. Configuration Timing when Power-on ..............................................................................224
Figure 119. Boot Process Waveform ..................................................................................................224
Figure 120. Timing Diagram after RESET ..........................................................................................226
Figure 121. Oscillator generating waveform example ........................................................................226
Figure 122. Block Diagram of LVR......................................................................................................227
Figure 123. Internal Reset at Power Fail Situation .............................................................................227
Figure 124. Configuration Timing When LVR RESET.........................................................................228
Figure 125. LVI Block Diagram ...........................................................................................................228
Figure 126. Read Device Internal Checksum (Full Size) ....................................................................237
Figure 127. Read Device Internal Checksum (User Define Size).......................................................238
Figure 128. Flash Memory Map ..........................................................................................................240
Figure 129. Address Configuration of Flash Memory .........................................................................240
Figure 130. The Sequence of Page Program and Erase of Flash Memory........................................241
Figure 131. The Sequence of Bulk Erase of Flash Memory ...............................................................242
Figure 132. ISP Mode .........................................................................................................................246
Figure 133. Configuration of Extended Stack Pointer.........................................................................255
Figure 134. OCD 1 and OCD 2 Connector Pin Diagram ....................................................................257
Figure 135. Debugger (OCD1/OCD2) and Pinouts ............................................................................258
Figure 136. On-Chip Debugging System Block Diagram ...................................................................259
Figure 137. Timing Diagram of Debug Mode Entry ............................................................................259
Figure 138. 10-bit Transmission Packet..............................................................................................260
Figure 139. Data Transfer on OCD .....................................................................................................261
Figure 140. Bit Transfer on Serial Bus ................................................................................................262
Figure 141. Start and Stop Conditions ................................................................................................262
Figure 142. Acknowledge on Serial Bus .............................................................................................263
Figure 143. Clock Synchronization during Wait Procedure ................................................................263
Figure 144. E-PGM+ (Single Writer) and Pinouts ...............................................................................264
Figure 145. E-Gang4 and E-Gang6 (for Mass Production) ................................................................265
Figure 146. Connection of Transmission ............................................................................................267
Figure 147. PCB Design Guide for On-Board Programming ..............................................................269

List of figures A96G140/A96G148/A96A148 User’s manual
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A96G140/A96G148/A96A148 User’s manual List of tables
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List of tables
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts .................................13
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued) ..............14
Table 3. Normal Pin Description............................................................................................................22
Table 4. SFR Map Summary .................................................................................................................38
Table 5. XSFR Map Summary ..............................................................................................................39
Table 6. SFR Map .................................................................................................................................40
Table 7. XSFR Map ...............................................................................................................................44
Table 8. Port Register Map....................................................................................................................48
Table 9. Interrupt Vector Address Table ................................................................................................68
Table 10. Interrupt Register Map...........................................................................................................75
Table 11. Clock Generator Register Map ..............................................................................................83
Table 12. Basic Interval Timer Register Map ........................................................................................86
Table 13. Watchdog Timer Register Map ..............................................................................................89
Table 14. Watch Timer Register Map ....................................................................................................92
Table 15. Timer 0 Operating Mode........................................................................................................94
Table 16. Timer 0 Register Map ..........................................................................................................100
Table 17. TIMER 1 Operating Modes..................................................................................................102
Table 18. TIMER 1 Register Map ........................................................................................................108
Table 19. TIMER 2 Operating Modes..................................................................................................112
Table 20. TIMER 2 Register Map ........................................................................................................118
Table 21. TIMER 3 Operating Modes..................................................................................................121
Table 22. TIMER 3 Register Map ........................................................................................................128
Table 23. TIMER 4 Operating Modes..................................................................................................132
Table 24. TIMER 4 Register Map ........................................................................................................138
Table 25. TIMER 5 Operating Modes..................................................................................................141
Table 26. TIMER 5 Register Map ........................................................................................................147
Table 27. Buzzer Frequency at 8MHz.................................................................................................150
Table 28. Buzzer Driver Register Map ................................................................................................151
Table 29. ADC Register Map...............................................................................................................155
Table 30. Equations for Calculating USIn Baud Rate Register Setting ..............................................160
Table 31. CPOLn Functionality............................................................................................................168
Table 32. USI Register Map ................................................................................................................181
Table 33. Example1 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies ..191
Table 34. Example2 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies ..192
Table 35. Equations for Calculating Baud Rate Register Setting........................................................195
Table 36. CPOL Functionality..............................................................................................................203
Table 37. Example Condition of RTO..................................................................................................205
Table 38. USART2 Register Map ........................................................................................................206
Table 39. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies .......................214
Table 40. Peripheral Operation Status during Power Down Mode .....................................................217
Table 41. Power Down Operation Register Map.................................................................................220
Table 42. Hardware Setting Values in Reset State .............................................................................222
Table 43. Boot Process Description ....................................................................................................225
Table 44. Reset Operation Register Map ............................................................................................229
Table 45. Flash Control and Status Register Map ..............................................................................232
Table 46. Program and Erase Time ....................................................................................................239
Table 47. Operation Mode...................................................................................................................246
Table 48. Mode entrance method for ISP ...........................................................................................246

List of tables A96G140/A96G148/A96A148 User’s manual
12
Table 49. Security Policy using Lock Bits............................................................................................247
Table 50. Information of Core and Debug Emulation Interfaces .........................................................251
Table 51. Cores and Debug Interfaces by Series ...............................................................................251
Table 52. Feature Comparison Chart By Series and Core .................................................................252
Table 53. OCD Type of Each Series ...................................................................................................253
Table 54. Comparison of OCD 1 and OCD 2 ......................................................................................253
Table 55. Interrupt Priorities in Groups and Levels .............................................................................254
Table 56. Debug Feature by Series ....................................................................................................256
Table 57. OCD 1 and OCD 2 Pin Description .....................................................................................257
Table 58. OCD Features .....................................................................................................................258
Table 59. Pins for Flash Programming ................................................................................................266
Table 60. Instruction Table ..................................................................................................................270

A96G140/A96G148/A96A148 User’s manual 1. Description
13
1Description
A96G140/A96G148/A96A148 is an advanced CMOS 8-bit microcontroller with 64/32Kbytes of FLASH.
This is a powerful microcontroller which provides a highly flexible and cost-effective solution to many
embedded control applications.
1.1 Device overview
In this section, features of A96G140/A96G148/A96A148 and peripheral counts are introduced.
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts
Peripherals
Description
Core
CPU
8-bit CISC core (M8051, 2 clocks per cycle)
Interrupt
Up to 23 peripheral interrupts supported.
EINT0 to 7, EINT8, EINT10, EINT11, EINT12 (5)
Timer (0/1/2/3/4/5) (6)
WDT (1)
BIT (1)
WT (1)
USART Rx/Tx (2)
USI 2-ch. *Rx/Tx/I2C (6)
ADC (1)
LVI (1)
Memory
ROM (FLASH)
capacity
64/32 Kbytes FLASH with self-read and write capability
In-system programming (ISP)
Endurance: 30,000times
IRAM
256Bytes
XRAM
2304Bytes
Programmable pulse generation
Pulse generation (by T1/T2/T3/T4/T5)
8-bit PWM (by T0)
Buzzer
8-bit ×1-ch
Minimum instruction execution
time
125ns (@ 16MHz main clock)
61us (@ 32.768KHz sub clock)
Power down mode
STOP mode
IDLE mode
General Purpose I/O (GPIO)
Normal I/O: 46ports
High sink current port: 8ports P3[7:0]

1. Description A96G140/A96G148/A96A148 User’s manual
14
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued)
Peripherals
Description
Reset
Power
on reset
Reset release level: 1.2V
Low voltage
reset
16 levels detect
1.61/1.68/1.77/1.88/2.00/2.13/2.28/2.46/2.68/2.81/3.06/
3.21/3.56/3.73/3.91/4.25V
Low voltage indicator
13 levels detect
1.88/2.00/2.13/2.28/2.46/2.68/2.81/3.06/3.21/3.56/3.73/
3.91/4.25V
Watch Timer (WT)
3.91ms/0.25s/0.5s/1s/1min interval at 32.768KHz
Timer/counter
Basic interval timer (BIT) 8-bit x 1-ch.
Watchdog timer (WDT) 8-bit x 1-ch.
8-bit x 1-ch (T0), 16-bit x 5-ch (T1/T2/ T3/T4/T5)
Communication
function
USART2
8-bit USART x 1-ch or 8-bit SPI x 1-ch
Receiver timer out (RTO)
0% error baud rate
USI0/1
USART + SPI + I2C
8-bit USART x 2-ch or 8-bit SPI x 2-ch or I2C x 2-ch
12-bit A/D converter
16 input channels
Oscillator type
4MHz to 12MHz crystal or ceramic for main clock
32.768kHz Crystal for sub clock
Internal RC oscillator
HSI 32MHz ±1.5% (TA= 0~ +50°C)
HSI 32MHz ±2.0% (TA=-10~ +70°C)
HSI 32MHz ±2.5% (TA=-40~ +85°C)
HSI 32MHz ±5.0% (TA=-40~ +105°C)
LSI 128kHz ±20% (TA= -40~ +85°C)
LSI 128kHz ±30% (TA= -40~ +105°C)
Operating voltage
and frequency
1.8V to 5.5V @ 32.768KHz with crystal
2.2V to 5.5V @ 4MHz to 10MHz with crystal
2.4V to 5.5V @ 4MHz to 12MHz with crystal
1.8V to 5.5V @ 0.5MHz to 8.0MHz with internal RC
2.0V to 5.5V @ 0.5MHz to 16.0MHz with internal RC
Operating temperature
-40℃to +85℃, -40℃to +105℃

A96G140/A96G148/A96A148 User’s manual 1. Description
15
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued)
Peripherals
Description
Package
Pb-free packages
48 LQFP 7x7 mm, 48 QFN 6x6 mm
44 MQFP 10x10 mm
32 LQFP, 32 SOP
28 SOP, 28 TSSOP

1. Description A96G140/A96G148/A96A148 User’s manual
16
1.2 A96G140/A96G148/A96A148 block diagram
In this section, A96G140/A96G148/A96A148 device with peripherals are described in a block diagram.
XRAM
2304B
IRAM
256B
Flash
64/32KB
ISP
In-system programming
Power control
Power on reset
Low voltage reset
Low voltage indicator
Power down mode
Clock generator
32MHz, Internal RC OSC
128kHz Internal RC OSC
12MHz, Crystal OSC
32.768kHz, Crystal OSC
Buzzer
1 channel, 8-bit
UART
3 channels, 8-bit
SPI
3 channels, 8-bit
I2C
2 channels, 8-bit
CORE
M8051
General purpose I/O
46 ports normal I/O
Watchdog timer
1 channel, 8-bit
128kHz, internal RC OSC
Basic interval timer
1 channel, 8-bit
Timer / Counter
1 channel, 8-bit
5 channels, 16-bit
ADC
16 Input channels, 12-bit
PWM
1-ch 8-bit (T0)
5-ch 16-bit (T1/T2/T3/T4/T5)
Figure 1. A96G140/A96G148/A96A148 Block Diagram

A96G140/A96G148/A96A148 User’s manual 2. Pinouts and pin description
17
2Pinouts and pin description
In this chapter, A96G140/A96G148/A96A148 device pinouts and pin descriptions are introduced.
2.1 Pinouts
A96G140CL
A96G148CL
(48LQFP-0707)
A96G140CU
A96G148CU
(48QFN-0606)
NOTE: Programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
Figure 2. A96G140/A96G148 48LQFP/48QFN Pin Assignment

2. Pinouts and pin description A96G140/A96G148/A96A148 User’s manual
18
A96G140SQ
A96G148SQ
(44MQFP-1010)
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P44-P47 pins should be selected as a push-pull output or an input with pull-up resistor by software
control when the 44-pin package is used.
Figure 3. A96G140/A96G148 44MQFP-1010 Pin Assignment

A96G140/A96G148/A96A148 User’s manual 2. Pinouts and pin description
19
A96G140KN
A96G148KN
(32-LQFP)
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P14-P17, P23-P25, P34-P37 and P43-P47 pins should be selected as a push-pull output or an input
with pull-up resistor by software control when the 32-pin package is used.
Figure 4. A96G140/A96G148 32LQFP Pin Assignment

2. Pinouts and pin description A96G140/A96G148/A96A148 User’s manual
20
1
2
13
14
15
16
8
9
10
11
12
3
4
5
6
7
20
19
18
17
25
24
23
22
21
30
29
28
27
26
32
31
P22/SS1
P01/T3O/PWM3O/DSCL/(TXD2)
P00/EC3/DSDA/(RXD2)
P03/AN1/EINT1
P02/AN0/AVREF/EINT0/T4O/PWM4O
P51/XIN
P52/EINT8/EC0
P53/SXIN/T0O/PWM0O
P54/SXOUT/EINT10
VSS
P26 P21/AN15/SCK1
P20/AN14/TXD1/SDA1/MOSI1
VDD
P50/XOUT
P55/RESETB
P40/RXD0/SCL0/MISO0
P41/TXD0/SDA0/MOSI0
P32/LED5
P31/LED6
P30/LED7
P27
P42/SCK0
P33/LED4
P05/AN3/EINT3/(EC3)
P04/AN2/EINT2/(T3O)/(PWM3O)
P13/AN10/EC1/BUZO
P07/AN5/EINT5
P11/AN12/EINT12/T2O/PWM2O
P12/AN11/EINT11/T1O/PWM1O
P10/AN13/RXD1/SCL1/MISO1
P06/AN4/EINT4/T5O/PWM5O
A96G140KD
A96G148KD
(32-SOP)
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P14-P17, P23-P25, P34-P37 and P43-P47 pins should be selected as a push-pull output or an input
with pull-up resistor by software control when the 32-pin package is used.
Figure 5. A96G140/A96G148 32SOP Pin Assignment
1
2
13
14
8
9
10
11
12
3
4
5
6
7
16
15
21
20
19
18
17
26
25
24
23
22
28
27
P51/XIN
P52/EINT8/EC0
P53/SXIN/T0O/PWM0O
P54/SXOUT/EINT10
VSS
P50/XOUT
P55/RESETB
P40/RXD0/SCL0/MISO0
P41/TXD0/SDA0/MOSI0
P32/LED5
P31/LED6
P30/LED7
P42/SCK0
P33/LED4
P01/T3O/PWM3O/DSCL/(TXD2)
P00/EC3/DSDA/(RXD2)
P03/AN1/EINT1
P02/AN0/AVREF/EINT0/T4O/PWM4O
P21/AN15/SCK1
P20/AN14/TXD1/SDA1/MOSI1
VDD
P05/AN3/EINT3/(EC3)
P04/AN2/EINT2/(T3O)/(PWM3O)
P07/AN5/EINT5
P11/AN12/EINT12/T2O/PWM2O
P12/AN11/EINT11/T1O/PWM1O
P10/AN13/RXD1/SCL1/MISO1
P06/AN4/EINT4/T5O/PWM5O
A96G140GD
A96G148GD
(28-SOP)
A96G140GR
A96G148GR
(28-TSSOP)
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P13-P17, P22-P27, P34-P37 and P43-P47 pins should be selected as a push-pull output or an input
with pull-up resistor by software control when the 28-pin package is used.
Figure 6. A96G140/A96G148 28SOP Pin Assignment