Abov MC95FG0128A User manual

MC95FG0128A
Aug 02, 2018 Ver.2.9 1
ABOV SEMICONDUCTOR Co., Ltd.
8-BIT MICROCONTROLLERS
MC95FG0128A
User’s Manual (Ver. 2.9)

MC95FG0128A
2 Aug 02, 2018 Ver.2.9
REVISION HISTORY
VERSION
COMMENT
DATE
2.9
Modified Internal RC oscillator spec. (Chapter 7.7, 7.8)
Update Development Tools. (Chapter 1.4)
Add Device Nomenclature.
(Aug 02, 2018)
2.8
Add “direct input port Bit test and branch”instruction warning
(April 30, 2015)
2.7
Change Configure Option naming.
(Jul 04, 2014)
2.6
Correct Pin description (LPF).
(Jan 16, 2012)
2.5
Correct PSR address.
(Dec 21, 2011)
2.4
Appendix D (Instructions on how to use the input port) added.
(Nov 24, 2011)
2.3
Add DC Characteristics
(Aug 17, 2011)
2.2
Add PWM description
(Jun 07, 2011)
2.1
Add Package type
(Apr 26, 2011)
2.0
Correct A/D Converter Characteristics
(Mar 03, 2011)
1.9
Correct Interrupt register, Port selection register name
(Feb 10, 2011)
1.8
AC description modification
(Jan 18, 2011)
1.7
Timer register description modification
(Jan 07, 2011)
1.6
TxDR register increment range modification
(Nov 23, 2010)
1.5
Update 11.1.5 register description for clock generator
(Oct 30, 2010)
1.4
Update gang 4 gang 8
(Apr 09, 2010)
1.3
fix Figure 10.5 Multi interrupt(add ‘SETB EA’) and update example
Correct Figure 11-17 (timer 2, 3, 4 block diagram)
(Feb 04, 2010)
1.2
update Figure 11-45 ADC Block Diagram.
(Jan 18, 2010)
1.1
update 11.7.8.2 transmit flag and interrupt, 11.7.12 USTAT register
(Jan 15, 2010)
1.0
update special Pin description add LPF circuit, change open drain port
description
(Jan 11, 2010)

MC95FG0128A
Aug 02, 2018 Ver.2.9 3
Published by AE Team
2018 ABOV Semiconductor Co..Ltd. All rights reserved.
Additional information of this manual may be served by ABOV Semiconductor offices in Korea or Distributors.
ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable.
However, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party
generated by the use of this manual.

MC95FG0128A
4 Aug 02, 2018 Ver.2.9
Table of Contents
REVISION HISTORY..........................................................................................................................................2
Table of Contents....................................................................................................................................................4
List of Figures.........................................................................................................................................................7
MC95FG0128A....................................................................................................................................................10
1. Overview ..........................................................................................................................................................10
1.1 Description.................................................................................................................................................10
1.2 Features......................................................................................................................................................10
1.3 Ordering Information.................................................................................................................................12
1.4 Development Tools....................................................................................................................................13
2. Block Diagram..................................................................................................................................................18
3. Pin Assignmnet.................................................................................................................................................21
4. Package Diagram..............................................................................................................................................26
5. Pin Description.................................................................................................................................................31
6. Port Structures ..................................................................................................................................................35
6.1 General Purpose I/O Port...........................................................................................................................35
6.2 External Interrupt I/O Port.........................................................................................................................36
7. Electrical Characteristics ..................................................................................................................................37
7.1 Absolute Maximum Ratings ......................................................................................................................37
7.2 Recommended Operating Conditions ........................................................................................................37
7.3 A/D Converter Characteristics...................................................................................................................38
7.4 Voltage Dropout Converter Characteristics...............................................................................................38
7.5 Power-On Reset Characteristics.................................................................................................................39
7.6 Brown Out Detector Characteristics ..........................................................................................................39
7.7 Internal RC Oscillator Characteristics .......................................................................................................39
7.8 Ring-Oscillator Characteristics..................................................................................................................40
7.9 PLL Characteristics....................................................................................................................................40
7.10 DC Characteristics...................................................................................................................................41
7.11 AC Characteristics...................................................................................................................................42
7.12 SPI Characteristics...................................................................................................................................43
7.13 Typical Characteristics.............................................................................................................................44
8. Memory ............................................................................................................................................................45
8.1 Program Memory.......................................................................................................................................45
8.2 Data Memory.............................................................................................................................................47
8.3 EEPROM Data Memory and XSRAM ......................................................................................................49
8.4 SFR Map....................................................................................................................................................50
9. I/O Ports............................................................................................................................................................54
9.1 I/O Ports.....................................................................................................................................................54
9.2 Port Register ..............................................................................................................................................54
9.3 Px Port .......................................................................................................................................................57
10. Interrupt Controller.........................................................................................................................................59
10.1 Overview..................................................................................................................................................59
10.2 External Interrupt.....................................................................................................................................60
10.3 Block Diagram.........................................................................................................................................61
10.4 Interrupt Vector Table..............................................................................................................................62

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Aug 02, 2018 Ver.2.9 5
10.5 Interrupt Sequence ...................................................................................................................................62
10.6 Effective Timing after Controlling Interrupt bit ......................................................................................64
10.7 Multi Interrupt..........................................................................................................................................65
10.8 Interrupt Enable Accept Timing ..............................................................................................................66
10.9 Interrupt Service Routine Address...........................................................................................................66
10.10 Saving/Restore General-Purpose Registers............................................................................................66
10.11 Interrupt Timing.....................................................................................................................................67
10.12 Interrupt Register Overview...................................................................................................................67
10.13 Interrupt Register Description................................................................................................................69
11. Peripheral Hardware.......................................................................................................................................74
11.1 Clock Generator.......................................................................................................................................74
11.2 BIT...........................................................................................................................................................78
11.3 WDT ........................................................................................................................................................80
11.4 WT...........................................................................................................................................................83
11.5 Timer/PWM.............................................................................................................................................86
11.6 Buzzer Driver.........................................................................................................................................108
11.7 USART ..................................................................................................................................................110
11.8 SPI..........................................................................................................................................................128
11.9 I2C..........................................................................................................................................................133
11.10 12-Bit A/D Converter ..........................................................................................................................150
11.11 CALCULATOR_AI ............................................................................................................................155
12. Power Down Operation ................................................................................................................................159
12.1 Overview................................................................................................................................................159
12.2 Peripheral Operation in IDLE/STOP Mode...........................................................................................159
12.3 IDLE mode ............................................................................................................................................160
12.4 STOP mode............................................................................................................................................160
12.5 Release Operation of STOP1, 2 Mode...................................................................................................162
13. RESET..........................................................................................................................................................164
13.1 Overview................................................................................................................................................164
13.2 Reset source...........................................................................................................................................164
13.3 Block Diagram.......................................................................................................................................164
13.4 RESET Noise Canceller.........................................................................................................................165
13.5 Power ON RESET .................................................................................................................................165
13.6 External RESETB Input.........................................................................................................................168
13.7 Brown Out Detector Processor ..............................................................................................................169
14. On-chip Debug System.................................................................................................................................172
14.1 Overview................................................................................................................................................172
14.2 Two-pin external interface.....................................................................................................................173
15. Memory Programming..................................................................................................................................177
15.1 Overview................................................................................................................................................177
15.2 Flash and EEPROM Control and status register....................................................................................177
15.3 Memory map..........................................................................................................................................181
15.4 Serial In-System Program Mode............................................................................................................184
15.5 Parallel Mode.........................................................................................................................................191
15.6 Mode entrance method of ISP and byte-parallel mode..........................................................................194
15.7 Security..................................................................................................................................................195

MC95FG0128A
6 Aug 02, 2018 Ver.2.9
16. Configure option...........................................................................................................................................196
16.1 Configure option Control Register.........................................................................................................196
17. APPENDIX ..................................................................................................................................................197

MC95FG0128A
Aug 02, 2018 Ver.2.9 7
List of Figures
Figure 1.1 Device Nomenclature..........................................................................................................12
Figure 1.2 Debugger and Pin description..............................................................................................13
Figure 1.3 OCD Interface Circuit .........................................................................................................14
Figure 1.4 E-PGM+ component and connector ....................................................................................15
Figure 1.5 PGMplusLC Writer .............................................................................................................16
Figure 1.6 E-PGM+ Gang4/6 Programmer...........................................................................................17
Figure 2.1 MC95FG0128A block diagram...........................................................................................18
Figure 2.2 MC95FG8128A block diagram...........................................................................................19
Figure 2.3 MC95FG6128A block diagram...........................................................................................20
Figure 3.1 MC95FG0128A 100 Pin LQFP assignment........................................................................21
Figure 3.2 MC95FG0128A 80 Pin LQFP assignment..........................................................................22
Figure 4.1 100 pin LQFP package........................................................................................................26
Figure 4.2 80 pin LQFP package..........................................................................................................27
Figure 4.3 80 pin MQFP package.........................................................................................................28
Figure 4.4 64 pin LQFP package..........................................................................................................29
Figure 4.5 64 pin LQFP14 package......................................................................................................30
Figure 6.1 General Purpose I/O Port.....................................................................................................35
Figure 6.2 General Purpose I/O Port.....................................................................................................36
Figure 7.1 AC Timing...........................................................................................................................42
Figure 7.2 SPI Timing ..........................................................................................................................43
Figure 8.1 Program memory.................................................................................................................46
Figure 8.2 Data memory map ...............................................................................................................47
Figure 8.3 Lower 128 bytes RAM........................................................................................................48
Figure 8.4 XDATA memory area .........................................................................................................49
Figure 10.1 External Interrupt Description...........................................................................................60
Figure 10.2 Block Diagram of Interrupt ...............................................................................................61
Figure 10.3 Interrupt Sequence Flow....................................................................................................63
Figure 10.4 Interrupt Enable Register effective Timing.......................................................................64
Figure 10.5 Execution of Multi Interrupt..............................................................................................65
Figure 10.6 Interrupt Response Timing Diagram .................................................................................66
Figure 10.7 Correspondence between vector Table address and the entry address of ISR...................66
Figure 10.8 Saving/Restore Process Diagram & Sample Source..........................................................66
Figure 10.9 Timing chart of Interrupt Acceptance and Interrupt Return Instruction............................67
Figure 11.1 Clock Generator Block Diagram.......................................................................................74
Figure 11.2 BIT Block Diagram...........................................................................................................78
Figure 11.3 WDT Block Diagram ........................................................................................................80
Figure 11.4 WDT Interrupt Timing Waveform ....................................................................................82
Figure 11.5 Watch Timer Block Diagram ............................................................................................83
Figure 11.6 8 Bit Timer/Event Counter2, 3 Block Diagram.................................................................87
Figure 11.7 Timer/Event Counter0, 1 Example....................................................................................88
Figure 11.8 Operation Example of Timer/Event Counter0, 1...............................................................88

MC95FG0128A
8 Aug 02, 2018 Ver.2.9
Figure 11.9 16 Bit Timer/Event Counter0, 1 Block Diagram...............................................................89
Figure 11.10 8-bit Capture Mode for Timer0, 1 ...................................................................................90
Figure 11.11 Input Capture Mode Operation of Timer 0, 1..................................................................91
Figure 11.12 Express Timer Overflow in Capture Mode .....................................................................91
Figure 11.13 16-bit Capture Mode of Timer 0, 1..................................................................................92
Figure 11.14 PWM Mode.....................................................................................................................93
Figure 11.15 Example of PWM at 4MHz.............................................................................................94
Figure 11.16 Example of Changing the Period in Absolute Duty Cycle at 4Mhz ................................94
Figure 11.17 Timerx 16-bit Mode Block Diagram...............................................................................99
Figure 11.18 16-bit Capture Mode of Timer x....................................................................................100
Figure 11.19 PWM Mode...................................................................................................................101
Figure 11.20 Example of PWM at 8MHz...........................................................................................102
Figure 11.21 Buzzer Driver Block Diagram.......................................................................................108
Figure 11.22 USART Block Diagram ................................................................................................111
Figure 11.23 Clock Generation Block Diagram .................................................................................112
Figure 11.24 Synchronous Mode XCKn Timing................................................................................113
Figure 11.25 frame format..................................................................................................................114
Figure 11.26 Start Bit Sampling .........................................................................................................118
Figure 11.27 Sampling of Data and Parity Bit....................................................................................118
Figure 11.28 Stop Bit Sampling and Next Start Bit Sampling............................................................119
Figure 11.29 SPI Clock Formats when UCPHA=0 ............................................................................120
Figure 11.30 SPI Clock Formats when UCPHA=1 ............................................................................121
Figure 11.31 SPI Block Diagram........................................................................................................128
Figure 11.32 SPI Transmit/Receive Timing Diagram at CPHA = 0...................................................130
Figure 11.33 SPI Transmit/Receive Timing Diagram at CPHA = 1...................................................130
Figure 11.34 I2C Block Diagram........................................................................................................133
Figure 11.35 Bit Transfer on the I2C-Bus...........................................................................................134
Figure 11.36 START and STOP Condition........................................................................................134
Figure 11.37 Data Transfer on the I2C-Bus ........................................................................................135
Figure 11.38 Acknowledge on the I2C-Bus ........................................................................................135
Figure 11.39 Clock Synchronization during Arbitration Procedure ...................................................136
Figure 11.40 Arbitration Procedure of Two Masters..........................................................................136
Figure 11.41 Formats and States in the Master Transmitter Mode.....................................................139
Figure 11.42 Formats and States in the Master Receiver Mode .........................................................141
Figure 11.43 Formats and States in the Slave Transmitter Mode .......................................................143
Figure 11.44 Formats and States in the Slave Receiver Mode............................................................145
Figure 11.45 ADC Block Diagram.....................................................................................................150
Figure 11.46 A/D Analog Input Pin Connecting Capacitor................................................................151
Figure 11.47 A/D Power(AVDD) Pin Connecting Capacitor.............................................................151
Figure 11.48 ADC Operation for Align bit.........................................................................................151
Figure 11.49 Converter Operation Flow.............................................................................................152
Figure 11.50 Calculator Block Diagram.............................................................................................155
Figure 12.1 IDLE Mode Release Timing by External Interrupt .........................................................160

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Aug 02, 2018 Ver.2.9 9
Figure 12.2 IDLE Mode Release Timing by /RESET ........................................................................160
Figure 12.3 STOP Mode Release Timing by External Interrupt.........................................................161
Figure 12.4 STOP Mode Release Timing by /RESET........................................................................161
Figure 12.5 STOP1, 2 Mode Release Flow ........................................................................................162
Figure 13.1 RESET Block Diagram ...................................................................................................164
Figure 13.2 Reset noise canceller time diagram .................................................................................165
Figure 13.3 Fast VDD rising time.......................................................................................................165
Figure 13.4 Internal RESET Release Timing On Power-Up ..............................................................166
Figure 13.5 Configuration timing when Power-on.............................................................................166
Figure 13.6 Boot Process Wave Form................................................................................................167
Figure 13.7 Timing Diagram after RESET.........................................................................................168
Figure 13.8 Oscillator generating waveform example........................................................................168
Figure 13.9 Block Diagram of BOD...................................................................................................169
Figure 13.10 Internal Reset at the power fail situation .......................................................................169
Figure 13.11 Configuration timing when BOD RESET .....................................................................170
Figure 14.1 Block Diagram of On-chip Debug System......................................................................173
Figure 14.2 10-bit transmission packet...............................................................................................174
Figure 14.3 Data transfer on the twin bus...........................................................................................174
Figure 14.4 Bit transfer on the serial bus............................................................................................175
Figure 14.5 Start and stop condition...................................................................................................175
Figure 14.6 Acknowledge on the serial bus........................................................................................175
Figure 14.7 Clock synchronization during wait procedure.................................................................176
Figure 14.8 Connection of transmission .............................................................................................176
Figure 15.1 Flash Memory Map .........................................................................................................181
Figure 15.2 Address configuration of Flash memory .........................................................................182
Figure 15.3 Data EEPROM memory map ..........................................................................................182
Figure 15.4 Address configuration of data EEPROM ........................................................................183
Figure 15.5 The sequence of page program and erase of Flash memory............................................184
Figure 15.6 The sequence of bulk erase of Flash memory .................................................................185
Figure 15.7 Pin diagram for parallel programming ............................................................................191
Figure 15.8 Parallel Byte Read Timing of Program Memory.............................................................192
Figure 15.9 Parallel Byte Write Timing of Program Memory............................................................193
Figure 15.10 ISP mode .......................................................................................................................194
Figure 15.11 Byte-parallel mode ........................................................................................................194

MC95FG0128A
10 Aug 02, 2018 Ver.2.9
MC95FG0128A
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 12-BITA/D CONVERTER
1. Overview
1.1 Description
The MC95FG0128A is an advanced CMOS 8-bit microcontroller with 128K bytes of FLASH. This is
powerful microcontroller which provides a highly flexible and cost effective solution to many
embedded control applications. This provides the following features : 128K bytes of FLASH, 256
bytes of SRAM, 4K bytes of Data EEPROM, 8K bytes of XRAM general purpose I/O, 8/16-bit
timer/counter, watchdog timer, watch timer, SPI, USART, I2C, Calculator, on-chip POR and BOD, 12-
bit A/D converter, buzzer driving port, 16-bit PWM output, on-chip oscillator and clock circuitry. The
MC95FG0128A also supports power saving modes to reduce power consumption.
Device Name
FLASH
EEPROM
XRAM
SRAM
ADC
Package
MC95FG0128A
128K
bytes
4K bytes
8K bytes
256 bytes
15 channel
100LQFP
80LQFP
80MQFP
64LQFP
64LQPF14
1.2 Features
•CPU
-8 Bit CISC Core (8051 Compatible,2 clock
per cycle)
•128K Bytes On-chip FLASH
-Endurance : 10,000 times
-Retention : 10 years
•4K Bytes Data EEPROM
-Endurance : 100,000 times
-Retention : 10 years
•256 Bytes SRAM
•8K Bytes XRAM
•General Purpose I/O
-86 Ports (P0[7:0], P1[7:0], P2[7:0], P3[7:0],
P4[7:0], P5[7:0], P6[7:0], P7[7:0], P8[7:0],
P9[7:0], PA[5:0]) : 100 Pin
-66 Ports (P0[7:0], P1[7:0], P2[7:0], P3[7:0],
P4[7:0], P5[7:0], P6[5:0], P7[7:0],
P8[1:0]) : 80 Pin
-52 Ports (P0[7:0], P1[7:0], P2[7:0], P3[7:0],
P4[7:0], P5[7:0], P6[3:0]) : 64 Pin
-Support TTL compatible PAD (P3[7:0], SPI0,
USART1)
•Basic Interval Timer
•Timer / Counter 6Ch
-8Bit×2ch(16Bit×1ch) + 16Bit×4ch
•1Ch 10-bit PWM (using Timer1)
•4Ch 16-bit PWM (using Timer2,3,4,5)

MC95FG0128A
Aug 02, 2018 Ver.2.9 11
•Watch Dog Timer
•Watch Timer
•2 SPI
•4 USART (4th usart can use only 100pin)
•I2C
•Buzzer Driving Port
•Calculator
-Multiplier mode : 16bits x 16bits
-Divider mode : 32bits / 16bits
•12 Bit A/D Converter
-15 Input channels
•Interrupt Sources
-External (8)
-Pin Change Interrupt (P0, P7) (2)
-USART (8)
-SPI (2)
-Timer (6)
-I2C (1)
-ADC (1)
-WDT (1)
-WT (1)
-BIT (1)
-EEPROM (1)
•On-Chip RC-Oscillator
-8MHz OSC ( ±1.5%@25℃)
•On-Chip WDT-Oscillator
-8MHz OSC ( ±50%@-40~+85℃)
•On-Chip PLL
-1.38MHz ~ 20.18MHz (with 32.768KHz)
•Power On Reset
-1.4V
•Programmable Brown-Out Detector
-1.6V / 2.5V / 3.6V / 4.2V
•Minimum Instruction Execution Time
-200ns (@10MHz, NOP Instruction)
•Power down mode
-IDLE, STOP1, STOP2 mode
•Sub-Active mode
-System used external 32.768KHz crystal
•Operating Frequency
-1MHz ~ 10MHz (crystal oscillator)
- 1, 2, 4, 8MHz (internal RC oscillator)
-1.38MHz ~ 20.18MHz (PLL)
•Operating Voltage
-2.7V ~ 5.5V (@ 1~20.18MHz)
•Operating Temperature : -40 ~ +85℃
•Package Type
-100 LQFP
-80 LQFP
-80 MQFP
-64 LQFP
-64 LQFP14
-Pb free package

MC95FG0128A
12 Aug 02, 2018 Ver.2.9
1.3 Ordering Information
Table 1-1 Ordering Information of MC95FG0128A
Device name
ROM size
SRAM size
XRAM size
EEPROM size
Package
MC95FG0128AL
128 Kbytes FLASH
256 bytes
8 Kbytes
4 Kbytes
100 LQFP
MC95FG8128AL
MC95FG8128AQ
80 LQFP
80 MQFP
MC95FG6128AL
64 LQFP
MC95FG6128AL14
64 LQFP14
Figure 1.1 Device Nomenclature

MC95FG0128A
Aug 02, 2018 Ver.2.9 13
1.4 Development Tools
1.4.1 Compiler
ABOV Semiconductor dose not provide compiler. It is recommended that you consult a compiler
provider.
The MC95FG0128A core is Mentor 8051. Device ROM size of standard 8051 is smaller than 64KB.
Developer can use all kinds of third party’s standard 8051 compiler. But MC95FG0128A has 128KB
code ROM area and uses memory banking scheme for this extended ROM. So user should use the
proper compiler which can support the memory space over 64KB ROM address area.
1.4.2 OCD emulator and debugger
The OCD (On Chip Debug) emulator supports ABOV Semiconductor’s 8051 series MCU
emulation.The OCD interface uses two-wire connection between PC and MCU which is attached to
user’s system. The OCD can read or change the value of MCU internal memory and I/O peripherals.
And the OCD also controls MCU internal debugging logic, it means OCD controls emulation, step run,
monitoring, etc.
The OCD Debugger program works on Microsoft-Windows NT, 2000, XP, Vista (32-bit), 7, 8, 10
operating system.
If you want to see more details, please refer OCD debugger manual. You can download debugger
S/W and manual from our web-site.
On-Board programming :
The program memory of MC95FG308 is FLASH Memory Type. This flash is accessed by serial data
format. There are four pins (DSCL, DSDA, VDD, and VSS) for programming/reading the flash. The
MC95FG308 needs only four signal lines including VDD and VSS pins for programming FLASH with
serial protocol. Therefore the on-board programming is possible if the programming signal lines are
considered when the PCB of application board is designed.
Connection:
- SCLK (MC95FG0128A DSCL pin)
- SDAT (MC95FG0128A DSDA pin)
OCD connector diagram: Connect OCD and user system
Figure 1.2 Debugger and Pin description

MC95FG0128A
14 Aug 02, 2018 Ver.2.9
E-PGM+, PGM Plus LC2, E-PGM+ Gang4/6
DSCL(I)
DSDA(I/O)
VDD
VSS
R1 (2k ~ 5k )
R2 (2k ~ 5k )
To application circuit
To application circuit
Figure 1.3 OCD Interface Circuit
NOTE)
1. In on-board programming mode, very high-speed signal will be provided to pin DSCL and
DSDA. And it will cause some damages to the application circuits connected to DSCL or
DSDA port if the application circuit is designed as high speed response such as relay control
circuit. If possible, the I/O configuration of DSDA, DSCL pins had better be set to input mode.
2. The value of R1 and R2 is recommended value. It varies with circuit of system.

MC95FG0128A
Aug 02, 2018 Ver.2.9 15
1.4.3 Programmer
E-PGM +
•Support ABOV / ADAM devices
•2~5 times faster than S-PGM+
•Main controller : 32-bit MCU @ 72MHz
•Buffer memory : 1MB
Figure 1.4 E-PGM+ component and connector

MC95FG0128A
16 Aug 02, 2018 Ver.2.9
PGMPlusLC 2
Description
PGMPlusLC2 is for ISP (In System Programming). It is used to write into the MCU
Which is already mounted on target board using 10pin cable.
Features
•PGMplusLC2 is low cost writing Tool.
•USB interface is supported.
•Not need USB driver installation.
•Connect the external power adapter (5V@2A).
•Supported high voltage Max 18V.
•PGMplusLC2 is based on PC environment.
•PGMplusLC2 is faster than PGM plus LC.
•Transmission speed is 64Kbyte/s
Figure 1.5 PGMplusLC Writer

MC95FG0128A
Aug 02, 2018 Ver.2.9 17
E-PGM+ Gang4/6
•Product name : E-PGM+ GANG 4
•Dimension(x , y, h) : 33.5 x 22.5 x35mm
•Weight : 2.0kg
•Input Voltage : DC Adaptor 15V/2A
•Operating Temp : -10 ~ 40℃
•Storage Temp: -30 ~ 80℃
•Water Proof : No
•Product name : E-PGM+ GANG 6
•Dimension(x , y, h) : 148.2 x 22.5 x35mm
•Weight : 2.8kg
•Input Voltage : DC Adaptor 15V/2A
•Operating Temp : -10 ~ 40℃
•Storage Temp: -30 ~ 80℃
•Water Proof : No
Figure 1.6 E-PGM+ Gang4/6 Programmer

MC95FG0128A
18 Aug 02, 2018 Ver.2.9
2. Block Diagram
Figure 2.1 MC95FG0128A block diagram
On –Chip
Debug
nTEST
M8051
CORE
EEPROM
(4KB)
SRAM
(256B)
FLASH
(128K byte)
Power on
Reset
Brown Out
Detector
INT-RC OSC
(8MHz)
Voltage
Down
Convertor
P0
PORT
BIT
WDT
WT
CLOCK/
SYSTEM
CON
TIMER
&
PWM
12-BIT
ADC
DSCL / DSDA
P31/AN9
P30/AN8
P27/AN7
P26/AN6
P25/AN5
P24/AN4
P23/AN3
P22/AN2
P21/AN1
P20/AVREF/AN0
P51/EC0
P52/T0
P53/T1(PWM1)
P54/T2(PWM2)
P55/T3(PWM3)
P56/T4(PWM4)
P57/T5(PWM5)
SPI0
P37/MISO0
P36/MOSI0
P35/SCK0
P34/SSS0
I2C
P07/SDA
P06/SCL
P07~P00
SUBXIN/P04
SUBXOUT/P05
XIN/P62
XOUT/P63
nRESET
VDD
VSS
USART0
P03/RxD0
P02/TxD0
P01/ACK0
P00/USS0
P50/BUZ
BUZZER
P32/AN10
P33/AN11
P34/AN12
P36/AN14
XRAM
(8KB)
VDD18
P1
PORT
P17~P10
P2
PORT
P3
PORT
P4
PORT
P5
PORT
P27~P20
P37~P30
P47~P40
P57~P50
P6
PORT
P67~P60
P7
PORT
P77~P70
P8
PORT
P9
PORT
PA
PORT
P87~P80
P97~P90
PA5~PA0
USART1
P33/RxD1
P32/TxD1
P31/ACK1
P30/USS1
USART2
P43/RxD2
P42/TxD2
P41/ACK2
P40/USS2
SPI1
P47/MISO1
P46/MOSI1
P45/SCK1
P44/SSS1
USART3
(100pin only)
P93/RxD3
P92/TxD3
P91/ACK3
P90/USS3
Calculator
P60/EC2
P61/EC3
P65/EC5
P64/EC4
Interrupt
Controller
P00 ~ P07/ PCI0
P70 ~ P77/ PCI7
P10/INT0
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17/INT7
PLL
(20.18MHz)
P35/AN13

MC95FG0128A
Aug 02, 2018 Ver.2.9 19
Figure 2.2 MC95FG8128A block diagram
On –Chip
Debug
nTEST
M8051
CORE
EEPROM
(4KB)
SRAM
(256B)
FLASH
(128K byte)
Power on
Reset
Brown Out
Detector
INT-RC OSC
(8MHz)
Voltage
Down
Convertor
P0
PORT
BIT
WDT
WT
CLOCK/
SYSTEM
CON
TIMER
&
PWM
12-BIT
ADC
DSCL / DSDA
P31/AN9
P30/AN8
P27/AN7
P26/AN6
P25/AN5
P24/AN4
P23/AN3
P22/AN2
P21/AN1
P20/AVREF/AN0
P51/EC0
P52/T0
P53/T1(PWM1)
P54/T2(PWM2)
P55/T3(PWM3)
P56/T4(PWM4)
P57/T5(PWM5)
SPI0
P37/MISO0
P36/MOSI0
P35/SCK0
P34/SSS0
I2C
P07/SDA
P06/SCL
P07~P00
SUBXIN/P04
SUBXOUT/P05
XIN/P62
XOUT/P63
nRESET
VDD
VSS
USART0
P03/RxD0
P02/TxD0
P01/ACK0
P00/USS0
P50/BUZ
BUZZER
P32/AN10
P33/AN11
P34/AN12
P36/AN14
XRAM
(8KB)
VDD18
P1
PORT
P17~P10
P2
PORT
P3
PORT
P4
PORT
P5
PORT
P27~P20
P37~P30
P47~P40
P57~P50
P6
PORT
P67~P60
P7
PORT
P77~P70
USART1
P33/RxD1
P32/TxD1
P31/ACK1
P30/USS1
USART2
P43/RxD2
P42/TxD2
P41/ACK2
P40/USS2
SPI1
P47/MISO1
P46/MOSI1
P45/SCK1
P44/SSS1
Calculator
P60/EC2
P61/EC3
Interrupt
Controller
P00 ~ P07/ PCI0
P10/INT0
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17/INT7
PLL
(20.18MHz)
P35/AN13
P64/EC4
P65/EC5

MC95FG0128A
20 Aug 02, 2018 Ver.2.9
Figure 2.3 MC95FG6128A block diagram
On –Chip
Debug
nTEST
M8051
CORE
EEPROM
(4KB)
SRAM
(256B)
FLASH
(128K byte)
Power on
Reset
Brown Out
Detector
INT-RC OSC
(8MHz)
Voltage
Down
Convertor
P0
PORT
BIT
WDT
WT
CLOCK/
SYSTEM
CON
TIMER
&
PWM
12-BIT
ADC
DSCL / DSDA
P31/AN9
P30/AN8
P27/AN7
P26/AN6
P25/AN5
P24/AN4
P23/AN3
P22/AN2
P21/AN1
P20/AVREF/AN0
P51/EC0
P52/T0
P53/T1(PWM1)
P54/T2(PWM2)
P55/T3(PWM3)
P56/T4(PWM4)
P57/T5(PWM5)
SPI0
P37/MISO0
P36/MOSI0
P35/SCK0
P34/SSS0
I2C
P07/SDA
P06/SCL
P07~P00
SUBXIN/P04
SUBXOUT/P05
XIN/P62
XOUT/P63
nRESET
VDD
VSS
USART0
P03/RxD0
P02/TxD0
P01/ACK0
P00/USS0
P50/BUZ
BUZZER
P32/AN10
P33/AN11
P34/AN12
P36/AN14
XRAM
(8KB)
VDD18
P1
PORT
P17~P10
P2
PORT
P3
PORT
P4
PORT
P5
PORT
P27~P20
P37~P30
P47~P40
P57~P50
P6
PORT
P63~P60
USART1
P33/RxD1
P32/TxD1
P31/ACK1
P30/USS1
USART2
P43/RxD2
P42/TxD2
P41/ACK2
P40/USS2
SPI1
P47/MISO1
P46/MOSI1
P45/SCK1
P44/SSS1
Calculator
P60/EC2
P61/EC3
Interrupt
Controller
P00 ~ P07/ PCI0
P10/INT0
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17/INT7
PLL
(20.18MHz)
P35/AN13