Abov MC96FR364B User manual

MC96FR364B
November, 2018 Rev.1.4 1
ABOV SEMICONDUCTOR Co., Ltd.
8-BIT MICROCONTROLLERS
MC96FR364B
User’s Manual (Rev.1.4)

MC96FR364B
2 November, 2018 Rev.1.4
REVISION HISTORY
REVISION 0.0 (February 19, 2013)
- Preliminary Version
REVISION 1.0 (July 23, 2013)
- Initial Version
REVISION 1.1 (December 11, 2014)
9.2.11 PORT 3
The address of P3 Data register is changed from 9FHto C0H
REVISION 1.2 (January 8, 2016)
11.7.6 Examples of REMOUT control
The function of “rdpe_disable_mode_init” is a prerequisite for RDPE disable mode.
REVISION 1.3 (January 11, 2018)
1.3 Ordering information
Ordering information are changed
Device nomenclature is added
1.4 Devolopment tools
Pictures are changed
Delete VPP pin name
REVISION 1.4 (November 20, 2018)
Remove QFN, SOP PKG

MC96FR364B
November, 2018 Rev.1.4 3
Revision 1.4
Published by AE
2018 ABOV Semiconductor Co., Ltd. All rights reserved.
Additional information of this manual may be served by ABOV Semiconductor offices in Korea or
Distributors.
ABOV Semiconductor reserves the right to make changes to any information here in at any time without
notice.
The information, diagrams and other data in this manual are correct and reliable; however, ABOV
Semiconductor is in no way responsible for any violations of patents or other rights of the third party
generated by the use of this manual.

MC96FR364B
4 November, 2018 Rev.1.4
Table of Contents
REVISION HISTORY .......................................................................................................................................... 2
Table of Contents................................................................................................................................................. 4
List of Figures ....................................................................................................................................................... 6
MC96FR364B....................................................................................................................................................... 9
1. OVERVIEW....................................................................................................................................................... 9
1.1 Description................................................................................................................................................... 9
1.2 Features........................................................................................................................................................ 9
1.3 Ordering Information ................................................................................................................................. 10
1.4 Development Tools.................................................................................................................................... 12
2. BLOCK DIAGRAM......................................................................................................................................... 15
3. PIN CONFIGURATIONS................................................................................................................................ 16
4. PACKAGE DIMENSION ................................................................................................................................ 17
5. PIN DESCRIPTION......................................................................................................................................... 19
6. PORT STRUCTURES ..................................................................................................................................... 21
6.1 General Purpose I/O Port ........................................................................................................................... 21
6.2 External Interrupt I/O Port ......................................................................................................................... 22
6.3 REMOUT Port........................................................................................................................................... 23
7. ELECTRICAL CHARACTERISTICS............................................................................................................. 24
7.1 Absolute Maximum Ratings ...................................................................................................................... 24
7.2 RECOMMENDED OPERATING CONDITION...................................................................................... 24
7.3 VOLTAGE DROPOUT CONVERTER(VDC) CHARACTERISTICS.................................................... 25
7.4 BROWN OUT DETECTOR(BOD) CHARACTERISTICS ..................................................................... 25
7.5 POWER-ON RESET CHARACTERISTICS ............................................................................................ 26
7.6 DC CHARACTERISTICS......................................................................................................................... 26
7.7 AC CHARACTERISTICS......................................................................................................................... 27
7.8 USART CHARACTERISTICS ................................................................................................................. 28
7.9 REMOUT PORT CHARACTERISTICS .................................................................................................. 31
7.10 TYPICAL CHARACTERISTICS ........................................................................................................... 32
8. MEMORY ........................................................................................................................................................ 33
8.1 Program Memory ....................................................................................................................................... 33
8.2 IRAM......................................................................................................................................................... 34
8.3 XRAM ....................................................................................................................................................... 38
8.4 Registers .................................................................................................................................................... 39
9. I/O PORTS ....................................................................................................................................................... 43
9.1 Introduction................................................................................................................................................ 43
9.2 Register Description................................................................................................................................... 43
10. Interrupt Controller......................................................................................................................................... 51
10.1 Overview.................................................................................................................................................. 51
10.2 External Interrupt ..................................................................................................................................... 52
10.3 Block Diagram......................................................................................................................................... 53
10.4 Interrupt Vectors ...................................................................................................................................... 54
10.5 Interrupt Sequence ................................................................................................................................... 54
10.6 Effective time of Interrupt Request.......................................................................................................... 55
10.7 Multiple Interrupts ................................................................................................................................... 56
10.8 Interrupt Service Procedure ..................................................................................................................... 57

MC96FR364B
November, 2018 Rev.1.4 5
10.9 Generation of Branch Address to Interrupt Service Routine(ISR)........................................................... 57
10.10 Saving and Restoring General Purpose Registers .................................................................................. 58
10.11 Interrupt Timing..................................................................................................................................... 58
10.12 Interrupt Registers.................................................................................................................................. 59
11. Peripheral Units .............................................................................................................................................. 65
11.1 Clock Generator....................................................................................................................................... 65
11.2 Basic Interval Timer (BIT) ...................................................................................................................... 67
11.3 Watch Dog Timer (WDT)........................................................................................................................ 70
11.4 TIMER/PWM .......................................................................................................................................... 73
11.5 Watch Timer with event capture function (WT) .................................................................................... 101
11.6 IR Capture Control (IRCC).................................................................................................................... 107
11.7 Carrier Generator ................................................................................................................................... 111
11.8 Key Scan ................................................................................................................................................ 119
11.9 USART0/1 ............................................................................................................................................. 122
11.10 I2C ........................................................................................................................................................ 140
12. POWER MANAGEMENT .......................................................................................................................... 157
12.1 Overview................................................................................................................................................ 157
12.2 PERIPHERAL OPERATION IN SLEEP/STOP/BOD MODE ............................................................. 157
12.3 SLEEP mode.......................................................................................................................................... 157
12.4 STOP mode............................................................................................................................................ 158
12.5 BOD mode ............................................................................................................................................. 160
12.6 Register Map.......................................................................................................................................... 161
12.7 Register Description............................................................................................................................... 161
13. RESET.......................................................................................................................................................... 162
13.1 Overview................................................................................................................................................ 162
13.2 Reset source ........................................................................................................................................... 162
13.3 Block Diagram....................................................................................................................................... 162
13.4 Noise Canceller for External Reset Pin.................................................................................................. 163
13.5 Power-On-RESET ................................................................................................................................. 163
13.6 External RESETB Input......................................................................................................................... 166
13.7 Brown Out Detector............................................................................................................................... 167
13.8 Register Map.......................................................................................................................................... 168
13.9 Register Description............................................................................................................................... 168
14. On-chip Debug System................................................................................................................................. 171
14.1 Overview................................................................................................................................................ 171
14.2 Two-pin external interface ..................................................................................................................... 172
15. FLASH Memory Controller ......................................................................................................................... 176
15.1 Overview................................................................................................................................................ 176
15.2 Boot Area............................................................................................................................................... 176
15.3 Register Map.......................................................................................................................................... 177
15.4 Register Description............................................................................................................................... 178
15.5 Memory map.......................................................................................................................................... 184
15.6 Serial In-System Program Mode............................................................................................................ 185
15.7 Security .................................................................................................................................................. 189
15.8 FLASH Memory operating mode .......................................................................................................... 190
16. Etc................................................................................................................................................................. 191
16.1 FUSE Control Register .......................................................................................................................... 191
17. APPENDIX .................................................................................................................................................. 192

MC96FR364B
6 November, 2018 Rev.1.4
List of Figures
Figure 1-1 Device Nomenclature.......................................................................................................... 11
Figure 1-2 OCD Software and Connector............................................................................................. 12
Figure 1-3 E-PGM+ .............................................................................................................................. 13
Figure 1-4 PGMPlusLC-II .................................................................................................................... 14
Figure 1-5 Gang programmer ............................................................................................................... 14
Figure 2-1 Block Diagram of MC96FR364B ....................................................................................... 15
Figure 3-1 28 TSSOP Pinout MC96FR364BR ..................................................................................... 16
Figure 4-1 PKG DIMENSION (28 TSSOP)......................................................................................... 18
Figure 6-1 General I/O.......................................................................................................................... 21
Figure 6-2 I/O with external interrupt function .................................................................................... 22
Figure 7-1 AC Timing .......................................................................................................................... 27
Figure 7-2 SPI master mode timing (UCPHA = 0, MSB first) ............................................................. 29
Figure 7-3 SPI / Synchronous master mode timing (UCPHA = 1, MSB first) ..................................... 29
Figure 7-4 SPI slave mode timing (UCPHA = 0, MSB first) ............................................................... 30
Figure 7-5 SPI / Synchronous slave mode timing (UCPHA = 1, MSB first)........................................ 30
Figure 7-6 IOL vs VOL ........................................................................................................................ 31
Figure 7-7 IOH vs VOH ....................................................................................................................... 31
Figure 8-1 Program Memory ................................................................................................................ 33
Figure 8-2 DATA MEMORY (IRAM)................................................................................................. 34
Figure 8-3 Lower 128 Byte of IRAM ................................................................................................... 35
Figure 8-4 PSW Register ...................................................................................................................... 37
Figure 8-5 DATA MEMORY (XRAM) ............................................................................................... 38
Figure 10-1 External Interrupt trigger condition................................................................................... 52
Figure 10-2 Block Diagram of Interrupt Controller.............................................................................. 53
Figure 10-3 Sequence of Interrupt handling ......................................................................................... 55
Figure 10-4 Effective time of interrupt request after setting IEx registers ........................................... 56
Figure 10-5 Accept of another interrupt request in interrupt service routine........................................ 56
Figure 10-6 Interrupt Request and Service Procedure .......................................................................... 57
Figure 10-7 Generating branch address to BIT interrupt service routine from vector table ................. 57
Figure 10-8 Processing General registers while an interrupt is serviced .............................................. 58
Figure 10-9 Timing chart for Interrupt Accept and Branch Address Generation ................................. 58
Figure 11-1 Block Diagram of Clock Generator .................................................................................. 65
Figure 11-2 Block Diagram of BIT ...................................................................................................... 67
Figure 11-3 Block Diagram .................................................................................................................. 70
Figure 11-4 WDT Interrupt and Reset Timing ..................................................................................... 72
Figure 11-5 Block Diagram of Timer 0,1 in 8-bit timer/counter mode ................................................ 74
Figure 11-6 Interrupt Period of Timer 0, 1 ........................................................................................... 75
Figure 11-7 Counter Operation of Timer 0, 1 ....................................................................................... 75
Figure 11-8 Block Diagram of Timer 0, 1 in 16-bit Timer/ Counter mode .......................................... 76
Figure 11-9 Block Diagram of Timer 0, 1 in 8-bit Capture mode ........................................................ 78

MC96FR364B
November, 2018 Rev.1.4 7
Figure 11-10 Timer 0,1 Operation in 8-bit Input Capture Mode .......................................................... 79
Figure 11-11 Example of Capture Interval Calculation in 8-bit Input Capture Mode .......................... 79
Figure 11-12 Block Diagram of Timer 0, 1 in 16-bit Capture Mode.................................................... 80
Figure 11-13 Block Diagram of Timer 1 in PWM mode...................................................................... 81
Figure 11-14 Example of PWM Waveform (In case frequency of SCLK(=fSCLK) is 4MHz)............... 82
Figure 11-15 Behaviour of waveform when changing period (In case fSCLK is 4MHz)........................ 82
Figure 11-16 Block Diagram of 16-bit Timer 2 in Output Compare or Event Counter Mode ............. 87
Figure 11-17 Block Diagram of Timer 2 in Capture Mode .................................................................. 87
Figure 11-18 Block Diagram of Timer 2 in Carrier Counting Mode .................................................... 88
Figure 11-19 Block Diagram of Timer 3 in Output Compare or Event Counter Mode ........................ 92
Figure 11-20 Block Diagram of Timer 3 in Capture Mode .................................................................. 93
Figure 11-21 Block Diagram of Timer 3 in Carrier Counting Mode.................................................... 94
Figure 11-22 Block Diagram of Timer 3 in PWM Mode ..................................................................... 95
Figure 11-23 Example of PWM waveform (In case of fSCLK=4MHz) .................................................. 96
Figure 11-24 Block Diagram of Watch Timer in Normal mode......................................................... 101
Figure 11-25 Block Diagram of Watch Timer in IR capture mode .................................................... 102
Figure 11-26 Timing Diagram of Watch Timer in IR capture mode .................................................. 102
Figure 11-27 Block Diagram of IR Capture function ......................................................................... 107
Figure 11-28 Block Diagram of IR AMP ........................................................................................... 107
Figure 11-29 Block Diagram of Carrier Generator............................................................................. 111
Figure 11-30 Period of Carrier signal and Remote data pulse ............................................................ 115
Figure 11-31 REMOUT by CRF & ROB (In case of CEN=1, RDPE=1) .......................................... 116
Figure 11-32 REMOUT by ROB only (In case of CEN=0, RDPE=1) ............................................... 116
Figure 11-33 REMOUT by RODR..................................................................................................... 117
Figure 11-34 Block Diagram of KEYSCAN module ......................................................................... 119
Figure 11-35 The Block Diagram of USART..................................................................................... 123
Figure 11-36 The Block Diagram of Clock Generation...................................................................... 124
Figure 11-37 Synchronous Mode XCKn Timing. .............................................................................. 125
Figure 11-38 frame format.................................................................................................................. 126
Figure 11-39 Start Bit Sampling ......................................................................................................... 129
Figure 11-40 The Sampling of Data and Parity Bit ............................................................................ 130
Figure 11-41 Stop Bit Sampling and Next Start Bit Sampling ........................................................... 130
Figure 11-42 SPI Clock Formats when UCPHA=0 ............................................................................ 132
Figure 11-43 SPI Clock Formats when UCPHA=1 ............................................................................ 133
Figure 11-44 I2C Block Diagram........................................................................................................ 140
Figure 11-45 Bit Transfer on the I2C-Bus........................................................................................... 141
Figure 11-46 START and STOP Condition........................................................................................ 141
Figure 11-47 STOP or Repeated START Condition .......................................................................... 142
Figure 11-48 Acknowledge on the I2C-Bus ........................................................................................ 142
Figure 11-49 Clock Synchronization during Arbitration Procedure ................................................... 143
Figure 11-50 Arbitration Procedure of Two Masters.......................................................................... 143
Figure 11-51 Formats and States in the Master Transmitter Mode..................................................... 146
Figure 11-52 Formats and States in the Master Receiver Mode ......................................................... 148
Figure 11-53 Formats and States in the Slave Transmitter Mode ....................................................... 150

MC96FR364B
8 November, 2018 Rev.1.4
Figure 11-54 Formats and States in the Slave Receiver Mode ........................................................... 152
Figure 12-1 Wake-up from SLEEP mode by an interrupt .................................................................. 158
Figure 12-2 SLEEP mode release by an external reset ....................................................................... 158
Figure 12-3 Wake-up from STOP mode by an interrupt .................................................................... 159
Figure 12-4 STOP mode release by an external reset ......................................................................... 159
Figure 12-5 Entry into STOP mode and Release sequence ................................................................ 160
Figure 12-6 Entry into BOD mode and Release sequence.................................................................. 161
Figure 13-1 Block Diagram of Reset Circuit ...................................................................................... 162
Figure 13-2 Noise Cancelling of External Reset Pin .......................................................................... 163
Figure 13-3 Reset Release Timing when Power is supplied (VDD Rises Rapidly) ........................... 163
Figure 13-4 Reset Release Timing when Power is supplied (VDD Rises Slowly)............................. 164
Figure 13-5 Fuse Configuration Value Read Timing after Power On ................................................ 164
Figure 13-6 Operation according to Power Level............................................................................... 165
Figure 13-7 Reset procedure due to external reset input..................................................................... 166
Figure 13-8 Example of oscillation..................................................................................................... 166
Figure 13-9 Block Diagram of BOD .................................................................................................. 167
Figure 13-10 Configuration value read timing when BOD RESET is asserted .................................. 168
Figure 14-1 Block Diagram of On-Chip Debug System..................................................................... 172
Figure 14-2 10-bit transmission packets ............................................................................................. 173
Figure 14-3 Data transfer on the twin bus........................................................................................... 173
Figure 14-4 Bit transfer on the serial bus............................................................................................ 174
Figure 14-5 Start and stop condition................................................................................................... 174
Figure 14-6 Acknowledge by receiver................................................................................................ 174
Figure 14-7 Clock synchronization during wait procedure................................................................. 175
Figure 14-8 Wire connection for serial communication ..................................................................... 175
Figure 15-1 Program Memory Address Space.................................................................................... 177
Figure 15-2 FLASH Memory Map ..................................................................................................... 184
Figure 15-3 FLASH Memory Address generation ............................................................................. 184

MC96FR364B
November, 2018 Rev.1.4 9
MC96FR364B
CMOS 8-bit Flash Microcontroller : UR
1. OVERVIEW
1.1 Description
The MC96FR364B is an advanced 8-bit microcontroller based on CMOS process with 64K Bytes of
Flash. This is a powerful device which provides a highly flexible and cost effective solution to many
embedded control applications.
The MC96FR364B provides the following features : 64K Bytes of embedded FLASH ROMNOTE1, 1792
Bytes of XRAM, 256 Bytes of IRAM, 8/16-bit Timer/Counter, WDT, WT, 10-bit PWM, USART(w/ SPI
function), I2C, Carrier Generator, 8-bit Basic Interval Timer, Watch Timer and Clock control circuit. It
also provides one dedicated output pin which has large current drivability specialized for remote
control application. Additionally, the MC96FR364B supports power saving modes to reduce power
consumption.
NOTE1 In this document, the ROM means non-volitile memory which is read-writable.
Device Name
FLASH size
IRAM
XRAM
I/O PORT
Package
MC96FR364B
64KB
256B
1792B
23
28 TSSOP
1.2 Features
•CPU
8-bit CISC Core (8051 Compatible, 2 clocks
per cycle)
•64K Bytes On-chip FLASH
Endurance : 10,000 times
Retention : 10 years
•XRAM
1792 Bytes
•IRAM
256 Bytes
•General Purpose I/O
23/27 Ports (P0[7:0],P1[7:0],P2[2:0],P3[7:0])
•One Basic Interval Timer
•Timer / Counter
8-bit×2ch(16-bit×1ch) + 16-bit×2ch
•10-bit PWM(Using Timer0,1)
•One Watch Dog Timer
•One Watch Timer
•Two USART(with SPI feature)
•One I2C
•One Carrier Generator
•Key scan module
P0[7:0], P1[7:0]
•Interrupt Sources
External : 4
Pin Change Interrupt(P0) : 1
USART: 4
I2C : 1
Key scan : 1
Carrier Generator : 1
WDT :1
WT : 1
BIT :1
Timer0,1,2,3 : 4

MC96FR364B
10 November, 2018 Rev.1.4
FLASH : 1
•Flash secure protection
•Analog Comparator for IR learning
•Power On Reset
•Programmable Brown-Out Detector
•Minimum Instruction Execution Time
200ns (@10MHz, 1 Cycle NOP Instruction)
•Power down mode
SLEEP, STOP mode
•Operating Frequency
1 ~ 12MHz
•Operating Voltage
1.75 ~ 3.6V (@ 1 ~ 12MHz)
•Operating Temperature
-20 ~ +70℃
•PKG Type
28 TSSOP
Available Pb free package
1.3 Ordering Information
Device name
ROM size
IRAM size
XRAM size
Package
MC96FR364BDBR
64KB FLASH
256B
1792B
28 TSSOP
Table 1-1 Ordering Information

MC96FR364B
November, 2018 Rev.1.4 11
1.3.1 Device Nomenclature
Device nomenclature
MC96FR364Bx Family Name
Package type
RoHS
Packing
MC96FR364Bx RB(T)
RTSSOP
Halogen Free
(T) Tape & Reel
B
X=none MC96FR364B series
MC96FR364BD series
X=D
Figure 1-1 Device Nomenclature

MC96FR364B
12 November, 2018 Rev.1.4
1.4 Development Tools
1.4.1 Compiler
ABOV semiconductor does not provide any compiler for MC96FR364B. As the CPU core of
MC96FR364B is Mentor 8051, you can use all kinds of third party’s standard 8051 compiler.
1.4.2 OCD emulator and debugger
OCD(On Chip Debugger) program is a debugging software for ABOV semiconductor’s 8051 MCU
series. OCD uses only two lines to download a user code, to read and modify the internal memory or
SFR(Special Function Register)s. And also OCD controls MCU’s internal debugging logic, which
means OCD controls emulation, step run, monitoring, etc.
OCD debugger program works on Microsoft-Windows 7, NT, 2000, XP, Vista(32-bit) operating system.
If you want to see details more, please refer to OCD debugger manual. You can download debugger
S/W and manual from out web-site.
The connecting pins between PC and MCU is as follows :
- DSCL (P2[1] of MC96FR364B)
- DSDA (P2[2] of MC96FR364B)
1.4.3 Programmer
To program or download user code into the ROM of MC96FR364B, ABOV semiconductor provides
several tools. As a single programmer which can program only one chip at a time, there are E-PGM+
and PGMPlusLC-II. On the other hand, you can program multi-chips at a time by using a gang
programmer. Gang programmer, E-GANG6, can program up to 6 devices simultaneously.
2. VDD
4. GND
6. Serial Clock (DSCL)
8. Serial Data (DSDA)
Figure 1-2 OCD Software and Connector

MC96FR364B
November, 2018 Rev.1.4 13
1.4.3.1 E-PGM+
E-PGM+ is a single write tool for ABOV MCUs.
Features :
Support ABOV / ADAM devices
2~5 times faster than S-PGM+
Main controller : 32 bit MCU @72MHz
Buffer memory : 1MB
1.4.3.2 PGMPlusLC-II
PGMPlusLC-II is for ISP (In System Programming). It is used to program or erase the MCU which is
already mounted on the target board using 10pin cable.
Features :
PGMPlusLC-II is low cost writing tool
USB interface is supported
No need for USB driver installation
Connect to the external power adaptor (5V@2A)
Fast 32-bit Cortex-M3 MCU is used
Support high voltage up to max 18V
PGMPlusLC-II is based on PC environment
PGMPlusLC-II is faster than PGMplusLC
Transmission speed of 64KB/s
Figure 1-3 E-PGM+
1. MCU RX
2. VDD
3. MCU TX
4. GND
5. Run Flag or Boot Pin
6. Serial Clock (DSCL)
7. GND
8. Serial Data (DSDA)
9. N/A
10. VPP or Reset Pin
Enter Key Connector.
To connect with the auto-
handler
Power DC 9 ~ 15V
For ISP (In-System-Programming)
For Barcode reader

MC96FR364B
14 November, 2018 Rev.1.4
1.4.3.3 E-GANG4(6)
The gang programmer, E-GANG4/(6) can program maximum4(6) MCUs at a time. So it is mainly used
in mass production line. As gang programmer is standalone type, it does not require host PC.
2. VDD
4. GND
6. Serial Clock (DSCL)
8. Serial Data (DSDA)
Figure 1-4 PGMPlusLC-II
Figure 1-5 Gang programmer

MC96FR364B
November, 2018 Rev.1.4 15
2. BLOCK DIAGRAM
*Note: P32, P33, P34, and P35 do not have a pin in the PKG, but the port setting must be set to Input
pull up, so there is no leakage current.
PIN
Type
Option
Remarks
P20
I/O
RESETB
FUSE Control
P0
PORT
AMP /
IR Control
TIMER
&
PWM
INTERRUPT
CONTROLLER
KEYSCAN
USART0 /
SPI0
P1
PORT
P2
PORT
P3
PORT
I2C
BIT
CLOCK /
SYSTEM
CONTROL
On-Chip
Debug
M8051
CORE
RAM
(1792B + 256B)
FLASH
(64KB)
Power On
Reset
Brown Out
Detector
CARRIER
GENERATOR
P01/T1/PWM1
REMOUT
P04/EC0
P00/T0
P02/T2
P03/PWM3
P36(P12)/INT0
P37(P13)/INT1
P21(P14)/INT2
P22(P15)/INT3
P07~P00
P17~P10
P16/MOSI0
P07~P00
P17~P10
P22~P20
P37~P30
Voltage Down
Converter
XIN
XOUT
RESETB/P20
P21/DSCL
P22/DSDA
VDD
VSS
USART1 /
SPI1
P10/MOSI1
WT
P31/SENSOR
P31(P36)/XCK
0
P17/MISO0
P30(P37)/SS0
P15/XCK1
P11/MISO1
P14/SS1
P30/EC2
P05/EC3
WDT
P22(P10)/
SDA
P21(P11)/
SCL
P32/SIGNAL
P30/EXTREF
Figure 2-1 Block Diagram of MC96FR364B

MC96FR364B
16 November, 2018 Rev.1.4
3. PIN CONFIGURATIONS
28 TSSOP (MC96FR364BR)
VDD
REMOUT
P22/INT3/SDA/DSDA
P21/INT2/SCL/DSCL
P07/KS7
P06/KS6
P05/KS5/EC3
P04/KS4/EC0
P03/KS3/T3/PWM3
P02/KS2/T2
P01/KS1/T1/PWM1
P00/KS0/T0
P37/INT1/SS0/SDA
P36/INT0/XCK0/SCL
VSS
XIN
XOUT
P20/RESETB
P10/KS8/MOSI1
P11/KS9/MISO1
P12/KS10/INT0
P13/KS11/INT1
P14/KS12/SS1/INT2
P15/KS13/XCK1/INT3
P16/KS14/MOSI0
P17/KS15/MISO0
P30/SS0/EC2/EXTREF
P31/XCK0/SENSOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
MC96FR364BR
15
16
Figure 3-1 28 TSSOP Pinout MC96FR364BR

MC96FR364B
November, 2018 Rev.1.4 17
4. PACKAGE DIMENSION

MC96FR364B
18 November, 2018 Rev.1.4
Figure 4-1 PKG DIMENSION (28 TSSOP)

MC96FR364B
November, 2018 Rev.1.4 19
5. PIN DESCRIPTION
PIN
Name
I/O
Function
@RESET
Shared with
P00
I/O
- 8-bit I/O port, P0.
- Can be set in input or output mode bitwise.
- Internal pull-up resistor can be activated by
setting PxnPU bit in PxPU register when this
port is used as input port.
- Can be configured as an open drain output
mode by setting PxnOD bit in PxOD register.
Input
KS0/T0
P01
KS1/T1/PWM1
P02
KS2/T2
P03
KS3/T3/PWM3
P04
KS4/EC0
P05
KS5
P06
KS6
P07
KS7
P10
I/O
8-bit I/O port, P1.
- Can be set in input or output mode bitwise.
- Internal pull-up resistor can be activated by
setting PxnPU bit in PxPU register when this
port is used as input port.
- Can be configured as an open drain output
mode by setting PxnOD bit in PxOD register.
Input
KS8/MOSI1
P11
KS9/MISO1
P12
KS10/INT0 NOTE0
P13
KS11/INT1 NOTE0
P14
KS12/SS1/
INT2 NOTE0
P15
KS13/XCK1/
INT3 NOTE0
P16
KS14/MOSI0
P17
KS15/MISO0
P20
I/O
- 3-bit I/O port, P2.
- Can be set in input or output mode bitwise.
- Internal pull-up resistor can be activated by
setting PxnPU bit in PxPU register when this
port is used as input port.
- Can be configured as an open drain output
mode by setting PxnOD bit in PxOD register.
Input
RESETB NOTE1
P21
INT2/DSCL/
SCL NOTE2
P22
INT3/DSDA/
SDA NOTE2
-
-
-
NOTE0 INT3,2,1,0 can be triggered on P2[2:1], P3[7:6] ports when appropriate bits in PSR0 register are set.
NOTE1 When P20 is used as a external reset pin(=RESETB) by the FUSE configuration, this pin is configured as
an input port with internal pull-up resistor on.
NOTE2 SDA and SCL ports can be switched to P3[7:6] ports when appropriate bits in PSR0 register are set.

MC96FR364B
20 November, 2018 Rev.1.4
PIN
Name
I/O
Function
@RESET
Shared with
P30
I/O
- 8-bit I/O port, P3.
- Can be set in input or output mode bitwise.
- Internal pull-up resistor can be activated by
setting PxnPU bit in PxPU register when this
port is used as input port.
- Can be configured as an open drain output
mode by setting PxnOD bit in PxOD register.
Input
SS0/EC2/EXTR
EF
P31
XCK0/ SENSOR
P32
SIGNAL
P33
-
P34
-
P35
-
P36
INT0/XCK0
P37
INT1/SS0
XIN
I
Oscillator input
-
XOUT
O
Oscillator output
-
REMOUT
O
Push-pull high current output
-