Abov A96G150 User manual

A96G150
User’s Manual
16 MHz 8-bit A96G150 Microcontroller
64 Kbyte Flash memory, 2Kbyte EEPROM, 12-bit ADC,
6 Timers, USART, USI, High Current Port
Version 1.00
Global Top Smart MCU Innovator, ABOV Semiconductor
www.abovsemi.com
Introduction
This user’s manual targets application developers who use A96G150 for their specific needs. It provides
complete information of how to use A96G150 device. Standard functions and blocks including
corresponding register information of A96G150 are introduced in each chapter, while instruction set is
in Appendix.
A96G150 is based on M8051 core and provides standard features of 8051 such as 8-bit ALU, PC, 8-bit
registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data bus and 2x16-
bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
64Kbytes of FLASH, 256bytes of IRAM, 2304bytes of XRAM, 2Kbytes of Data EEPROM, general
purpose I/O, basic interval timer, watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM
output, 16-bit PWM output, watch timer, buzzer driving port, USI, 12-bit A/D converter, on-chip POR,
LVR, LVI, on-chip oscillator and clock circuitry.
As a field proven best seller, A96G150 has been sold more than 3 billion units up to now, and introduces
rich features such as excellent noise immunity, code optimization, cost effectiveness, and so on.
Reference document
A96G150 programming tools and manuals released by ABOV: They are available at ABOV
website, www.abovsemi.com.
SDK-51 User’s guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel’s 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentorwebsite: https://www.mentor.com/products/ip/peripheral/microcontroller/

Contents A96G150 User's manual
2
Contents
Introduction..............................................................................................................................................1
Reference document...............................................................................................................................1
1Description ...................................................................................................................................14
1.1 Device overview................................................................................................................14
1.2 A96G150 block diagram....................................................................................................17
2Pinouts and pin description..........................................................................................................18
2.1 Pinouts ..............................................................................................................................18
2.2 Pin description...................................................................................................................19
3Port structures..............................................................................................................................25
4Central Processing Unit (CPU) ....................................................................................................27
4.1 Architecture and registers .................................................................................................27
4.2 Addressing ........................................................................................................................29
4.3 Instruction set....................................................................................................................30
5Memory organization....................................................................................................................32
5.1 Program memory...............................................................................................................32
5.2 Data memory.....................................................................................................................34
5.3 EEPROM data memory and external data memory..........................................................36
5.4 SFR map...........................................................................................................................37
5.4.1 SFR map summary...............................................................................................37
5.4.2 SFR map...............................................................................................................39
5.4.3 Compiler compatible SFR.....................................................................................46
6I/O ports .......................................................................................................................................48
6.1 Port register.......................................................................................................................48
6.1.1 Data register (Px) .................................................................................................48
6.1.2 Direction register (PxIO).......................................................................................48
6.1.3 Pull-up register selection register (PxPU) ............................................................48
6.1.4 Open-drain selection register (PxOD) ..................................................................48
6.1.5 De-bounce enable register (PxDB) ......................................................................48
6.1.6 Port function selection register (PxFSR) ..............................................................48
6.1.7 Register map ........................................................................................................49
6.2 P0 port...............................................................................................................................50
6.2.1 P0 port description................................................................................................50
6.2.2 Register description for P0...................................................................................50
6.3 P1 port...............................................................................................................................54
6.3.1 P1 port description................................................................................................54
6.3.2 Register description for P1...................................................................................54
6.4 P2 port...............................................................................................................................58
6.4.1 P2 port description................................................................................................58
6.4.2 Register description for P2...................................................................................58
6.5 P3 port...............................................................................................................................61
6.5.1 P3 port description................................................................................................61
6.5.2 Register description for P3...................................................................................61
6.6 P4 port...............................................................................................................................64
6.6.1 P4 port description................................................................................................64
6.6.2 Register description for P4...................................................................................64
6.7 P5 port...............................................................................................................................67
6.7.1 P5 port description................................................................................................67
6.7.2 Register description for P5...................................................................................67

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7Interrupt controller........................................................................................................................69
7.1 External interrupt...............................................................................................................71
7.2 Block diagram....................................................................................................................72
7.3 Interrupt vector table .........................................................................................................73
7.4 Interrupt sequence ............................................................................................................74
7.5 Effective timing after controlling interrupt bit.....................................................................75
7.6 Multi-interrupt ....................................................................................................................76
7.7 Interrupt enable accept timing...........................................................................................77
7.8 Interrupt service routine address.......................................................................................78
7.9 Saving/restore general purpose registers.........................................................................79
7.10 Interrupt timing ..................................................................................................................80
7.11 Interrupt register overview.................................................................................................81
7.11.1 Interrupt Enable register (IE, IE1, IE2, and IE3)...................................................81
7.11.2 Interrupt priority register (IP and IP1)...................................................................81
7.11.3 External interrupt flag register (EIFLAG0 and EIFLAG1).....................................81
7.11.4 External interrupt polarity register (EIPOL0L, EIPOL0H, and EIPOL1) ...............81
7.11.5 Register map ........................................................................................................82
7.11.6 Interrupt register description.................................................................................83
8Clock generator............................................................................................................................89
8.1 Clock generator block diagram .........................................................................................90
8.2 Register map.....................................................................................................................91
8.3 Register description ..........................................................................................................92
9Basic Interval Timer (BIT) ............................................................................................................94
9.1 BIT block diagram .............................................................................................................94
9.2 BIT register map................................................................................................................95
9.3 BIT register description .....................................................................................................96
10 Watchdog Timer (WDT) ...............................................................................................................97
10.1 WDT interrupt timing waveform.........................................................................................97
10.2 WDT block diagram...........................................................................................................98
10.3 Register map.....................................................................................................................99
10.4 Register description ........................................................................................................100
11 Watch Timer (WT)......................................................................................................................101
11.1 WT block diagram ...........................................................................................................101
11.2 Register map...................................................................................................................102
11.3 Watch Timer register description ....................................................................................103
12 Timer 0/1/2/3/4/5........................................................................................................................105
12.1 Timer 0 ............................................................................................................................105
12.1.1 8-bit timer/counter mode.....................................................................................105
12.1.2 8-bit PWM mode.................................................................................................107
12.1.3 8-bit capture mode..............................................................................................109
12.1.4 Timer 0 block diagram........................................................................................111
12.1.5 Register map ......................................................................................................111
12.1.6 Register description............................................................................................112
12.2 Timer 1 ............................................................................................................................114
12.2.1 16-bit timer/counter mode...................................................................................114
12.2.2 16-bit capture mode............................................................................................116
12.2.3 16-bit PPG mode................................................................................................118
12.2.4 16-bit timer 1 block diagram...............................................................................120
12.2.5 Register map ......................................................................................................120
12.2.6 Register description............................................................................................121

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12.3 Timer 2 ............................................................................................................................124
12.3.1 16-bit timer/counter mode...................................................................................125
12.3.2 16-bit capture mode............................................................................................127
12.3.3 16-bit PPG mode................................................................................................129
12.3.4 16-bit timer 2 block diagram...............................................................................131
12.3.5 Register map ......................................................................................................131
12.3.6 Register description............................................................................................132
12.4 Timer 3 ............................................................................................................................134
12.4.1 16-bit timer/counter mode...................................................................................135
12.4.2 16-bit capture mode............................................................................................137
12.4.3 16-bit PPG mode................................................................................................139
12.4.4 16-bit timer 3 block diagram...............................................................................141
12.4.5 Register map ......................................................................................................141
12.4.6 Register description............................................................................................142
12.5 Timer 4 ............................................................................................................................145
12.5.1 16-bit timer/counter mode...................................................................................146
12.5.2 16-bit capture mode............................................................................................148
12.5.3 16-bit PPG mode................................................................................................150
12.5.4 16-bit timer 4 block diagram...............................................................................152
12.5.5 Register map ......................................................................................................152
12.5.6 Register description............................................................................................153
12.6 Timer 5 ............................................................................................................................155
12.6.1 16-bit timer/counter mode...................................................................................156
12.6.2 16-bit capture mode............................................................................................158
12.6.3 16-bit PPG mode................................................................................................160
12.6.4 16-bit timer 5 block diagram...............................................................................162
12.6.5 Register map ......................................................................................................162
12.6.6 Register description............................................................................................163
13 Buzzer driver..............................................................................................................................165
13.1 Buzzer driver block diagram............................................................................................165
13.2 Register map...................................................................................................................166
13.3 Register description ........................................................................................................167
14 12-bit ADC..................................................................................................................................168
14.1 Conversion timing............................................................................................................168
14.2 Block diagram..................................................................................................................169
14.3 ADC operation.................................................................................................................170
14.4 Register map...................................................................................................................172
14.5 Register description ........................................................................................................173
15 Combination of USART, SPI, and I2C (USI)..............................................................................176
15.1 USIn UART mode............................................................................................................177
15.2 USIn UART block diagram..............................................................................................178
15.3 USIn clock generation.....................................................................................................179
15.4 USIn external clock (SCKn) ............................................................................................180
15.5 USIn synchronous mode operation.................................................................................181
15.6 USIn UART data format ..................................................................................................182
15.7 USIn UART parity bit.......................................................................................................183
15.8 USIn UART transmitter ...................................................................................................183
15.8.1 USIn UART sending TX data..............................................................................183
15.8.2 USIn UART transmitter flag and interrupt...........................................................184
15.8.3 USIn UART parity generator...............................................................................184

A96G150 User's manual Contents
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15.8.4 USIn UART disabling transmitter .......................................................................184
15.9 USIn UART receiver........................................................................................................185
15.9.1 USIn UART receiver RX data.............................................................................185
15.9.2 USIn UART receiver flag and interrupt...............................................................185
15.9.3 USIn UART parity checker .................................................................................186
15.9.4 USIn UART disabling receiver............................................................................186
15.9.5 USIn Asynchronous data reception....................................................................186
15.10 USIn SPI mode................................................................................................................189
15.11 USIn SPI clock formats and timing..................................................................................190
15.12 USIn SPI block diagram..................................................................................................193
15.13 USIn I2C mode................................................................................................................194
15.14 USIn I2C bit transfer........................................................................................................195
15.15 USIn I2C START/repeated START/STOP......................................................................196
15.16 USIn I2C data transfer ....................................................................................................197
15.17 USIn I2C acknowledge....................................................................................................198
15.18 USIn I2C synchronization/arbitration...............................................................................199
15.19 USIn I2C operation..........................................................................................................200
15.19.1USIn I2C master transmitter...............................................................................200
15.19.2USIn I2C master receiver...................................................................................202
15.19.3USIn I2C slave transmitter..................................................................................204
15.19.4USIn I2C slave receiver......................................................................................205
15.20 USIn I2C block diagram ..................................................................................................207
15.21 Register map...................................................................................................................208
15.22 USIn register description.................................................................................................209
15.23 Baud rate settings (example) ..........................................................................................217
16 USART2.....................................................................................................................................219
16.1 Block diagram..................................................................................................................220
16.2 Clock generation .............................................................................................................221
16.3 External clock (XCK).......................................................................................................222
16.4 Synchronous mode operation.........................................................................................223
16.5 Data format......................................................................................................................224
16.6 Parity bit ..........................................................................................................................225
16.7 USART2 transmitter........................................................................................................226
16.7.1 Sending Tx data .................................................................................................226
16.7.2 Transmitter flag and interrupt .............................................................................226
16.7.3 Parity generator..................................................................................................227
16.7.4 Disabling transmitter...........................................................................................227
16.8 USART2 receiver ............................................................................................................228
16.8.1 Receiving Rx data ..............................................................................................228
16.8.2 Receiver flag and interrupt .................................................................................228
16.8.3 Parity checker.....................................................................................................229
16.8.4 Disabling receiver...............................................................................................229
16.8.5 Asynchronous data reception.............................................................................229
16.9 SPI mode.........................................................................................................................232
16.9.1 SPI clock formats and timing..............................................................................232
16.10 Receiver time out (RTO) .................................................................................................235
16.11 Register map...................................................................................................................236
16.12 Register description ........................................................................................................237
16.13 Baud rate settings (example) ..........................................................................................244
16.14 0% Error baud rate..........................................................................................................245

Contents A96G150 User's manual
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17 LCD Driver .................................................................................................................................246
17.1 LCD Display RAM organization.......................................................................................247
17.2 LCD Signal waveform .....................................................................................................248
17.3 Internal resistor bias connection .....................................................................................251
17.4 External resistor bias connection ....................................................................................252
17.5 LCD Automatic bias control timing..................................................................................253
17.6 Block diagram..................................................................................................................254
17.7 Register map...................................................................................................................255
17.8 Register description ........................................................................................................256
18 Cyclic Redundancy Check (CRC)..............................................................................................260
18.1 Block diagram..................................................................................................................260
18.2 Register map...................................................................................................................261
18.3 Register description ........................................................................................................262
18.4 Polynomial.......................................................................................................................264
19 Power down operation ...............................................................................................................265
19.1 Peripheral operation in IDLE/STOP mode......................................................................266
19.2 IDLE mode ......................................................................................................................267
19.3 STOP mode.....................................................................................................................268
19.4 Released operation of STOP mode................................................................................269
19.5 Register map...................................................................................................................270
19.6 Register description ........................................................................................................270
20 Reset..........................................................................................................................................271
20.1 Reset block diagram .......................................................................................................271
20.2 Power on reset................................................................................................................272
20.3 External resetb input .......................................................................................................275
20.4 Low voltage reset process ..............................................................................................276
20.5 LVI block diagram............................................................................................................278
20.6 Register map...................................................................................................................279
20.7 Reset operation register description ...............................................................................280
21 Memory programming................................................................................................................283
21.1 Flash control and status registers ...................................................................................283
21.1.1 Register map ......................................................................................................283
21.1.2 Register description............................................................................................284
21.2 Memory map ...................................................................................................................291
21.2.1 Flash memory map.............................................................................................291
21.2.2 Data EEPROM memory map .............................................................................292
21.3 Serial In-system Program (ISP) mode ............................................................................293
21.3.1 Flash operation...................................................................................................293
21.3.2 Data EEPROM operation ...................................................................................300
21.4 Mode entrance method of ISP mode ..............................................................................303
21.4.1 Mode entrance method for ISP ..........................................................................303
21.5 Security ...........................................................................................................................304
21.6 Configure option..............................................................................................................305
22 Development tools .....................................................................................................................307
22.1 Compiler..........................................................................................................................307
22.2 Core and debug tool information.....................................................................................308
22.2.1 Feature of 94/96/97 Series core.........................................................................308
22.2.2 OCD type of 94/96/97 Series core .....................................................................310
22.2.3 Interrupt priority of 94/96/97 Series core............................................................311
22.2.4 Extended Stack Pointer of 94/96/97 Series core ...............................................312

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22.3 OCD (On-chip debugger) emulator and debugger..........................................................313
22.3.1 On-chip debug system........................................................................................315
22.3.2 Entering debug mode .........................................................................................316
22.3.3 Two-wire communication protocol......................................................................317
22.4 Programmers...................................................................................................................321
22.4.1 E-PGM+..............................................................................................................321
22.4.2 OCD emulator.....................................................................................................321
22.4.3 Gang programmer ..............................................................................................322
22.5 Flash programming .........................................................................................................323
22.5.1 On-board programming......................................................................................323
22.6 Connection of transmission.............................................................................................324
22.7 Circuit design guide.........................................................................................................325
Appendix .............................................................................................................................................327
Instruction table..........................................................................................................................327
Revision history...................................................................................................................................333

List of figures A96G150 User's manual
8
List of figures
Figure 1. A96G150 Block Diagram .......................................................................................................17
Figure 2. A96G150 44LQFP-1010 Pin Assignment ..............................................................................18
Figure 3. General Purpose I/O Port ......................................................................................................25
Figure 4. External Interrupt I/O Port ......................................................................................................26
Figure 5. M8051EW Architecture ..........................................................................................................27
Figure 6. Program Memory Map ...........................................................................................................33
Figure 7. Data Memory Map .................................................................................................................34
Figure 8. Lower 128bytes of RAM ........................................................................................................35
Figure 9. XDATA Memory Area .............................................................................................................36
Figure 10. Interrupt Group Priority Level...............................................................................................70
Figure 11. External Interrupt Description ..............................................................................................71
Figure 12. Interrupt Controller Block Diagram ......................................................................................72
Figure 13. Interrupt Sequence Flow......................................................................................................74
Figure 14. Effective Timing of Interrupt Enable Register ......................................................................75
Figure 15. Effective Timing of Interrupt Flag Register...........................................................................75
Figure 16. Effective Timing of Multi-interrupt ........................................................................................76
Figure 17. Interrupt Response Timing Diagram ....................................................................................77
Figure 18. Correspondence between Vector Table Address and the Entry Address of ISR .................78
Figure 19. Saving/Restore Process Diagram and Sample Source.......................................................79
Figure 20. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction ...............................80
Figure 21. Clock Generator Block Diagram ..........................................................................................90
Figure 22. Basic Interval Timer Block Diagram.....................................................................................94
Figure 23. Watchdog Timer Interrupt Timing Waveform .......................................................................97
Figure 24. Watchdog Timer Block Diagram ..........................................................................................98
Figure 25. Watch Timer Block Diagram ..............................................................................................101
Figure 26. 8-bit Timer/Counter Mode for Timer 0................................................................................106
Figure 27. 8-bit Timer/Counter 0 Example ..........................................................................................106
Figure 28. 8-bit PWM Mode for Timer 0..............................................................................................107
Figure 29. PWM Output Waveforms in PWM Mode for Timer 0 .........................................................108
Figure 30. 8-bit Capture Mode for Timer 0..........................................................................................109
Figure 31. Input Capture Mode Operation for Timer 0 ........................................................................110
Figure 32. Express Timer Overflow in Capture Mode .........................................................................110
Figure 33. 8-bit Timer 0 Block Diagram .............................................................................................. 111
Figure 34. 16-bit Timer/Counter Mode of Timer 1 ...............................................................................115
Figure 35. 16-bit Timer/Counter Mode Operation Example ................................................................115
Figure 36. 16-bit Capture Mode of Timer 1 .........................................................................................116
Figure 37. 16-bit Capture Mode Operation Example ..........................................................................117
Figure 38. Express Timer Overflow in Capture Mode .........................................................................117
Figure 39. 16-bit PPG Mode of Timer 1 ..............................................................................................118
Figure 40. 16-bit PPG Mode Operation Example ...............................................................................119
Figure 41. 16-bit Timer 1 Block Diagram ............................................................................................120
Figure 42. 16-bit Timer/Counter Mode of Timer 2 ...............................................................................125
Figure 43. 16-bit Timer/Counter Mode Operation Example ................................................................126
Figure 44. 16-bit Capture Mode of Timer 2 .........................................................................................127
Figure 45. 16-bit Capture Mode Operation Example ..........................................................................128
Figure 46. Express Timer Overflow in Capture Mode .........................................................................128
Figure 47. 16-bit PPG Mode of Timer 2 ..............................................................................................129
Figure 48. 16-bit PPG Mode Operation Example ...............................................................................130

A96G150 User's manual List of figures
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Figure 49. 16-bit Timer 2 Block Diagram ............................................................................................131
Figure 50. 16-bit Timer/Counter Mode of Timer 3 ...............................................................................135
Figure 51. 16-bit Timer/Counter Mode Operation Example ................................................................136
Figure 52. 16-bit Capture Mode of Timer 3 .........................................................................................137
Figure 53. 16-bit Capture Mode Operation Example ..........................................................................138
Figure 54. Express Timer Overflow in Capture Mode .........................................................................138
Figure 55. 16-bit PPG Mode of Timer 3 ..............................................................................................139
Figure 56. 16-bit PPG Mode Operation Example ...............................................................................140
Figure 57. 16-bit Timer 3 Block Diagram ............................................................................................141
Figure 58. 16-bit Timer/Counter Mode of Timer 4 ...............................................................................146
Figure 59. 16-bit Timer/Counter Mode Operation Example ................................................................147
Figure 60. 16-bit Capture Mode of Timer 4 .........................................................................................148
Figure 61. 16-bit Capture Mode Operation Example ..........................................................................149
Figure 62. Express Timer Overflow in Capture Mode .........................................................................149
Figure 63. 16-bit PPG Mode of Timer 4 ..............................................................................................150
Figure 64. 16-bit PPG Mode Operation Example ...............................................................................151
Figure 65. 16-bit Timer 4 Block Diagram ............................................................................................152
Figure 66. 16-bit Timer/Counter Mode of Timer 5 ...............................................................................156
Figure 67. 16-bit Timer/Counter Mode Operation Example ................................................................157
Figure 68. 16-bit Capture Mode of Timer 5 .........................................................................................158
Figure 69. 16-bit Capture Mode Operation Example ..........................................................................159
Figure 70. Express Timer Overflow in Capture Mode .........................................................................159
Figure 71. 16-bit PPG Mode of Timer 5 ..............................................................................................160
Figure 72. 16-bit PPG Mode Operation Example ...............................................................................161
Figure 73. 16-bit Timer 5 Block Diagram ............................................................................................162
Figure 74. Buzzer Driver Block Diagram.............................................................................................165
Figure 75. 12-bit ADC Block Diagram .................................................................................................169
Figure 76. A/D Analog Input Pin with a Capacitor ...............................................................................169
Figure 77. A/D Power (AVREF) Pin with a Capacitor..........................................................................169
Figure 78. Control Registers and Align Bits ........................................................................................170
Figure 79. ADC Operation Flow Sequence .........................................................................................171
Figure 80. USIn USART Block Diagram (n = 0 and 1)........................................................................178
Figure 81. Clock Generation Block Diagram (USIn) ...........................................................................179
Figure 82. Synchronous Mode SCKn Timing (USIn) ..........................................................................181
Figure 83. Frame Formats (USIn) .......................................................................................................182
Figure 84. Asynchronous Start Bit Sampling (USIn)...........................................................................187
Figure 85. Asynchronous Sampling of Data and Parity Bit (USIn)......................................................188
Figure 86. Stop Bit Sampling and Next Start Bit Sampling (USIn) .....................................................188
Figure 87. USIn SPI Clock Formats when CPHAn = 0 .......................................................................191
Figure 88. USIn SPI Clock Formats when CPHAn = 1 .......................................................................192
Figure 89. USIn SPI Block Diagram (n = 0 and 1) ..............................................................................193
Figure 90. Bit Transfer on the I2C-Bus (USIn) ....................................................................................195
Figure 91. START and STOP Condition (USIn) ..................................................................................196
Figure 92. Data Transfer on the I2C-Bus (USIn).................................................................................197
Figure 93. Acknowledge on the I2C-Bus (USIn) .................................................................................198
Figure 94. Clock Synchronization during Arbitration Procedure (USIn)..............................................199
Figure 95. Arbitration Procedure of Two Masters (USIn) ....................................................................199
Figure 96. USIn I2C Block Diagram ....................................................................................................207
Figure 97. USART2 Block Diagram ....................................................................................................220
Figure 98. Clock Generation Block Diagram.......................................................................................221

List of figures A96G150 User's manual
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Figure 99. Synchronous Mode XCK Timing ........................................................................................223
Figure 100. A Frame Format ...............................................................................................................224
Figure 101. Start Bit Sampling ............................................................................................................230
Figure 102. Sampling of Data and Parity Bit.......................................................................................231
Figure 103. Stop Bit Sampling and Next Start Bit Sampling ...............................................................231
Figure 104. SPI Clock Formats when UCPHA = 0..............................................................................233
Figure 105. SPI Clock Formats when UCPHA = 1..............................................................................234
Figure 106. Example for RTO in USART2 ..........................................................................................235
Figure 107. 0% Error Baud Rate Block Diagram ................................................................................245
Figure 108. LCD Display RAM ............................................................................................................247
Figure 109. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)....................................................................248
Figure 110. LCD Signal Waveforms (1/4 Duty, 1/3 Bias) ....................................................................249
Figure 111. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) ....................................................................250
Figure 112. Internal Resistor Bias Connection....................................................................................251
Figure 113. External Resistor Bias Connection ..................................................................................252
Figure 114. LCD Automatic Bias Control Timing Diagram ..................................................................253
Figure 115. Block Diagram Figure.......................................................................................................254
Figure 116. CRC Block Diagram .........................................................................................................260
Figure 117. IDLE Mode Release Timing by an External Interrupt.......................................................267
Figure 118. STOP Mode Release Timing by External Interrupt ..........................................................268
Figure 119. STOP Mode Release Flow...............................................................................................269
Figure 120. Reset Block Diagram .......................................................................................................271
Figure 121. Fast VDD Rising Time .....................................................................................................272
Figure 122. Internal RESET Release Timing on Power-up ................................................................272
Figure 123. Configuration Timing when Power-on..............................................................................273
Figure 124. Boot Process Waveform ..................................................................................................274
Figure 125. Timing Diagram after RESET ..........................................................................................275
Figure 126. Oscillator Generating Waveform Example.......................................................................275
Figure 127. Block Diagram of LVR......................................................................................................276
Figure 128. Internal Reset at Power Fail Situation .............................................................................276
Figure 129. Configuration Timing When LVR RESET.........................................................................277
Figure 130. LVI Block Diagram ...........................................................................................................278
Figure 131. Read Device Internal Checksum (Full Size)....................................................................288
Figure 132. Read Device Internal Checksum (User Define Size).......................................................289
Figure 133. Flash Memory Map ..........................................................................................................291
Figure 134. Address Configuration of Flash Memory .........................................................................291
Figure 135. Data EEPROM Memory Map...........................................................................................292
Figure 136. Address Configuration of Data EEPROM Memory ..........................................................292
Figure 137. The Sequence of Page Program and Erase of Flash Memory........................................293
Figure 138. The Sequence of Bulk Erase of Flash Memory ...............................................................294
Figure 139. ISP Mode .........................................................................................................................303
Figure 140. Configuration of the Extended Stack Pointer...................................................................312
Figure 141. OCD 1 and OCD 2 Connector Pin Diagram ....................................................................314
Figure 142. Debugger (OCD1/OCD2) and Pinouts ............................................................................315
Figure 143. On-chip Debugging System in Block Diagram ................................................................316
Figure 144. Timing Diagram of Debug Mode Entry ............................................................................316
Figure 145. 10-bit Transmission Packet..............................................................................................318
Figure 146. Data Transfer on OCD .....................................................................................................318
Figure 147. Bit Transfer on Serial Bus ................................................................................................319
Figure 148. Start and Stop Condition..................................................................................................319

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Figure 149. Acknowledge on Serial Bus .............................................................................................320
Figure 150. Clock Synchronization during Wait Procedure ................................................................320
Figure 151. E-PGM+ (Single Writer) and Pinouts ...............................................................................321
Figure 152. E-Gang4 and E-Gang6 (for Mass Production) ................................................................322
Figure 153. Connection of Transmission ............................................................................................324
Figure 154. PCB Design Guide for On-board Programming ..............................................................326

List of tables A96G150 User's manual
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List of tables
Table 1. A96G150 Device Features and Peripheral Counts .................................................................14
Table 2. Normal Pin Description............................................................................................................19
Table 3. SFR Map Summary .................................................................................................................37
Table 4. XSFR Map Summary ..............................................................................................................38
Table 5. SFR Map .................................................................................................................................39
Table 6. XSFR Map ...............................................................................................................................43
Table 7. Port Register Map....................................................................................................................49
Table 8. Interrupt Vector Address Table ................................................................................................73
Table 9. Interrupt Register Map.............................................................................................................82
Table 10. Clock Generator Register Map..............................................................................................91
Table 11. Basic Interval Timer Register Map.........................................................................................95
Table 12. Watchdog Timer Register Map ..............................................................................................99
Table 13. Watch Timer Register Map ..................................................................................................102
Table 14. Timer 0 Operating Mode......................................................................................................105
Table 15. Timer 0 Register Map .......................................................................................................... 111
Table 16. TIMER 1 Operating Modes..................................................................................................114
Table 17. TIMER 1 Register Map ........................................................................................................120
Table 18. TIMER 2 Operating Modes..................................................................................................124
Table 19. TIMER 2 Register Map ........................................................................................................131
Table 20. TIMER 3 Operating Modes..................................................................................................134
Table 21. TIMER 3 Register Map ........................................................................................................141
Table 22. TIMER 4 Operating Modes..................................................................................................145
Table 23. TIMER 4 Register Map ........................................................................................................152
Table 24. TIMER 5 Operating Modes..................................................................................................155
Table 25. TIMER 5 Register Map ........................................................................................................162
Table 26. Buzzer Frequency at 8MHz.................................................................................................165
Table 27. Buzzer Driver Register Map ................................................................................................166
Table 28. ADC Register Map...............................................................................................................172
Table 29. Equations for Calculating USIn Baud Rate Register Setting ..............................................179
Table 30. CPOLn Functionality............................................................................................................190
Table 31. USI Register Map ................................................................................................................208
Table 32. Example1 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies ..217
Table 33. Example2 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies ..218
Table 34. Equations for Calculating Baud Rate Register Setting........................................................221
Table 35. CPOL Functionality..............................................................................................................232
Table 36. Example Condition of RTO..................................................................................................235
Table 37. USART2 Register Map ........................................................................................................236
Table 38. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies .......................244
Table 39. LCD Register Map ...............................................................................................................255
Table 40. CRC Mode...........................................................................................................................260
Table 41. CRC Register Map ..............................................................................................................261
Table 42. Peripheral Operation Status during Power Down Mode .....................................................266
Table 43. Power Down Operation Register Map.................................................................................270
Table 44. Hardware Setting Values in Reset State .............................................................................271
Table 45. Boot Process Description ....................................................................................................274
Table 46. Reset Operation Register Map............................................................................................279
Table 47. Flash Control and Status Register Map ..............................................................................283
Table 48. Program and Erase Time ....................................................................................................290

A96G150 User's manual List of tables
13
Table 49. Operation Mode...................................................................................................................299
Table 50. Mode Entrance Method for ISP ...........................................................................................303
Table 51. Security Policy using Lock Bits............................................................................................304
Table 52. Core and Debug Information ...............................................................................................308
Table 53. Core and Debug Interface by Series ...................................................................................308
Table 54. Feature Comparison Chart by Series and Cores ................................................................309
Table 55. OCD Type of Each Series ...................................................................................................310
Table 56. Comparison of OCD 1 and OCD 2 ......................................................................................310
Table 57. Interrupt Priorities in Groups and Levels .............................................................................311
Table 58. Debug Feature by Series ....................................................................................................313
Table 59. OCD 1 and OCD 2 Pin Description .....................................................................................314
Table 60. OCD Features .....................................................................................................................315
Table 61. Pins for Flash Programming ................................................................................................323
Table 62. Instruction Table ..................................................................................................................327

1. Description A96G150 User's manual
14
1Description
A96G150 is an advanced CMOS 8-bit microcontroller with 64Kbytes of FLASH. This is a powerful
microcontroller which provides a highly flexible and cost-effective solution to many embedded control
applications.
1.1 Device overview
In this section, features of A96G150 and peripheral counts are introduced.
Table 1. A96G150 Device Features and Peripheral Counts
Peripherals
Description
Core
CPU
8-bit CISC core (M8051, 2 clocks per cycle)
Interrupt
Up to 23 peripheral interrupts supported.
EINT40 to 47, EINT0, EINT1, EINT2, EINT3 (5)
Timer (0/1/2/3/4/5) (6)
WDT (1)
BIT (1)
WT (1)
USART (Rx, CRC)/Tx (2)
USI 2-ch. *Rx/Tx/I2C (6)
ADC (1)
LVI (1)
Memory
ROM (FLASH)
capacity
64 KB FLASH with self-read and write capability
In-system programming (ISP)
Endurance: 30,000 times
IRAM
256 bytes
XRAM
2304 bytes
EEPROM
2 KB
Endurance: 300,000 times at room temperature
Retention: 10 years
Programmable pulse generation
Pulse generation (by T1/T2/T3/T4/T5)
8-bit PWM (by T0)
Buzzer
8-bit ×1-ch
Minimum instruction execution
time
125 ns (@ 16 MHz main clock)
61 us (@ 32.768 kHz sub clock)
Power down mode
STOP mode
IDLE mode

A96G150 User's manual 1. Description
15
Table 1. A96G150 Device Features and Peripheral Counts (continued)
Peripherals
Description
General Purpose I/O (GPIO)
Normal I/O: 42 ports
High sink current port: 8 ports P3[7:0]
Reset
Power on
reset
Reset release level: 1.2 V
Low voltage
reset
16 levels detect
1.61 / 1.68 / 1.77 / 1.88 / 2.00 / 2.13 / 2.28 / 2.46 / 2.68 /
2.81 / 3.06 / 3.21 / 3.56 / 3.73 / 3.91 / 4.25V
Low voltage indicator
13 levels detect
1.88 / 2.00 / 2.13 / 2.28 / 2.46 / 2.68 / 2.81 / 3.06 / 3.21 /
3.56 / 3.73 / 3.91 / 4.25V
Watch Timer (WT)
3.91 ms / 0.25 s / 0.5 s / 1 s / 1 min interval at 32.768 kHz
Timer/counter
Basic interval timer (BIT) 8-bit x 1-ch.
Watchdog timer (WDT) 8-bit x 1-ch.
8-bit x 1-ch (T0), 16-bit x 5-ch (T1 / T2 / T3 / T4 / T5)
Communication
function
USART2
8-bit USART x 1-ch or 8-bit SPI x 1-ch
Receiver timer out (RTO)
0% error baud rate
USI0/1
USART + SPI + I2C
8-bit USART x 2-ch or 8-bit SPI x 2-ch or I2C x 2-ch
12-bit A/D converter
15 input channels
Oscillator type
4 MHz to 12 MHz crystal or ceramic for main clock
32.768 kHz Crystal for sub clock
LCD Driver
24 segments and 8 common terminals
Internal or external resistor bias
4 Internal Resistors Selectable
1/3, 1/4, 1/5, 1/6 and 1/8 duty selectable
Resistor Bias and 16-step contrast control
CRC
CRC16
Polynomial representations Normal : 0x8C81
f(x) = 1 + x7+ x10 + x11 + x15 + x16

1. Description A96G150 User's manual
16
Table 1. A96G150 Device Features and Peripheral Counts (continued)
Peripherals
Description
Internal RC oscillator
HSI 32MHz ±2.0% (TA=-40~ +85°C)
HSI 32MHz ±3.0% (TA=-40~ +105°C)
LSI 128kHz ±20% (TA= -40~ +85°C)
LSI 128kHz ±30% (TA= -40~ +105°C)
Operating voltage
and frequency
LVR (<1.8V) to 5.5V @ 32.768KHz with crystal
2.4V to 5.5V @ 4MHz to 12MHz with crystal
LVR (<1.8V) to 5.5V @ 0.5MHz to 16MHz with internal RC
Operating temperature
-40℃to +85℃, -40℃to +105℃
Package
Pb-free packages
44 LQFP 1010

A96G150 User's manual 1. Description
17
1.2 A96G150 block diagram
In this section, A96G150 device with peripherals are described in a block diagram.
Flash
64KB
ISP
In-system programming
Power control
Power on reset
Low voltage reset
Low voltage indicator
Power down mode
Clock generator
32MHz, Internal RC OSC
128kHz Internal RC OSC
12MHz, Crystal OSC
32.768kHz, Crystal OSC
Buzzer
1 channel, 8-bit
UART
3 channels, 8-bit
SPI
3 channels, 8-bit
I2C
2 channels, 8-bit
CORE
M8051
General purpose I/O
42 ports normal I/O
Watchdog timer
1 channel, 8-bit
128kHz, internal RC OSC
Basic interval timer
1 channel, 8-bit
Timer / Counter
1 channel, 8-bit
5 channels, 16-bit
ADC
15 Input channels, 12-bit
PWM
1-ch 8-bit (T0)
5-ch 16-bit (T1/T2/T3/T4/T5)
XRAM
2304B
IRAM
256B
EEPROM
2KB
LCD Driver
24 segments, 8 common
CRC
Polynomial representations
Normal : 0x8C81
Figure 1. A96G150 Block Diagram

2. Pinouts and pin description A96G150 User's manual
18
2Pinouts and pin description
In this chapter, A96G150 device pinouts and pin descriptions are introduced.
2.1 Pinouts
A96G150SN
44-LQFP
NOTE: The programmer (E-PGM+, E-Gang4/6) uses P1[3], P1[1] pin as DSCL, DSDA.
Figure 2. A96G150 44LQFP-1010 Pin Assignment

A96G150 User's manual 2. Pinouts and pin description
19
2.2 Pin description
Table 2. Normal Pin Description
Pin no.
Pin name
I/O(1)
Description
Remark
44
43
P00*
IOUS
Port 0 bit 0 Input/output
LCD_S16
O
LCD Segment Signal 16 Output
T3O
O
Timer 3 interval output
PWM3O
O
Timer 3 PWM output
44
P01*
IOUS
Port 0 bit 1 Input/output
LCD_S17
O
LCD Segment Signal 17 Output
T2O
O
Timer 2 interval output
PWM2O
O
Timer 2 PWM output
1
P02*
IOUS
Port 0 bit 2 Input/output
LCD_S18
O
LCD Segment Signal 18 Output
T1O
O
Timer 1 interval output
PWM1O
O
Timer 1 PWM output
2
P03*
IOUS
Port 0 bit 3 Input/output
T0O
O
Timer 0 interval output
PWM0O
O
Timer 0 PWM output
3
P04*
IOUS
Port 0 bit 4 Input/output
EINT0
I
External interrupt input ch-0
4
P05*
IOUS
Port 0 bit 5 Input/output
EINT1
I
External interrupt input ch-1
TXD2
O
USART2 data transmit
5
P06*
IOUS
Port 0 bit 6 Input/output
EINT2
I
External interrupt input ch-2
XOUT1
O
Main Oscillator Output ch-1
RXD2
I
USART2 data receive
6
P07*
IOUS
Port 0 bit 7 Input/output
EINT3
I
External interrupt input ch-3
XIN1
I
Main Oscillator Input ch-1
EC3
I
Timer 3(Event Capture) input

2. Pinouts and pin description A96G150 User's manual
20
Table 2. Normal Pin Description (continued)
Pin no.
Pin name
I/O(1)
Description
Remark
44
27
P10*
IOUS
Port 1 bit 0 Input/output
LCD_S0
O
LCD Segment Signal 0 Output
EINT44
I
External interrupt input ch-44
AN13
IA
ADC input ch-13
28
P11*
IOUS
Port 1 bit 1 Input/output
LCD_S1
O
LCD Segment Signal 1 Output
EINT45
I
External interrupt input ch-45
AN14
IA
ADC input ch-14
DSDA
IOU
OCD debugger data input/output
Pull-up
29
P12*
IOUS
Port 1 bit 2 Input/output
LCD_S2
O
LCD Segment Signal 2 Output
EINT46
I
External interrupt input ch-46
SCK1
IO
USART1 clock signal
30
P13*
IOUS
Port 1 bit 3 Input/output
LCD_S3
O
LCD Segment Signal 3 Output
EINT47
I
External interrupt input ch-47
TXD1
O
USART1 data transmit
SDA1
IO
I2C1 data signal
MOSI1
IO
USART1 SPI MOSI
DSCL
IOU
OCD debugger clock
Pull-up
31
P14*
IOUS
Port 1 bit 4 Input/output
LCD_S4
O
LCD Segment Signal 4 Output
EC1
I
Timer 1(Event Capture) input
RXD1
I
USART1 data receive
SCL1
IO
I2C1 clock signal
MISO1
IO
USART1 SPI MISO
32
P15*
IOUS
Port 1 bit 5 Input/output
LCD_S5
O
LCD Segment Signal 5 Output
SS1
IO
USART1 slave select signal
33
P16*
IOUS
Port 1 bit 6 Input/output
LCD_S6
O
LCD Segment Signal 6 Output
EC3
I
Timer 3(Event Capture) input
SS0
IO
USART0 slave select signal
34
P17*
IOUS
Port 1 bit 7 Input/output
LCD_S7
O
LCD Segment Signal 7 Output
SCK0
IO
USART0 clock signal