Abov A96G174 User manual

A96G174/A96S174
User’s Manual
16 MHz 8-bit A96G174 Microcontroller
8 Kbyte Flash memory, 12-bit ADC, 3 Timers, USART, I2C,
Window WDT
User’s Manual Version 1.11
Global Top Smart MCU Innovator, ABOV Semiconductor
www.abovsemi.com
Introduction
This user’s manual targets application developers who use A96G174/A96S174 for their specific needs.
It provides complete information of how to use A96G174/A96S174 device. Standard functions and
blocks including corresponding register information of A96G174/A96S174 are introduced in each
chapter, while instruction set is in Appendix.
A96G174/A96S174 is based on M8051 core, and provides standard features of 8051 such as 8-bit ALU,
PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data bus
and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
8Kbytes of FLASH, 256bytes of IRAM, and 256bytes of XRAM
Basic interval timer, watchdog timer, and 8/16-bit timer/counter
16-bit PPG output, 8-bit PWM output, 16-bit PWM output, USART, I2C, and 12-bit ADC
On-chip POR, LVR, LVI
On-chip oscillator and clock circuitry.
As a field proven best seller, A96G174/A96S174 introduces rich features such as excellent noise
immunity, code optimization, cost effectiveness, and so on.
Reference document
A96G174/A96S174 programming tools and manuals released by ABOV: They are available at
ABOV website, www.abovsemi.com.
SDK-51 User’s guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel’s 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentorwebsite: https://www.mentor.com/products/ip/peripheral/microcontroller/

Contents A96G174/A96S174 User’s manual
2
Contents
Introduction..............................................................................................................................................1
Reference document...............................................................................................................................1
1Description ...................................................................................................................................11
1.1 Device overview..................................................................................................................11
1.2 A96G174/A96S174 block diagram......................................................................................13
2Pinouts and pin description..........................................................................................................14
2.1 Pinouts................................................................................................................................14
2.2 Pin description.....................................................................................................................20
3Port structures..............................................................................................................................23
4Central Processing Unit(CPU) .....................................................................................................25
4.1 Architecture and registers...................................................................................................25
4.2 Addressing..........................................................................................................................27
4.3 Instruction set......................................................................................................................28
5Memory organization....................................................................................................................30
5.1 Program memory ................................................................................................................30
5.2 Data memory.......................................................................................................................31
5.3 External data memory.........................................................................................................34
5.4 SFR map.............................................................................................................................35
5.4.1 SFR map summary ................................................................................................35
5.4.2 SFR map ................................................................................................................37
5.4.3 Compiler compatible SFR ......................................................................................41
6I/O ports .......................................................................................................................................43
6.1 Port register.........................................................................................................................43
6.1.1 Data register (Px) ...................................................................................................43
6.1.2 Direction register (PxIO).........................................................................................43
6.1.3 Pull-up register selection register (PxPU) ..............................................................43
6.1.4 Open-drain Selection Register (PxOD)..................................................................43
6.1.5 De-bounce Enable Register (PxDB) ......................................................................43
6.1.6 Port Function Selection Register (PxFSR).............................................................43
6.1.7 Register Map..........................................................................................................44
6.2 P0 port.................................................................................................................................45
6.2.1 P0 port description .................................................................................................45
6.2.2 Register description for P0.....................................................................................45
6.3 P1 port.................................................................................................................................49
6.3.1 P1 port description .................................................................................................49
6.3.2 Register description for P1.....................................................................................49
6.4 P2 port.................................................................................................................................53
6.4.1 P2 port description .................................................................................................53
6.4.2 Register description for P2.....................................................................................53
7Interrupt controller........................................................................................................................55
7.1 External interrupt.................................................................................................................56
7.2 Pin Change Interrupt...........................................................................................................57
7.3 Block diagram .....................................................................................................................58
7.4 Interrupt vector table...........................................................................................................59
7.5 Interrupt sequence..............................................................................................................60
7.6 Effective timing after controlling interrupt bit.......................................................................61
7.7 Multi-interrupt......................................................................................................................62

A96G174/A96S174 User’s manual Contents
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7.8 Interrupt enable accept timing.............................................................................................63
7.9 Interrupt service routine address ........................................................................................63
7.10 Saving/restore general purpose registers...........................................................................63
7.11 Interrupt timing....................................................................................................................64
7.12 Interrupt register overview ..................................................................................................64
7.12.1 Interrupt Enable Register (IE, IE1, and IE2)...........................................................64
7.12.2 Interrupt Priority Register (IP and IP1)...................................................................64
7.12.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1)....................................65
7.12.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, and EIPOL1)...............65
7.12.5 Register map..........................................................................................................65
7.12.6 Interrupt register description...................................................................................66
8Clock generator............................................................................................................................69
8.1 Clock generator block diagram ...........................................................................................69
8.2 Register map.......................................................................................................................70
8.3 Register description ............................................................................................................70
9Basic interval timer.......................................................................................................................71
9.1 BIT block diagram...............................................................................................................71
9.2 BIT register map..................................................................................................................71
9.3 BIT register description.......................................................................................................72
10 Watchdog timer............................................................................................................................73
10.1 Setting window open period of watchdog timer ..................................................................74
10.2 WDT block diagram ............................................................................................................75
10.3 Register map.......................................................................................................................75
10.4 Register description ............................................................................................................76
11 Timer 0/1/2...................................................................................................................................78
11.1 Timer 0................................................................................................................................78
11.1.1 8-bit timer/counter mode ........................................................................................78
11.1.2 8-bit PWM mode.....................................................................................................80
11.1.3 8-bit capture mode .................................................................................................82
11.1.4 Timer 0 block diagram............................................................................................84
11.1.5 Register map..........................................................................................................84
11.1.6 Register description................................................................................................85
11.2 Timer 1................................................................................................................................87
11.2.1 16-bit timer/counter mode ......................................................................................87
11.2.2 16-bit capture mode ...............................................................................................89
11.2.3 16-bit PPG mode....................................................................................................91
11.2.4 16-bit Complementary PWM mode (Dead Time)...................................................93
11.2.5 16-bit timer 1 block diagram...................................................................................95
11.2.6 Register map..........................................................................................................95
11.2.7 Register description................................................................................................96
11.3 Timer 2................................................................................................................................99
11.3.1 16-bit timer/counter mode ......................................................................................99
11.3.2 16-bit capture mode .............................................................................................101
11.3.3 16-bit PPG mode..................................................................................................103
11.3.4 16-bit timer 2 block diagram.................................................................................105
11.3.5 Register map........................................................................................................105
11.3.6 Register description..............................................................................................106
12 12-bit ADC..................................................................................................................................108
12.1 Conversion timing .............................................................................................................108
12.2 Block diagram ...................................................................................................................109

Contents A96G174/A96S174 User’s manual
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12.3 ADC operation...................................................................................................................110
12.4 Register map.....................................................................................................................111
12.5 Register description ..........................................................................................................111
13 I2C..............................................................................................................................................114
13.1 Block diagram ...................................................................................................................114
13.2 Bit transfer.........................................................................................................................115
13.3 Start/ repeated start/ stop .................................................................................................115
13.4 Data transfer .....................................................................................................................116
13.5 Acknowledge.....................................................................................................................116
13.6 Synchronization/ Arbitration..............................................................................................117
13.7 Block operation .................................................................................................................119
13.7.1 I2C block initialization process.............................................................................119
13.7.2 I2C interrupt Service.............................................................................................120
13.7.3 Master transmitter ................................................................................................121
13.7.4 Slave Receiver .....................................................................................................123
13.8 Register map.....................................................................................................................124
13.9 I2C register description.....................................................................................................125
14 USART.......................................................................................................................................129
14.1 Block diagram ...................................................................................................................130
14.2 Clock generation...............................................................................................................131
14.3 External clock (XCK).........................................................................................................132
14.4 Synchronous mode operation...........................................................................................132
14.5 Data format .......................................................................................................................133
14.6 Parity bit............................................................................................................................134
14.7 USART transmitter............................................................................................................134
14.7.1 Sending Tx data ...................................................................................................134
14.7.2 Transmitter flag and interrupt...............................................................................134
14.7.3 Parity generator....................................................................................................135
14.7.4 Disabling transmitter.............................................................................................135
14.8 USART receiver................................................................................................................135
14.8.1 Receiving Rx data ................................................................................................135
14.8.2 Receiver flag and interrupt...................................................................................136
14.8.3 Parity checker.......................................................................................................137
14.8.4 Disabling receiver.................................................................................................137
14.8.5 Asynchronous data reception...............................................................................137
14.9 SPI mode ..........................................................................................................................139
14.9.1 SPI clock formats and timing................................................................................139
14.10 Receiver time out (RTO)...................................................................................................142
14.11 Register map.....................................................................................................................143
14.12 Register description ..........................................................................................................144
14.13 Baud rate settings (example)............................................................................................151
14.14 0% error baud rate............................................................................................................153
15 Power down operation ...............................................................................................................154
15.1 Peripheral operation in IDLE/ STOP mode.......................................................................154
15.2 IDLE mode........................................................................................................................155
15.3 STOP mode ......................................................................................................................155
15.4 Released operation of STOP mode..................................................................................156
15.5 Register map.....................................................................................................................158
15.6 Register description ..........................................................................................................158
16 Reset..........................................................................................................................................159

A96G174/A96S174 User’s manual Contents
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16.1 Reset block diagram .........................................................................................................159
16.2 Power on reset..................................................................................................................160
16.3 External RESETB input.....................................................................................................162
16.4 Low voltage reset process ................................................................................................164
16.5 LVI block diagram .............................................................................................................165
16.6 Register Map.....................................................................................................................166
16.7 Reset Operation Register Description ..............................................................................166
17 Memory programming................................................................................................................168
17.1 Flash control and status registers.....................................................................................168
17.1.1 Register map........................................................................................................168
17.1.2 Register description..............................................................................................169
17.2 Memory map.....................................................................................................................176
17.2.1 Flash memory map...............................................................................................176
17.3 Serial in-system program mode........................................................................................177
17.3.1 Flash operation.....................................................................................................177
17.4 Mode entrance method of ISP mode................................................................................182
17.4.1 Mode entrance method for ISP ............................................................................182
17.5 Security.............................................................................................................................183
17.6 Configure option................................................................................................................183
17.6.1 How to write the configure option in user program ..............................................184
18 Development tools .....................................................................................................................185
18.1 Compiler............................................................................................................................185
18.2 Core and debug tool information.......................................................................................185
18.2.1 Feature of 94/96/97 series core ...........................................................................186
18.2.2 OCD type of 94/96/97 series core........................................................................188
18.2.3 Interrupt priority of 94/96/97 series core ..............................................................189
18.2.4 Extended stack pointer of 94/96/97 series core...................................................190
18.3 OCD (On-chip debugger) emulator and debugger ...........................................................191
18.3.1 On-chip debug system .........................................................................................193
18.3.2 Entering debug mode...........................................................................................194
18.3.3 Two-wire communication protocol........................................................................195
18.4 Programmers ....................................................................................................................199
18.4.1 E-PGM+................................................................................................................199
18.4.2 OCD emulator ......................................................................................................199
18.4.3 Gang programmer................................................................................................200
18.5 Flash programming...........................................................................................................200
18.5.1 On-board programming........................................................................................200
18.6 Connection of transmission...............................................................................................201
18.7 Circuit design guide ..........................................................................................................202
Appendix .............................................................................................................................................204
Instruction table...........................................................................................................................204
Revision history...................................................................................................................................209

List of figures A96G174/A96S174 User’s manual
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List of figures
Figure 1. A96G174/A96S174 Block Diagram........................................................................................13
Figure 2. A96G174 20TSSOP Pin Assignment.....................................................................................14
Figure 3. A96S174 20TSSOP pin assignment......................................................................................15
Figure 4. A96G174 20SOP Pin Assignment .........................................................................................16
Figure 5. A96G174 20QFN Pin Assignment .........................................................................................17
Figure 6. A96S174 20QFN Pin Assignment ..........................................................................................18
Figure 7. A94G174 16SOPN Pin Assignment.......................................................................................19
Figure 8. General Purpose I/O Port ......................................................................................................23
Figure 9. External Interrupt I/O Port ......................................................................................................24
Figure 10. M8051EW Architecture ........................................................................................................25
Figure 11. Program Memory Map .........................................................................................................31
Figure 12. Data Memory Map ...............................................................................................................32
Figure 13. Lower 128bytes of RAM ......................................................................................................33
Figure 14. XDATA Memory Area ...........................................................................................................34
Figure 15. Interrupt Group Priority Level...............................................................................................56
Figure 16. External Interrupt Description ..............................................................................................56
Figure 17. Pin Change Interrupt............................................................................................................57
Figure 18. Interrupt Controller Block Diagram ......................................................................................58
Figure 19. Interrupt Sequence Flow......................................................................................................60
Figure 20. Effective Timing of Interrupt Enable Register ......................................................................61
Figure 21. Effective Timing of Interrupt Flag Register...........................................................................61
Figure 22. Effective Timing of Multi-Interrupt ........................................................................................62
Figure 23. Interrupt Response Timing Diagram ....................................................................................63
Figure 24. Correspondence between Vector Table Address and the Entry Address of ISR .................63
Figure 25. Saving/Restore Process Diagram and Sample Source.......................................................63
Figure 26. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction ...............................64
Figure 27. Clock Generator Block Diagram ..........................................................................................69
Figure 28. Basic Interval Timer Block Diagram.....................................................................................71
Figure 29. Watch Dog Timer Interrupt Timing Waveform......................................................................74
Figure 30. Watch Dog Timer Block Diagram.........................................................................................75
Figure 31. 8-bit Timer/Counter Mode for Timer 0..................................................................................79
Figure 32. 8-bit Timer/Counter 0 Example ............................................................................................79
Figure 33. 8-bit PWM Mode for Timer 0................................................................................................80
Figure 34. PWM Output Waveforms in PWM Mode for Timer 0 ...........................................................81
Figure 35. 8-bit Capture Mode for Timer 0............................................................................................82
Figure 36. Input Capture Mode Operation for Timer 0 ..........................................................................83
Figure 37. Express Timer Overflow in Capture Mode...........................................................................83
Figure 38. 8-bit Timer 0 Block Diagram ................................................................................................84
Figure 39. 16-bit Timer/Counter Mode of Timer 1 .................................................................................88
Figure 40. 16-bit Timer/Counter Mode Operation Example ..................................................................88
Figure 41. 16-bit Capture Mode of Timer 1 ...........................................................................................89
Figure 42. Input Capture Mode Operation for timer1 ............................................................................90
Figure 43. Express Timer Overflow in Capture Mode ...........................................................................90
Figure 44. 16-bit PPG Mode of Timer 1 ................................................................................................91
Figure 45. 16-bit PPG Mode Operation Example .................................................................................92
Figure 46. 16-bit Complementary PWM Mode for Timer1 ....................................................................93
Figure 47. 16-bit Complementary PWM Mode Timing chart for Timer 1 ..............................................94

A96G174/A96S174 User’s manual List of figures
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Figure 48. 16-bit Timer 1 Block Diagram ..............................................................................................95
Figure 49. 16-bit Timer/Counter Mode of Timer 2 ...............................................................................100
Figure 50. 16-bit Timer/Counter Mode Operation Example ................................................................100
Figure 51. 16-bit Capture Mode of Timer 2 .........................................................................................101
Figure 52. 16-bit Capture Mode Operation Example ..........................................................................102
Figure 53. Express Timer Overflow in Capture Mode .........................................................................102
Figure 54. 16-bit PPG Mode of Timer 2 ..............................................................................................103
Figure 55. 16-bit PPG Mode Operation Example ...............................................................................104
Figure 56. 16-bit Timer 2 Block Diagram ............................................................................................105
Figure 57. 12-bit ADC Block Diagram .................................................................................................109
Figure 58. A/D Analog Input Pin with a Capacitor ...............................................................................109
Figure 59. Control Registers and Align Bits ........................................................................................110
Figure 60. ADC Operation Flow Sequence ......................................................................................... 111
Figure 61. I2C Block Diagram..............................................................................................................114
Figure 62. Bit Transfer on the I2C-Bus ...............................................................................................115
Figure 63. START and STOP Condition..............................................................................................115
Figure 64. Data Transfer on the I2C-Bus ............................................................................................116
Figure 65. Acknowledge on the I2C-Bus.............................................................................................117
Figure 66. Clock Synchronization during Arbitration Procedure .........................................................118
Figure 67. Arbitration Procedure of Two Masters................................................................................118
Figure 68. USART Block Diagram ......................................................................................................130
Figure 69. Clock Generation Block Diagram.......................................................................................131
Figure 70. Synchronous Mode XCK Timing ........................................................................................132
Figure 71. A Frame Format .................................................................................................................133
Figure 72. Start Bit Sampling ..............................................................................................................137
Figure 73. Sampling of Data and Parity Bit .........................................................................................138
Figure 74. Stop Bit Sampling and Next Start Bit Sampling.................................................................138
Figure 75. SPI Clock Formats when UCPHA = 0................................................................................140
Figure 76. SPI Clock Formats when UCPHA = 1................................................................................141
Figure 77. Example for RTO in USART ..............................................................................................142
Figure 78. 0% Error Baud Rate Block Diagram ..................................................................................153
Figure 79. IDLE Mode Release Timing by an External Interrupt ........................................................155
Figure 80. STOP Mode Release Timing by External Interrupt............................................................156
Figure 81. STOP Mode Release Flow ................................................................................................157
Figure 82. Reset Block Diagram .........................................................................................................159
Figure 83. Fast VDD Rising Time .......................................................................................................160
Figure 84. Internal RESET Release Timing On Power-Up .................................................................160
Figure 85. Configuration Timing when Power-on................................................................................161
Figure 86. Boot Process Waveform ....................................................................................................161
Figure 87. Timing Diagram after RESET ............................................................................................163
Figure 88. Oscillator generating waveform example ..........................................................................163
Figure 89. Block Diagram of LVR........................................................................................................164
Figure 90. Internal Reset at Power Fail Situation ...............................................................................164
Figure 91. Configuration Timing When LVR RESET...........................................................................165
Figure 92. LVI Block Diagram .............................................................................................................165
Figure 93. Read Device Internal Checksum (Full Size) ......................................................................173
Figure 94. Read Device Internal Checksum (User Define Size).........................................................174
Figure 95. Flash Memory Map ............................................................................................................176
Figure 96. Address Configuration of Flash Memory ...........................................................................176
Figure 97. The Sequence of Page Program and Erase of Flash Memory..........................................177

List of figures A96G174/A96S174 User’s manual
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Figure 98. The Sequence of Bulk Erase of Flash Memory .................................................................178
Figure 99. ISP Mode ...........................................................................................................................182
Figure 100. Configuration of the Extended Stack Pointer...................................................................190
Figure 101. OCD 1 and OCD 2 Connector Pin Diagram ....................................................................192
Figure 102. Debugger (OCD1/OCD2) and Pinouts ............................................................................193
Figure 103. On-Chip Debugging System in Block Diagram................................................................194
Figure 104. Timing Diagram of Debug Mode Entry ............................................................................194
Figure 105. 10-bit Transmission Packet..............................................................................................196
Figure 106. Data Transfer on OCD .....................................................................................................196
Figure 107. Bit Transfer on Serial Bus ................................................................................................197
Figure 108. Start and Stop Condition..................................................................................................197
Figure 109. Acknowledge on Serial Bus .............................................................................................198
Figure 110. Clock Synchronization during Wait Procedure.................................................................198
Figure 111. E-PGM+ (Single Writer) and Pinouts ...............................................................................199
Figure 112. E-Gang4 and E-Gang6 (for Mass Production).................................................................200
Figure 113. Connection of Transmission.............................................................................................201
Figure 114. PCB Design Guide for On-Board Programming ..............................................................203

A96G174/A96S174 User’s manual List of tables
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List of tables
Table 1. A96G174/A96S174 Device Features and Peripheral Counts .................................................11
Table 1. A96G174/A96S174 Device Features and Peripheral Counts (continued) ..............................12
Table 2. Normal Pin Description............................................................................................................20
Table 2. Normal Pin Description (continued).........................................................................................21
Table 2. Normal Pin Description (continued).........................................................................................22
Table 3. SFR Map Summary .................................................................................................................35
Table 4. XSFR Map Summary ..............................................................................................................36
Table 5. SFR Map .................................................................................................................................37
Table 5. SFR Map (continued) ..............................................................................................................38
Table 5. SFR Map (continued) ..............................................................................................................39
Table 6. XSFR Map ...............................................................................................................................40
Table 7. Port Register Map....................................................................................................................44
Table 8. Interrupt Vector Address Table ................................................................................................59
Table 9. Interrupt Register Map.............................................................................................................65
Table 10. Clock Generator Register Map..............................................................................................70
Table 11. Basic Interval Timer Register Map.........................................................................................71
Table 12. Watch Dog Timer Register Map ............................................................................................75
Table 13. Watchdog Timer Register Map ..............................................................................................75
Table 14. Timer 0 Operating Mode........................................................................................................78
Table 15. Timer 0 Register Map ............................................................................................................84
Table 16. TIMER 1 Operating Modes....................................................................................................87
Table 17. TIMER 1 Register Map ..........................................................................................................95
Table 18. TIMER 2 Operating Modes....................................................................................................99
Table 19. TIMER 2 Register Map ........................................................................................................105
Table 20. ADC Register Map............................................................................................................... 111
Table 21. Register Map .......................................................................................................................124
Table 22. Equations for Calculating Baud Rate Register Setting........................................................131
Table 23. CPOL Functionality..............................................................................................................139
Table 24. Example Condition of RTO..................................................................................................142
Table 25. USART Register Map ..........................................................................................................143
Table 26. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies .......................151
Table 27. Peripheral Operation Status during Power-down Mode......................................................154
Table 28. Power-down Operation Register Map .................................................................................158
Table 29. Hardware Setting Values in Reset State .............................................................................159
Table 30. Boot Process Description ....................................................................................................162
Table 31. Reset Operation Register Map............................................................................................166
Table 32. Flash Control and Status Register Map ..............................................................................168
Table 33. Program and Erase Time ....................................................................................................175
Table 34. Operation Mode...................................................................................................................182
Table 35. Mode entrance method for ISP ...........................................................................................182
Table 36. Security Policy using Lock Bits............................................................................................183
Table 37. Information of Core and Debug Emulation Interfaces .........................................................185
Table 38. Core and Debug Interface by Series ...................................................................................186
Table 39. Feature Comparison Chart By Series and Cores................................................................186
Table 40. OCD Type of Each Series ...................................................................................................188
Table 41. Comparison of OCD 1 and OCD 2 ......................................................................................188
Table 42. Interrupt Priorities in Groups and Levels .............................................................................189

List of tables A96G174/A96S174 User’s manual
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Table 43. Debug Feature by Series ....................................................................................................191
Table 44. OCD 1 and OCD 2 Pin Description .....................................................................................192
Table 45. OCD Features .....................................................................................................................193
Table 46. Pins for Flash Programming................................................................................................200
Table 47. Instruction Table ..................................................................................................................204
Table 47. Instruction Table (continued) ...............................................................................................205
Table 47. Instruction Table (continued) ...............................................................................................206
Table 47. Instruction Table (continued) ...............................................................................................207
Table 47. Instruction Table (continued) ...............................................................................................208

A96G174/A96S174 User’s manual 1. Description
11
1Description
A96G174/A96S174 is an advanced CMOS 8-bit microcontroller with 8Kbytes of FLASH. This is a
powerful microcontroller which provides a highly flexible and cost effective solution to many embedded
control applications.
1.1 Device overview
In this section, features of A96G174/A96S174 and peripheral counts are introduced.
Table 1. A96G174/A96S174 Device Features and Peripheral Counts
Peripherals
Description
Core
CPU
8-bit CISC core (M8051, 2 clocks per cycle)
Interrupt
Up to 14 peripheral interrupts supported.
EINT0 to 2, PCI (4)
Timer (0/1/2) (3)
WDT (1)
BIT (1)
USART Rx/Tx (2)
I2C (1)
ADC (1)
LVI (1)
Memory
ROM (FLASH)
capacity
8Kbytes FLASH with self-read and write capability
In-system programming (ISP)
Endurance: 30,000times
IRAM
256Bytes
XRAM
256Bytes
Programmable pulse generation
Pulse generation (by T1/T2)
8-bit PWM (by T0)
16-bit Complementary PWM (by T1, Dead time)
Minimum instruction execution
time
125ns (@ 16MHz main clock)
61us (@ 32.768kHz sub clock)
Power down mode
STOP mode
IDLE mode
General Purpose I/O (GPIO)
Normal I/O: 18ports

1. Description A96G174/A96S174 User’s manual
12
Table 1. A96G174/A96S174 Device Features and Peripheral Counts (continued)
Peripherals
Description
Reset
Power on
reset
Reset release level: 1.32V
Low voltage
reset
5 levels detect
1.61/1.77/2.13/2.46/3.56V
Low voltage indicator
3 levels detect
1.77/2.13/2.46/3.56V
Timer/counter
Basic interval timer (BIT) 8-bit x 1-ch.
Window Watch Dog Timer (WWDT) 8-bit x 1-ch.
8-bit x 1-ch (T0), 16-bit x 2-ch (T1/T2)
Communication
function
USART
8-bit USART x 1-ch or 8-bit SPI x 1-ch
Receiver timer out (RTO)
0% error baud rate
I2C
Compatible with I2C bus standard
Up to 400kHz
12-bit A/D converter
15 input channels
Internal RC oscillator
HSIRC 32MHz ±1.5% (TA= 0~ +50°C)
HSIRC 32MHz ±2.0% (TA=-10~ +70°C)
HSIRC 32MHz ±2.5% (TA=-40~ +85°C)
HSIRC 32MHz ±5.0% (TA=-40~ +105°C)
LSIRC 128kHz ±20% (TA= -40~ +85°C)
LSIRC 128kHz ±30% (TA= -40~ +105°C)
Operating voltage and
frequency
1.8V to 5.5V @ 32.768kHz with crystal
1.8V to 5.5V @ 0.5MHz to 16.0MHz with internal RC
Operating temperature
-40℃to +85, -40℃to 105℃
Package
Pb-free packages
20 SOP / TSSOP / QFN
16 SOPN

A96G174/A96S174 User’s manual 1. Description
13
1.2 A96G174/A96S174 block diagram
In this section, A96G174/A96S174 device with peripherals is described in a block diagram.
XRAM
256B
IRAM
256B
Flash
8KB
ISP
In-system programming
Power control
Power on reset
Low voltage reset
Low voltage indicator
Power down mode
Clock generator
32MHz, Internal RC OSC
128kHz Internal RC OSC
USART
1 channels, 8-bit
I2C
1 channels, 8-bit
CORE
M8051
General purpose I/O
18 ports normal I/O
Watchdog timer
1 channel, 8-bit
128kHz, internal RC OSC
Basic interval timer
1 channel, 8-bit
Timer / Counter
1 channel, 8-bit
2 channels, 16-bit
ADC
15 Input channels, 12-bit
PWM
1-ch 8-bit (T0)
1-ch 16-bit (T2)
PPG (T1)
Figure 1. A96G174/A96S174 Block Diagram

2. Pinouts and pin description A96G174/A96S174 User’s manual
14
2Pinouts and pin description
Pinouts and pin descriptions of A96G174/A96S174 device are introduce in the following sections.
2.1 Pinouts
A96G174FR
(20TSSOP)
1
4
3
2
VDD
6
5
VSS
7
10
9
8
20
17
18
19
15
16
14
11
12
13
SS/DSDA/EC0/AN3/P00
SCL/RESETB/EINT0/P02
SDA/DSCL/AN4/P01
T0O/PWM0O/AN5/P03
T2O/PWM2O/AN6/P04
SCK/AN7/P05
MOSI(TXD)/(PWM1OB)/AN8/P06
MISO(RXD)/(T1O)/(PWM1O)/AN9/P07
AN10/P10
P21/AN2
P20/AN1/T1O/PWM1O
P17/AN0/PWM1OB
P16/AN14
P15/AN13/EINT2/RXD(MISO)
P14/AN12/TXD(MOSI)
P13/AN11/EINT1/EC1/XCK
P12/(T1O)/(PWM1O)/(SS)
P11/(T2O)/(PWM2O)/(SDA)
NOTES:
1. Programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P22 pins should be selected as a push-pull output or an input with pull-up resistor by software control
when the 20-pin package is used.
Figure 2. A96G174 20TSSOP Pin Assignment

A96G174/A96S174 User’s manual 2. Pinouts and pin description
15
20
17
18
19
15
16
14
11
12
13
1
4
3
2
6
5
7
10
9
8
A96S174FR
(20TSSOP)
VDD
VSS
SS/DSDA/EC0/AN3/P00 P01/DSCL/AN4/SDA
P03/AN5/T0O/PWM0O
P04/AN6/T2O/PWM2O
P05/AN7/SCK
P06/AN8/(PWM1OB)/MOSI(TXD)
P07/AN9/(T1O)/(PWM1O)MISO(RXD)
P10/AN10
T1O/PWM1O/AN1/P20
PWM1OB/AN0/P17
RESETB/AN14/P16
RXD(MISO)/EINT2/AN13/P15
TXD(MOSI)/AN12/P14
XCK/EC1/EINT1/AN11/P13 P12/(T0O)/(PWM0O)/(SS)
P11/(T2O)/(PWM2O)/(SDA)
P22
P02/EITN0/SCL
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P21 pins should be selected as a push-pull output or an input with pull-up resistor by software control
when the 20-pin package is used.
3.
Figure 3. A96S174 20TSSOP pin assignment

2. Pinouts and pin description A96G174/A96S174 User’s manual
16
A96G174FD
(20SOP)
1
4
3
2
VDD
6
5
VSS
7
10
9
8
20
17
18
19
15
16
14
11
12
13
SS/DSDA/EC0/AN3/P00
SCL/RESETB/EINT0/P02
SDA/DSCL/AN4/P01
T0O/PWM0O/AN5/P03
T2O/PWM2O/AN6/P04
SCK/AN7/P05
MOSI(TXD)/(PWM1OB)/AN8/P06
MISO(RXD)/(T1O)/(PWM1O)/AN9/P07
AN10/P10
P21/AN2
P20/AN1/T1O/PWM1O
P17/AN0/PWM1OB
P16/AN14
P15/AN13/EINT2/RXD(MISO)
P14/AN12/TXD(MOSI)
P13/AN11/EINT1/EC1/XCK
P12/(T1O)/(PWM1O)/(SS)
P11/(T2O)/(PWM2O)/(SDA)
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P22 pins should be selected as a push-pull output or an input with pull-up resistor by software control
when the 20-pin package is used.
3.
Figure 4. A96G174 20SOP Pin Assignment

A96G174/A96S174 User’s manual 2. Pinouts and pin description
17
A96G174FU
(20QFN)
20
17
18
19
16
6
9
8
7
10
P17/AN0/PWM1OB
15
12
13
14
11
P20/AN1/T1O/PWM1O
P15/AN13/EINT2/RXD(MISO)
P16/AN14
P14/AN12/TXD(MOSI)
1
4
3
2
5
T0O/PWM0O/AN5/P03
RESETB/SCL/EINT0/P02
SCK/AN7/P05
T2O/PWM2O/AN6/P04
MOSI(TXD)/(PWM1OB)/AN8/P06
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P22 pins should be selected as a push-pull output or an input with pull-up resistor by software control
when the 20-pin package is used.
3.
Figure 5. A96G174 20QFN Pin Assignment

2. Pinouts and pin description A96G174/A96S174 User’s manual
18
A96S174FU
(20QFN)
P15/AN13/EINT2/RXD(MISO)
20
17
18
19
16
6
9
8
7
10
VDD
P12/(T2O)/(PWM2O)/(SS)
P11/(T2O)/(PWM2O)/(SDA)
SS/DSDA/EC0/AN3/P00
SDA/DSCL/AN4/P01
SCL/EINT0/P02
T0O/PWM0O/AN5/P03
P07/AN9/T1O/PWM1O/MISO(RXD)
15
12
13
14
11
P10/AN10
P06/AN8/(PWM1OB)/MOSI(TXD)
P04/AN6/T2O/PWM2O
1
4
3
2
5
PWM1OB/AN0/P17
RESETB/AN14/P16
VSS
T1O/PWM1O/AN1/P20
P22
P14/AN12/TXD(MOSI)
P05/AN7/SCK
P13/AN11/EINT1/EC1/XCK
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P21 pins should be selected as a push-pull output or an input with pull-up resistor by software control
when the 20-pin package is used.
3.
Figure 6. A96S174 20QFN Pin Assignment

A96G174/A96S174 User’s manual 2. Pinouts and pin description
19
A96G174AE
(16SOPN)
1
4
3
2
VDD
6
5
VSS
7
8
16
13
14
15
11
12
10
9
SS/DSDA/EC0/AN3/P00
SCL/RESETB/EINT0/P02
SDA/DSCL/AN4/P01
T0O/PWM0O/AN5/P03
T2O/PWM2O/AN6/P04
SCK/AN7/P05
MOSI(TXD)/(PWM1OB)/AN8/P06
P21/AN2
P20/AN1/T1O/PWM1O
P17/AN0/PWM1OB
P16/AN14
P15/AN13/EINT2/RXD(MISO)
P14/AN12/TXD(MOSI)
P13/AN11/EINT1/EC1/XCK
NOTE: The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA
Figure 7. A94G174 16SOPN Pin Assignment

2. Pinouts and pin description A96G174/A96S174 User’s manual
20
2.2 Pin description
Table 2. Normal Pin Description
Pin no.
PIN Name
I/O(2)
Description
Remark
20TSSOP
20QFN
16SOPN
2(10) (1)
19(7)(1)
2
P00*
IOUS
Port 0 bit 0 Input/output
AN3
IA
ADC input ch-3
EC0
I
Timer 0(Event Capture) input
DSDA
IO
OCD debugger data input/output
Pull-up
SS
IO
USART slave select signal
3(11)
20(8)
3
P01*
IOUS
Port 0 bit 1 Input/output
AN4
IA
ADC input ch-4
DSCL
I
OCD debugger clock
Pull-up
SDA
IO
I2C data signal
4(12)
1(9)
4
P02*
IOUS
Port 0 bit 2 Input/output
RESETB
IU
A96G174 only, Reset pin
Pull-up
EINT0
I
External interrupt input ch-0
SCL
IO
I2C clock signal
5(13)
2(10)
5
P03*
IOUS
Port 0 bit 3 Input/output
AN5
IA
ADC input ch-5
T0O
O
Timer 0 interval output
PWM0O
O
Timer 0 PWM output
6(14)
3(11)
6
P04*
IOUS
Port 0 bit 4 Input/output
AN6
IA
ADC input ch-6
T2O
O
Timer 2 interval output
PWM2O
O
Timer 2 PWM output
7(15)
4(12)
7
P05*
IOUS
Port 0 bit 5 Input/output
AN7
IA
ADC input ch-7
SCK
IO
USART external clock input/output
8(16)
5(13)
8
P06*
IOUS
Port 0 bit 6 Input/output
AN8
IA
ADC input ch-8
MOSI
(TXD)
IO
USART data transmit /SPI MOSI
PWM1OB
O
Timer 1 PWM complementary output
9(17)
6(14)
-
P07*
IOUS
Port 0 bit 7 Input/output
AN9
IA
ADC input ch-9
MISO
(RXD)
IO
USART data receive /SPI MISO