ARM DSTREAM DS-5 User manual

ARM® DS-5
Version 5.27
ARM DSTREAM System and Interface Design Reference
Guide
Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved.
ARM 100956_0527_00_en

ARM® DS-5
ARM® DSTREAM System and Interface Design Reference Guide
Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved.
Release Information
Document History
Issue Date Confidentiality Change
A May 2010 Non-Confidential First release
B November 2010 Non-Confidential Update for DS-5 version 5.3
C 30 April 2011 Non-Confidential Update for DSTREAM and RVI v4.2.1
D 29 July 2011 Non-Confidential Update for DS-5 version 5.6
E 30 September 2011 Non-Confidential Update for DSTREAM and RVI v4.4, and DS-5 version 5.7
F 29 February 2012 Non-Confidential Update for DS-5 version 5.9
G 29 July 2012 Non-Confidential Update for DS-5 version 5.11
H 12 October 2012 Non-Confidential Update for DS-5 version 5.12
I 20 March 2015 Non-Confidential Update for DS-5 version 5.21
J 15 July 2015 Non-Confidential Update for DS-5 version 5.22
K 15 March 2016 Non-Confidential Update for DS-5 version 5.24
0527-00 07 April 2017 Non-Confidential Document numbering scheme has changed. Update for DS-5
version 5.27.
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LES-PRE-20349
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in
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Product Status
The information in this document is Final, that is for a developed product.
Web Address
http://www.arm.com
Conformance Notices
This section contains conformance notices.
Federal Communications Commission Notice
This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).
Class A
Important: This is a Class A device. In residential areas, this device may cause radio interference. The user should take the
necessary precautions, if appropriate.
CE Declaration of Conformity
The system should be powered down when not in use.
It is recommended that ESD precautions be taken when handling DSTREAM equipment.
The DSTREAM modules generate, use, and can radiate radio frequency energy and may cause harmful interference to radio
communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful
interference to radio reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct
the interference by one or more of the following measures:
• Ensure attached cables do not lie across the target board.
• Increase the distance between the equipment and the receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult ARM Support for help.
Note
It is recommended that wherever possible shielded interface cables be used.
ARM® DS-5
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Contents
ARM® DS-5 ARM DSTREAM System and Interface
Design Reference Guide
Preface
About this book ..................................................... ..................................................... 10
Chapter 1 ARM DSTREAM System Design Guidelines
1.1 About adaptive clocking to synchronize the JTAG port ..................... ..................... 1-13
1.2 Reset signals ..................................................... ..................................................... 1-16
1.3 ASIC guidelines ................................................... ................................................... 1-18
1.4 PCB guidelines ........................................................................................................ 1-20
Chapter 2 ARM DSTREAM Target Interface Connections
2.1 Signal descriptions .................................................................................................. 2-23
2.2 Target connectors supported by DSTREAM ............................................................ 2-28
2.3 The Mictor 38 connector pinouts and interface signals ..................... ..................... 2-29
2.4 The ARM JTAG 20 connector pinouts and interface signals ................. ................. 2-33
2.5 The TI JTAG 14 connector pinouts and interface signals ........................................ 2-36
2.6 The ARM JTAG 14 connector pinouts and interface signals ................. ................. 2-38
2.7 The CoreSight 10 connector pinouts and interface signals .................. .................. 2-40
2.8 The CoreSight 20 connector pinouts and interface signals .................. .................. 2-42
2.9 The MIPI 34 connector pinouts and interface signals .............................................. 2-45
2.10 I/O diagrams for the DSTREAM probe connectors ........................ ........................ 2-49
2.11 Voltage domains of the DSTREAM probe ............................... ............................... 2-51
2.12 Series termination .................................................................................................... 2-52
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Chapter 3 ARM DSTREAM User I/O Connections
3.1 About the User I/O connector .................................................................................. 3-54
3.2 User I/O pin connections ............................................ ............................................ 3-55
Chapter 4 Target Board Design for Tracing with ARM DSTREAM
4.1 Overview of high-speed design ....................................... ....................................... 4-57
4.2 PCB track impedance .............................................................................................. 4-58
4.3 Signal requirements ................................................ ................................................ 4-59
4.4 Probe modeling ................................................... ................................................... 4-60
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List of Figures
ARM® DS-5 ARM DSTREAM System and Interface
Design Reference Guide
Figure 1-1 Basic JTAG port synchronizer ............................................................................................... 1-14
Figure 1-2 Timing diagram for the Basic JTAG synchronizer .................................................................. 1-14
Figure 1-3 JTAG port synchronizer for single rising-edge D-type ASIC design rules ............................. 1-14
Figure 1-4 Timing diagram for the D-type JTAG synchronizer ................................................................ 1-15
Figure 1-5 Example reset circuit logic ..................................................................................................... 1-17
Figure 1-6 TAP Controllers serially chained within an ASIC ................................................................... 1-18
Figure 1-7 Typical PCB connections ....................................................................................................... 1-20
Figure 1-8 Target interface logic levels ................................................................................................... 1-21
Figure 2-1 JTAG port timing diagram ...................................................................................................... 2-24
Figure 2-2 Typical SWD connections ...................................................................................................... 2-25
Figure 2-3 SWD timing diagrams ............................................................................................................ 2-26
Figure 2-4 Clock waveforms ................................................................................................................... 2-27
Figure 2-5 Mictor 38 connector pinout .................................................................................................... 2-29
Figure 2-6 ARM JTAG 20 connector pinout ............................................................................................ 2-33
Figure 2-7 TI JTAG 14 connector pinout ................................................................................................. 2-36
Figure 2-8 ARM JTAG 14 connector pinout ............................................................................................ 2-38
Figure 2-9 CoreSight 10 connector pinout .............................................................................................. 2-40
Figure 2-10 CoreSight 20 connector pinout .............................................................................................. 2-42
Figure 2-11 MIPI 34 connector pinout ....................................................................................................... 2-45
Figure 2-12 Input ....................................................................................................................................... 2-49
Figure 2-13 Output .................................................................................................................................... 2-49
Figure 2-14 Input/Output ........................................................................................................................... 2-49
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Figure 2-15 Reset output .......................................................................................................................... 2-49
Figure 2-16 Reset output with feedback ................................................................................................... 2-49
Figure 2-17 VTRef input ............................................................................................................................ 2-50
Figure 2-18 VTRef input (decoupled) ........................................................................................................ 2-50
Figure 2-19 Ground ................................................................................................................................... 2-50
Figure 2-20 AC Ground ............................................................................................................................. 2-50
Figure 3-1 User I/O pin connections ....................................................................................................... 3-54
Figure 4-1 Track impedance ................................................................................................................... 4-58
Figure 4-2 Data waveforms ..................................................................................................................... 4-59
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List of Tables
ARM® DS-5 ARM DSTREAM System and Interface
Design Reference Guide
Table 2-1 DSTREAM JTAG Characteristics .......................................................................................... 2-24
Table 2-2 SWD timing requirements ...................................................................................................... 2-26
Table 2-3 TRACECLK frequencies ........................................................................................................ 2-27
Table 2-4 Mictor 38 interface pinout table ............................................................................................. 2-30
Table 2-5 Mictor 38 signals .................................................................................................................... 2-31
Table 2-6 ARM JTAG 20 interface pinout table ..................................................................................... 2-33
Table 2-7 ARM JTAG 20 signals ............................................................................................................ 2-34
Table 2-8 TI JTAG 14 interface pinout table .......................................................................................... 2-36
Table 2-9 TI JTAG 14 signals ................................................................................................................ 2-37
Table 2-10 ARM JTAG 14 interface pinout table ..................................................................................... 2-38
Table 2-11 ARM JTAG 14 signals ............................................................................................................ 2-39
Table 2-12 CoreSight 10 interface pinout table ....................................................................................... 2-40
Table 2-13 CoreSight 10 signals ............................................................................................................. 2-41
Table 2-14 CoreSight 20 interface pinout table ....................................................................................... 2-43
Table 2-15 CoreSight 20 signals ............................................................................................................. 2-43
Table 2-16 MIPI 34 interface pinout table ................................................................................................ 2-46
Table 2-17 MIPI 34 signals ...................................................................................................................... 2-47
Table 2-18 Typical series terminating resistor values .............................................................................. 2-52
Table 3-1 User I/O pin connections ....................................................................................................... 3-55
Table 4-1 Data setup and hold .............................................................................................................. 4-59
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Preface
This preface introduces the ARM® DS-5 ARM DSTREAM System and Interface Design Reference Guide.
It contains the following:
•About this book on page 10.
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About this book
DSTREAM System and Interface Design Reference Guide describes the DSTREAM debug and trace
unit, with details about designing ARM® architecture-based ASICs and PCBs. This document is written
for those using DSTREAM with DS-5 Debugger, and is available as a PDF.
Using this book
This book is organized into the following chapters:
Chapter 1 ARM DSTREAM System Design Guidelines
This contains information on developing ARM® architecture-based devices and Printed Circuit
Boards (PCBs) that can be debugged using ARM DSTREAM™.
Chapter 2 ARM DSTREAM Target Interface Connections
This describes the interface connections on the DSTREAM unit.
Chapter 3 ARM DSTREAM User I/O Connections
This describes the additional input and output connections provided in DSTREAM.
Chapter 4 Target Board Design for Tracing with ARM DSTREAM
This describes the properties of a target board that can be connected to the DSTREAM trace
feature.
Glossary
The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those
terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning
differs from the generally accepted meaning.
See the ARM Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the
ARM Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
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Preface
About this book
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Preface
About this book
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Chapter 1
ARM DSTREAM System Design Guidelines
This contains information on developing ARM® architecture-based devices and Printed Circuit Boards
(PCBs) that can be debugged using ARM DSTREAM™.
It contains the following sections:
•1.1 About adaptive clocking to synchronize the JTAG port on page 1-13.
•1.2 Reset signals on page 1-16.
•1.3 ASIC guidelines on page 1-18.
•1.4 PCB guidelines on page 1-20.
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1.1 About adaptive clocking to synchronize the JTAG port
ARM architecture-based devices that use only hard macrocells, such as ARM7TDMI® and ARM920T,
use the standard five-wire JTAG interface. However, some target systems require that JTAG events are
synchronized to a clock in the system. The adaptive clocking feature of DSTREAM addresses this
requirement.
The standard five-wire JTAG interface comprises the TCK, TMS, TDI, TDO, and nTRST signals. To
ensure a valid JTAG CLK setting, systems that require the JTAG events to be synchronized to a clock in
the system often support an extra signal (RTCK) at the JTAG port:
• An Application-Specific Integrated Circuit (ASIC) with single rising-edge D-type design rules, such
as one based on an ARM7TDMI-S™ processor.
• A system where scan chains external to the ARM macrocell must meet single rising-edge D-type
design rules.
When adaptive clocking is enabled, DSTREAM issues a TCK signal and waits for the RTCK signal to
come back. DSTREAM does not progress to the next TCK until RTCK is received.
Note
• Adaptive clocking is automatically configured in ARM DS-5™ as required by the target.
• If you use the adaptive clocking feature, transmission delays, gate delays, and synchronization
requirements result in a lower maximum clock frequency than with non-adaptive clocking. Do not
use adaptive clocking unless it is required by the hardware design.
• If, when autoconfiguring a target, the DSTREAM unit receives pulses on RTCK in response to TCK
it assumes that adaptive clocking is required, and enables adaptive clocking in the target
configuration. If the hardware does not require adaptive clocking, the target is driven slower than it
could be. You can disable adaptive clocking using controls on the JTAG settings dialog box.
• If adaptive clocking is used, DSTREAM cannot detect the clock speed, and therefore cannot scale its
internal timeouts. If the target clock frequency is very slow, a JTAG timeout might occur. This leaves
the JTAG in an unknown state, and DSTREAM cannot operate correctly without reconnecting to the
processor. JTAG timeouts are enabled by default. You can disable JTAG timeouts by deselecting the
option JTAG Timeouts Enabled in the installed Debug Hardware Config utility provided with the
DSTREAM unit.
You can use adaptive clocking as an interface to targets with slow or widely varying clock frequency,
such as battery-powered equipment that varies its clock speed according to processing demand. In this
system, TCK might be hundreds of times faster than the system clock, and the debugger loses
synchronization with the target system. Adaptive clocking ensures that the JTAG port speed
automatically adapts to slow system speed.
The following figure shows a circuit for a basic JTAG port synchronizer.
1 ARM DSTREAM System Design Guidelines
1.1 About adaptive clocking to synchronize the JTAG port
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nTRST
CLK
TCK
TDO
TMO
TDI
ASIC
nCLR
DQDQ
nCLR
RTCK
TDO
TCK
nTRST
CLK
TMS
TDI
Figure 1-1 Basic JTAG port synchronizer
The following figure shows a partial timing diagram for the basic JTAG synchronizer. The delay can be
reduced by clocking the flip-flops from opposite edges of the system clock, because the second flip-flop
only provides better immunity to metastability problems. Even a single flip-flop synchronizer never
completely misses TCK events, because RTCK is part of a feedback loop controlling TCK.
CLK
TCK
RTCK
Figure 1-2 Timing diagram for the Basic JTAG synchronizer
It is common for an ASIC design flow and its design rules to impose a restriction that all flip-flops in a
design are clocked by one edge of a single clock. To interface this to a JTAG port that is completely
asynchronous to the system, it is necessary to convert the JTAG TCK events into clock enables for this
single clock, and to ensure that the JTAG port cannot overrun this synchronization delay.
The following figure shows one possible implementation of this circuit.
CKEN
IN
nRESET
TMS
CKEN TAP Ctrl
State
Machine
OUT
Scan
Chain
CKEN
TCKFallingEn
TCKRisingEn
Shift En
DQ
nCLR
D Q
nCLR
D Q
nCLR
D Q
TDO
TMS
CLK
nTRST
TCK
RTCK
TDI
Figure 1-3 JTAG port synchronizer for single rising-edge D-type ASIC design rules
1 ARM DSTREAM System Design Guidelines
1.1 About adaptive clocking to synchronize the JTAG port
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The following figure shows a corresponding partial timing diagram, and how TCKFallingEn and
TCKRisingEn are each active for exactly one period of CLK. It also shows how these enable signals
gate the RTCK and TDO signals so that they only change state at the edges of TCK.
CLK
TCKRisingEn
TCK
TCKFallingEn
RTCK
TAPC
State
TDO
Figure 1-4 Timing diagram for the D-type JTAG synchronizer
Related references
1.2 Reset signals on page 1-16.
1 ARM DSTREAM System Design Guidelines
1.1 About adaptive clocking to synchronize the JTAG port
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1.2 Reset signals
There are two types of reset signals available on ARM devices. DSTREAM expects these signals to be
wired in a certain way.
This section contains the following subsections:
•1.2.1 ARM reset signals on page 1-16.
•1.2.2 DSTREAM reset signals on page 1-16.
•1.2.3 Example reset circuits on page 1-17.
1.2.1 ARM reset signals
All ARM processors have a main processor reset that might be called nRESET, BnRES, or HRESET.
This is asserted by one or more of these conditions:
• Power on.
• Manual push button.
• Remote reset from the debugger (using DSTREAM).
• Watchdog circuit (if appropriate to the application).
Any ARM processor including the JTAG interface has a second reset input called nTRST (TAP Reset).
This resets the EmbeddedICE logic, the Test Access Port (TAP) controller, and the boundary scan cells. It
is activated by remote JTAG reset (from DSTREAM).
ARM strongly recommends that both signals are separately available on the JTAG connector. If the
nRESET and nTRST signals are linked together, resetting the system also resets the TAP controller.
This means that:
• It is not possible to debug a system from reset, because any breakpoints previously set are lost.
• You might have to start the debug session from the beginning, because DSTREAM might not recover
when the TAP controller state is changed.
Related references
1.2.2 DSTREAM reset signals on page 1-16.
1.2.3 Example reset circuits on page 1-17.
1.2.2 DSTREAM reset signals
The DSTREAM unit has two reset signals connected to the debug target hardware, nTRST and nSRST.
What the signals do:
•nTRST drives the JTAG nTRST signal on the ARM processor. It is an output that is activated
whenever the debug software has to re-initialize the debug interface in the target system.
•nSRST is a bidirectional signal that both drives and senses the system reset signal on the target. By
default, this output is driven LOW by the debugger to re-initialize the target system.
The target hardware must pull the reset lines to their inactive state to assure normal operation when the
JTAG interface is disconnected. In the DSTREAM unit, the strong pull-up/pull-down resistance is
approximately 33Ω, and the weak pull-up/pull-down resistance is approximately 4.7kΩ. Because you can
select the drive strength for nTRST and nSRST, target assemblies with a variey of different reset
configurations can be supported.
Related references
1.2.1 ARM reset signals on page 1-16.
1.2.3 Example reset circuits on page 1-17.
Related information
Debug hardware Advanced configuration reset options.
1 ARM DSTREAM System Design Guidelines
1.2 Reset signals
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1.2.3 Example reset circuits
The diagram shows a typical reset circuit logic for the ARM reset signals and the DSTREAM reset
signals.
TRST
RESET
RST
RST
GndGnd
ARM
Processor
VDD
VDD
TAP RESET
SYSTEM RESET
Open-drain
reset devices
e.g. STM1001
To other
logic
VDD
VDD
nTRST
nSRST
Manual
reset
10K
10K
100R
100nF
Signals from JTAG connector
Figure 1-5 Example reset circuit logic
Related references
1.2.1 ARM reset signals on page 1-16.
1.2.2 DSTREAM reset signals on page 1-16.
1 ARM DSTREAM System Design Guidelines
1.2 Reset signals
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1.3 ASIC guidelines
This provides guidelines for ASIC designs.
This section contains the following subsections:
•1.3.1 ICs containing multiple devices on page 1-18.
•1.3.2 Boundary scan test vectors on page 1-19.
1.3.1 ICs containing multiple devices
If your ASIC contains multiple devices that have a JTAG Test Access Port (TAP) controller, you must
serially chain them so that DSTREAM can communicate with all of them simultaneously. The chaining
can either be within the ASIC, or externally.
Note
There is no support in DSTREAM for multiplexing TCK, TMS, TDI, TDO, and RTCK between a
number of different processors.
TAP controllers serially chained within the ASIC
The JTAG standard originally described serially chaining multiple devices on a PCB. This concept can
be extended to serially chaining multiple TAP controllers within an ASIC, as shown in the following
figure:
TDI
TDI TDO
TAP
Controller
TCK
nTRST
TMS
TDO
TDI
Second Tap Device
TDO
TCK
nTRST
TMS
TCK
nTRST
TMS
TAP
Controller
First Tap Device
Figure 1-6 TAP Controllers serially chained within an ASIC
This configuration does not increase the package pin count. It does increase JTAG propagation delays,
but this impact can be small if you put unaddressed TAP controllers into bypass mode.
TAP controllers serially chained externally
You can use separate pins on the ASIC for each JTAG port, and serially chain them externally (for
example on the PCB). This configuration can simplify device testing, and gives the greatest flexibility on
the PCB. However, this is at the cost of many pins on the device package.
Related concepts
1.3.2 Boundary scan test vectors on page 1-19.
1 ARM DSTREAM System Design Guidelines
1.3 ASIC guidelines
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Related information
CoreSight Technology System Design Guide.
1.3.2 Boundary scan test vectors
If you use the JTAG boundary scan test methodology to apply production test vectors, you might want to
have independent external access to each Test Access Port (TAP) controller. This avoids the requirement
to merge test vectors for more than one block in the device.
One solution to this is to adopt a hybrid, using a pin on the package that switches elements of the device
into a test mode. You can use this to break the internal daisy chaining of TDO and TDI signals, and to
multiplex out independent JTAG ports on pins that are used for another purpose during normal operation.
Related concepts
1.3.1 ICs containing multiple devices on page 1-18.
Related information
CoreSight Technology System Design Guide.
1 ARM DSTREAM System Design Guidelines
1.3 ASIC guidelines
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1.4 PCB guidelines
This provides PCB guidelines on the physical and electrical connections present on the target board.
This section contains the following subsections:
•1.4.1 PCB connections on page 1-20.
•1.4.2 Target interface logic levels on page 1-20.
1.4.1 PCB connections
The diagram shows a typical JTAG connection scheme.
TRST
RESET
ARM
Processor/
ASIC
10K
Signals from JTAG connector
TDI
TMS
TCK
RTCK
TDO
DBGRQ
DBGACK
10K
Gnd Gnd
Reset
circuit
22R
22R
0R
10K
10K
10K
10K
10K
VDD
Gnd
VTREF
TDI
TMS
TCK
RTCK
nTRST
nSRST
DBGRQ
TDO
DBGACK
GND
Figure 1-7 Typical PCB connections
Note
• The signals TDI, TMS, TCK, RTCK and TDO are typically pulled up on the target board to keep
them stable when the debug equipment is not connected.
•DBGRQ and DBGACK are typically pulled down on the target.
• If there is no RTCK signal provided on the processor, it can either be pulled to a fixed logic level or
connected to the TCK signal to provide a direct loop-back.
• All pull-up and pull-down resistors must be in the range 1K-100KΩ.
• The VTREF signal is typically connected directly to the VDD rail. If you use a series resistor to
protect against short-circuits, it must have a value no greater than 100Ω.
• To improve signal integrity, it is good practice to provide an impedance matching resistor on the
TDO and RTCK outputs of the processor. The value of these resistors, added to the impedance of the
driver must be approximately equal to 50Ω.
Related references
1.3 ASIC guidelines on page 1-18.
1.4.2 Target interface logic levels on page 1-20.
1.4.2 Target interface logic levels
DSTREAM is designed to interface with a wide range of target system logic levels. It does this by
adapting its output drive and input threshold to a reference voltage supplied by the target system.
1 ARM DSTREAM System Design Guidelines
1.4 PCB guidelines
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