ARM MPS2 Product manual

Arm® MPS2 and MPS2+ FPGA
Prototyping Boards
Technical Reference Manual
Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All rights reserved.
100112_0200_09_en

Arm® MPS2 and MPS2+ FPGA Prototyping Boards
Technical Reference Manual
Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All rights reserved.
Release Information
Document History
Issue Date Confidentiality Change
DDI0525A 20 December 2013 Non-Confidential First issue of TRM
DDI0525B 1 October 2014 Non-Confidential Second issue of TRM
DDI0525C 10 November 2014 Non-Confidential Third issue of TRM
0100-03 2 April 2015 Non-Confidential Fourth issue of TRM
0200-04 2 September 2015 Non-Confidential Fifth issue of TRM
0200-05 11 January 2016 Non-Confidential Sixth issue of TRM
0200-06 18 July 2016 Non-Confidential Seventh issue of TRM
0200-07 27 April 2018 Non-Confidential Eighth issue of TRM
0200-08 15 February 2019 Non-Confidential Ninth issue of TRM
0200-09 07 January 2020 Non-Confidential Tenth issue of TRM
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This document may include technical inaccuracies or typographical errors.
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Unrestricted Access is an Arm internal classification.
Product Status
The information in this document is Final, that is for a developed product.
Web Address
www.arm.com
Conformance Notices
This section contains conformance notices.
Federal Communications Commission Notice
This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).
CE Conformity
The Waste Electrical and Electronic Equipment (WEEE) marking, that is, the crossed out wheelie-bin figure, indicates that this
product must not be disposed of with general waste within the European Union. To prevent possible harm to the environment from
uncontrolled waste disposal, the user is required to recycle the product responsibly to promote reuse of material resources. To
comply with EU law, you must dispose of the product in one of the following ways:
• Return it to the distributer where it was purchased. The distributer is required to arrange free collection when requested.
• Recycle it using local WEEE recycling facilities. These facilities are now very common and might provide free collection.
• If purchased directly from Arm, Arm provides free collection. Please e-mail [email protected] for instructions.
The CE Declaration of Conformity for this product is available on request.
The system should be powered down when not in use.
It is recommended that ESD precautions be taken when handling this product.
The product generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications.
There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to
radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the
interference by one or more of the following measures:
• Ensure attached cables do not lie across any sensitive equipment.
• Reorient the receiving antenna.
• Increase the distance between the equipment and the receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
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Note
It is recommended that wherever possible shielded interface cables be used.
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Contents
Arm® MPS2 and MPS2+ FPGA Prototyping Boards
Technical Reference Manual
Preface
About this book ...................................................... ...................................................... 8
Feedback .................................................................................................................... 11
Chapter 1 Introduction
1.1 Precautions .............................................................................................................. 1-13
1.2 About the MPS2 and MPS2+ FPGA Prototyping Boards ........................................ 1-15
1.3 Location of components on the MPS2 FPGA Prototyping Board ............................ 1-17
1.4 Location of components on the MPS2+ FPGA Prototyping Board .......................... 1-19
Chapter 2 Hardware Description
2.1 Overview of the MPS2 and MPS2+ hardware ............................ ............................ 2-22
2.2 Clocks ...................................................................................................................... 2-25
2.3 Powerup, powerdown, and resets ..................................... ..................................... 2-27
2.4 User expansion port ................................................................................................ 2-28
2.5 USB 2.0 Full Speed interface .................................................................................. 2-29
2.6 SPI interface ............................................................................................................ 2-30
2.7 UART interface ........................................................................................................ 2-31
2.8 VGA and CLCD interfaces ........................................... ........................................... 2-32
2.9 Audio interface .................................................... .................................................... 2-33
2.10 Ethernet interface .................................................................................................... 2-34
2.11 User switches and user LEDs ........................................ ........................................ 2-35
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2.12 External user memory .............................................. .............................................. 2-36
2.13 MCC FPGA serial interface .......................................... .......................................... 2-39
2.14 Power ...................................................................................................................... 2-42
2.15 Debug and trace ...................................................................................................... 2-43
2.16 Minimum design settings for board operation .......................................................... 2-47
Chapter 3 Configuration
3.1 Overview of the configuration process .................................. .................................. 3-49
3.2 Remote USB operation ............................................................................................ 3-51
3.3 Configuration system ............................................... ............................................... 3-52
3.4 Powerup and configuration process ........................................................................ 3-53
3.5 Reset push buttons .................................................................................................. 3-55
3.6 Configuration files .................................................................................................... 3-56
Chapter 4 Programmers Model
4.1 About this programmers model ....................................... ....................................... 4-60
4.2 Memory map ............................................................................................................ 4-61
4.3 Register summary ................................................. ................................................. 4-62
4.4 SCC register descriptions ........................................................................................ 4-63
4.5 System configuration registers ................................................................................ 4-70
Chapter 5 Signal Descriptions
5.1 Debug connectors ................................................. ................................................. 5-75
5.2 Expansion connectors .............................................. .............................................. 5-80
5.3 CLCD connector ...................................................................................................... 5-82
5.4 USB 2.0 connector .................................................................................................. 5-83
5.5 UART connector ...................................................................................................... 5-84
5.6 SPI connector .......................................................................................................... 5-85
5.7 VGA connector ........................................................................................................ 5-86
5.8 Audio connectors .................................................. .................................................. 5-87
5.9 Ethernet connector .................................................................................................. 5-88
5.10 12V power connector ............................................... ............................................... 5-89
Appendix A Specifications
A.1 Electrical specification ......................................... ......................................... Appx-A-91
Appendix B Revisions
B.1 Revisions ................................................... ................................................... Appx-B-93
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Preface
This preface introduces the Arm® MPS2 and MPS2+ FPGA Prototyping Boards Technical Reference
Manual.
It contains the following:
•About this book on page 8.
•Feedback on page 11.
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rights reserved.
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About this book
This book describes the Arm® MPS2 and MPS2+ FPGA Prototyping Boards. Early issues of this book
had document number DDI0525.
Intended audience
This book is written for experienced hardware and software engineers who are doing Arm M-Class
processor evaluation and development using the Cortex®‑M Prototyping System, on either the MPS2 or
MPS2+ FPGA Prototyping Board.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
This chapter provides an introduction to the MPS2 and MPS2+ FPGA Prototyping Boards.
Chapter 2 Hardware Description
This chapter describes the MPS2 and MPS2+ board hardware.
Chapter 3 Configuration
This chapter describes the powerup and configuration process of the MPS2 and MPS2+ FPGA
Prototyping Boards.
Chapter 4 Programmers Model
This chapter describes the programmers model of the MPS2 and MPS2+ FPGA Prototyping
Boards.
Chapter 5 Signal Descriptions
This chapter describes the signals present at the interface connectors of the MPS2 and MPS2+
FPGA Prototyping Boards.
Appendix A Specifications
This chapter contains the electrical specification of the MPS2 and MPS2+ FPGA Prototyping
Boards and FPGAs.
Appendix B Revisions
This chapter describes the technical changes between released issues of this book.
Glossary
The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for those
terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning
differs from the generally accepted meaning.
See the Arm® Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
Preface
About this book
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monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the
Arm® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded
area at that time. The actual level is unimportant and does not affect normal operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Figure 1 Key to timing diagram conventions
Signals
The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Lowercase n
At the start or end of a signal name, n denotes an active-LOW signal.
Additional reading
This book contains information that is specific to this product. See the following documents for other
relevant information.
Preface
About this book
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rights reserved.
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Arm publications
•Cortex®-M0+ Technical Reference Manual (Arm DDI 0484)
•Cortex®-M0 Technical Reference Manual (Arm DDI 0432)
•Cortex®-M1 FPGA Development Kit Cortex-M1 User Guide: Altera Edition v1.1
(Arm DUI 0395)
•Cortex®-M1 FPGA Development Kit v1.1: Installation Guide (Arm DSI 0048)
•Cortex®-M1 Technical Reference Manual (Arm DDI 0413)
•Arm® Cortex®-M3 Technical Reference Manual (Arm 100165)
•Cortex®-M3 Devices Generic User Guide (Arm DUI 0552)
•Arm® Cortex®-M4 Processor Technical Reference Manual (Arm 100166)
•Cortex®-M4 Devices Generic User Guide (Arm DUI 0553)
•Arm® Cortex®-M System Design Kit Technical Reference Manual (Arm DDI 0479)
•Application Note AN382 Arm® Cortex®-M0 SMM on V2M_MPS2 (Arm DAI 0382)
•Application Note AN383 Arm® Cortex®-M0+ SMM on V2M-MPS2 (Arm DAI 0383)
•Application Note AN384 Arm® Cortex®-M1 SMM on V2M-MPS2 (Arm DAI 0384)
•Application Note AN385 Arm® Cortex®-M3 SMM on V2M-MPS2 (Arm DAI 0385)
•Application Note AN386 Arm® Cortex®-M4 SMM on V2M-MPS2 (Arm DAI 0386)
•Application Note AN387 Arm® Cortex®-M0 Design Start SMM on V2M-MPS2
(Arm DAI 0387)
•Application Note AN399 Arm® Cortex®-M7 SMM on V2M-MPS2 (Arm DAI 0399)
•Application Note AN400 Arm® Cortex®-M7CS SMM on V2M-MPS2 (Arm DAI 0400)
•Application Note AN502 Adapter for Arduino (Arm DAI 0502)
•Cortex®-M1 FPGA Development Kit Example System Tutorial: Altera Cyclone III Edition
(Arm DUI 0430)
•Arm® DSTREAM System and Interface Design Reference (Arm DUI 0499)
•Arm® DSTREAM Setting up the Hardware (Arm DUI 0481)
•Arm® DSTREAM and RVI Using the Debug Hardware Configuration Utilities
(Arm DUI 0498)
•Arm® CoreSight™ Components Technical Reference Manual (Arm DDI 0314)
Other publications
• See the Altera website http://altera.com for information on the Altera Cyclone 5CEA7
FPGA and the Altera Cyclone 5CEA9 FPGA.
Preface
About this book
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rights reserved.
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Feedback
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
• The product name.
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms and diagnostic
procedures if appropriate.
Feedback on content
If you have comments on content then send an e-mail to [email protected]. Give:
• The title Arm MPS2 and MPS2+ FPGA Prototyping Boards Technical Reference Manual.
• The number 100112_0200_09_en.
• If applicable, the page number(s) to which your comments refer.
• A concise explanation of your comments.
Arm also welcomes general suggestions for additions and improvements.
Note
Arm tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the
represented document when used with any other PDF reader.
Preface
Feedback
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Chapter 1
Introduction
This chapter provides an introduction to the MPS2 and MPS2+ FPGA Prototyping Boards.
It contains the following sections:
•1.1 Precautions on page 1-13.
•1.2 About the MPS2 and MPS2+ FPGA Prototyping Boards on page 1-15.
•1.3 Location of components on the MPS2 FPGA Prototyping Board on page 1-17.
•1.4 Location of components on the MPS2+ FPGA Prototyping Board on page 1-19.
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1.1 Precautions
You can take certain precautions to ensure safety and prevent damage to your MPS2 or MPS2+ FPGA
Prototyping Board.
This section contains the following subsections:
•1.1.1 Ensuring safety on page 1-13.
•1.1.2 Operating temperature on page 1-13.
•1.1.3 Preventing damage on page 1-13.
•1.1.4 Encryption key on page 1-13.
1.1.1 Ensuring safety
An on‑board connector supplies 12V DC to the board.
Warning
• Do not use the board near equipment that is sensitive to electromagnetic emissions, for example,
medical equipment.
• Any external 12V DC +/- 10% power supply that is used must be a limited power source.
1.1.2 Operating temperature
The MPS2 and MPS2+ FPGA Prototyping Boards have been tested in the temperature range 15°C to
30°C.
1.1.3 Preventing damage
The board is intended for use within a laboratory or engineering development environment. The board is
sensitive to electrostatic discharges and permits electromagnetic emissions.
Caution
To avoid damage to the board, observe the following precautions:
• You must connect the external power supply to the board before powerup to prevent damage.
• Never subject the board to high electrostatic potentials. Observe Electrostatic Discharge (ESD)
precautions when handling any board.
• Always wear a grounding strap when handling the board.
• Only hold the board by the edges.
• Avoid touching the component pins or any other metallic element except the metal shielding for the
connectors.
• Avoid contact with components on the board which might be hot or sharp.
• Ensure that the voltage on the pins of the FPGA and interface circuitry on the board is at the correct
level.
• You must not configure as outputs any FPGA pins that connect directly to other outputs or an external
signal source.
• Do not use the board near a transmitter of electromagnetic emissions.
1.1.4 Encryption key
Arm supplies the MPS2 and MPS2+ FPGA Prototyping Boards with encryption keys programmed into
the FPGAs.
1 Introduction
1.1 Precautions
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A battery supplies power to part of the FPGA that stores the AES decryption key. You use this key to
enable loading of encrypted images.
Caution
The decryption key is lost when this part of the FPGA loses power. If this happens, you must return the
board to Arm for reprogramming of the decryption key.
1 Introduction
1.1 Precautions
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1.2 About the MPS2 and MPS2+ FPGA Prototyping Boards
The MPS2 and MPS2+ FPGA Prototyping Boards are development platforms for Arm Cortex‑M
evaluation and development.
The MPS2 and MPS2+ FPGA Prototyping Boards provide the following:
Altera Cyclone FPGA and board powerup and configuration
The MPS2 FPGA Prototyping Board provides an Altera Cyclone 5CEA7 FPGA, and the
MPS2+ FPGA Prototyping Board provides an Altera Cyclone 5CEA9 FPGA, both speed grade
C8. Both boards support Arm Cortex‑M software evaluation and development. A Motherboard
Configuration Controller (MCC) supports board powerup and configuration. An on‑board
EEPROM stores board and file identification information and a microSD card stores FPGA and
software images and configuration files. You can access the microSD card to perform
configuration file editing and to update FPGA and software images.
Caution
Images that are created for the Altera Cyclone 5CEA7 FPGA are not compatible with the Altera
Cyclone 5CEA9 FPGA. Images that are created for the Altera Cyclone 5CEA9 FPGA are not
compatible with the Altera Cyclone 5CEA7 FPGA.
External user memory
On‑board external SSRAM and PSRAM connect to memory interfaces in the FPGA.
Access ports
The MPS2 and MPS2+ FPGA Prototyping Boards provide access through Ethernet,
general‑purpose UART, and SPI ports. A general‑purpose user expansion port supports user
expansion to extra signal or bus I/O.
Video and audio output
The MPS2 and MPS2+ FPGA Prototyping Boards provide video output through VGA and
CLCD ports. The CLCD port drives an LCD module that is configured for SPI graphics and I2C
touch screen. Input and output audio ports connect to a stereo audio codec which connects to an
I2S digital audio interface on the FPGA.
User LEDs and user switches
The MPS2 and MPS2+ FPGA Prototyping Boards provide user LEDs, an 8-way dip switch and
push buttons that connect to the FPGA and to the MCC. The meaning of these LEDs and push
buttons depend on the image that you implement in the FPGA.
System LEDs
The MPS2 and MPS2+ FPGA Prototyping Boards provide LEDs which denote Configuration
Complete, MCC Powered, Ethernet Duplex Link Established, Ethernet Link Operating at
100Mbs, Ethernet Link Established, and microSD Card Read or Write Access.
1 Introduction
1.2 About the MPS2 and MPS2+ FPGA Prototyping Boards
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Debug
The MPS2 and MPS2+ FPGA Prototyping Boards support P-JTAG Processor debug, F-JTAG
Integrated Logic Analyzer (ILA) FPGA debug, 4-bit trace and 16-bit trace debug, and CMSIS-
DAP FPGA debug.
Note
The MPS2 and MPS2+ FPGA Prototyping Boards require MCC firmware version 2.0.1 or later
to support CMSIS-DAP FPGA debug.
1 Introduction
1.2 About the MPS2 and MPS2+ FPGA Prototyping Boards
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1.3 Location of components on the MPS2 FPGA Prototyping Board
The following figure shows the upper face of the MPS2 FPGA Prototyping Board.
Expansion
connector
EXP2
Expansion
connector
EXP1
LCD display panel
2MB ZBT
SSRAM
12V DC
power jack
RJ45
Ethernet
connector Out VGA General
purpose
UART
Stereo line
audio
JTAG 14
connector
JTAG 20
connector
MICTOR 38
connector
CoreSight 20
connector
CoreSight 10
connector
Reserved
MCC
PSRAM
8MB
ON/OFF
soft RESET
push button
Hardware
RESET
push button
MCC
user
LEDs
FPGA user push
buttons
PB0PB1
SPI
header
In
Altera Cyclone 5CEA7
FPGA MCC user
switches
Clock
connection
headers and
slide switches
J22
J23
J18
J19
Ethernet
activity
LEDs DPLX
LINK
100Mbs
USB 2.0
configuration
port
FPGA
user
LED 1
1
8
7
6
5
4
3
2
HDD
PWR
DONE
System
LEDs
1
8
7
6
5
4
3
2
FPGA
user
LED 0
3V battery
Figure 1-1 Upper face of the MPS2 FPGA Prototyping Board.
The following figure shows the lower face of the MPS2 FPGA Prototyping Board.
1 Introduction
1.3 Location of components on the MPS2 FPGA Prototyping Board
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2MB ZBT
SSRAM
2MB ZBT
SSRAM
microSD
Card
Figure 1-2 Lower face of the MPS2 FPGA Prototyping Board.
1 Introduction
1.3 Location of components on the MPS2 FPGA Prototyping Board
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1.4 Location of components on the MPS2+ FPGA Prototyping Board
The following figure shows the upper face of the MPS2+ FPGA Prototyping Board.
Expansion
connector
EXP2
Expansion
connector
EXP1
LCD display panel
2MB ZBT
SSRAM
12V DC
power jack
RJ45
Ethernet
connector
Out
VGA General
purpose
UART
Stereo line
audio
JTAG 14
connector
JTAG 20
connector
MICTOR 38
connector
CoreSight 20
connector
CoreSight 10
connector
Reserved
MCC
PSRAM
8MB
ON/OFF
soft RESET
push button
Hardware
RESET
push button
MCC
user
LEDs
FPGA user push
buttons
PB0PB1
SPI
header
In
Altera Cyclone 5CEA9
FPGA MCC user
switches
Clock
connection
headers and
slide switches
J22
J23
J18
J19
Ethernet
activity
LEDs DPLX
LINK
100Mbs
USB 2.0
configuration
port
FPGA
user
LED 1
1
8
7
6
5
4
3
2
HDD
PWR
DONE
System
LEDs
1
8
7
6
5
4
3
2
FPGA
user
LED 0
3V battery
Figure 1-3 Upper face of the MPS2+ FPGA Prototyping Board
The following figure shows the lower face of the MPS2+ FPGA Prototyping Board.
1 Introduction
1.4 Location of components on the MPS2+ FPGA Prototyping Board
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2MB ZBT
SSRAM
2MB ZBT
SSRAM
microSD
Card
Figure 1-4 Lower face of the MPS2+ FPGA Prototyping Board.
1 Introduction
1.4 Location of components on the MPS2+ FPGA Prototyping Board
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