ARM Cortex-M3 DesignStart Product manual

Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
Cortex-M3™
Revision: r0p0
Technical Reference Manual

ii Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
Cortex-M3
Technical Reference Manual
Copyright © 2005, 2006 ARM Limited. All rights reserved.
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Date Issue Confidentiality Change
15 December 2005 A Confidential First Release
13 January 2006 B Non-Confidential Confidentiality status amended

ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. iii
Contents
Cortex-M3 Technical Reference Manual
Preface
About this manual ...................................................................................... xviii
Feedback ................................................................................................... xxiii
Chapter 1 Introduction
1.1 About the processor .................................................................................... 1-2
1.2 Components of the processor ..................................................................... 1-4
1.3 Configurable options ................................................................................. 1-12
1.4 Instruction set summary ............................................................................ 1-13
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Privileged access and User access ............................................................ 2-3
2.3 Registers ..................................................................................................... 2-4
2.4 Data types ................................................................................................. 2-10
2.5 Memory formats ........................................................................................ 2-11
2.6 Instruction set ............................................................................................ 2-13
Chapter 3 System Control
3.1 Summary of processor registers ................................................................. 3-2

Contents
iv Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
Chapter 4 Memory Map
4.1 About the memory map .............................................................................. 4-2
4.2 Bit-banding ................................................................................................. 4-5
4.3 ROM memory table .................................................................................... 4-8
Chapter 5 Exceptions
5.1 About the exception model ......................................................................... 5-2
5.2 Exception types .......................................................................................... 5-3
5.3 Exception priority ........................................................................................ 5-5
5.4 Privilege and stacks .................................................................................... 5-8
5.5 Pre-emption .............................................................................................. 5-10
5.6 Tail-chaining ............................................................................................. 5-13
5.7 Late-arriving .............................................................................................. 5-14
5.8 Exit ............................................................................................................ 5-16
5.9 Resets ...................................................................................................... 5-19
5.10 Exception control transfer ......................................................................... 5-23
5.11 Setting up multiple stacks ......................................................................... 5-24
5.12 Abort model .............................................................................................. 5-26
5.13 Activation levels ........................................................................................ 5-31
5.14 Flowcharts ................................................................................................ 5-33
Chapter 6 Clocking and Resets
6.1 Cortex-M3 clocking ..................................................................................... 6-2
6.2 Cortex-M3 resets ........................................................................................ 6-4
6.3 Cortex-M3 reset modes .............................................................................. 6-5
Chapter 7 Power Management
7.1 About power management ......................................................................... 7-2
7.2 System power management ....................................................................... 7-3
Chapter 8 Nested Vectored Interrupt Controller
8.1 About the NVIC ........................................................................................... 8-2
8.2 NVIC programmer’s model ......................................................................... 8-3
8.3 Level versus pulse interrupts .................................................................... 8-39
Chapter 9 Memory Protection Unit
9.1 About the MPU ........................................................................................... 9-2
9.2 MPU programmer’s model .......................................................................... 9-3
9.3 MPU access permissions ......................................................................... 9-14
9.4 MPU aborts ............................................................................................... 9-16
9.5 Updating an MPU region .......................................................................... 9-17
9.6 Interrupts and updating the MPU .............................................................. 9-20
Chapter 10 Core Debug
10.1 About core debug ..................................................................................... 10-2

Contents
ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. v
10.2 Core debug registers ................................................................................ 10-3
10.3 Core debug access example .................................................................. 10-12
10.4 Using application registers in core debug ............................................... 10-13
Chapter 11 System Debug
11.1 About system debug ................................................................................. 11-2
11.2 System Debug Access .............................................................................. 11-3
11.3 System debug programmer’s model ......................................................... 11-5
11.4 Flash Patch and Breakpoint ...................................................................... 11-6
11.5 Data Watchpoint and Trace .................................................................... 11-13
11.6 Instrumentation Trace Macrocell ............................................................. 11-28
11.7 AHB Access Port .................................................................................... 11-37
Chapter 12 Debug Port
12.1 About the Debug Port ............................................................................... 12-2
12.2 JTAG-DP ................................................................................................... 12-3
12.3 SW-DP .................................................................................................... 12-20
12.4 Common Debug Port (DP) features ........................................................ 12-41
12.5 Debug Port Programmer’s Model ............................................................ 12-47
Chapter 13 Trace Port Interface Unit
13.1 About the Trace Port Interface Unit .......................................................... 13-2
13.2 TPIU registers ........................................................................................... 13-8
Chapter 14 Bus Interface
14.1 About bus interfaces ................................................................................. 14-2
14.2 ICode bus interface ................................................................................... 14-3
14.3 DCode bus interface ................................................................................. 14-5
14.4 System interface ....................................................................................... 14-6
14.5 External private peripheral interface ......................................................... 14-8
14.6 Access alignment ...................................................................................... 14-9
14.7 Unaligned accesses that cross regions ................................................... 14-10
14.8 Bit-band accesses ................................................................................... 14-11
14.9 Write buffer ............................................................................................. 14-12
14.10 Memory attributes ................................................................................... 14-13
Chapter 15 Embedded Trace Macrocell
15.1 About the ETM .......................................................................................... 15-2
15.2 Data tracing ............................................................................................... 15-6
15.3 ETM Resources ........................................................................................ 15-7
15.4 Trace output .............................................................................................. 15-9
15.5 ETM architecture ..................................................................................... 15-10
15.6 ETM programmer’s model ....................................................................... 15-14
Chapter 16 Embedded Trace Macrocell Interface
16.1 About the ETM interface ........................................................................... 16-2

Contents
vi Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
16.2 CPU ETM interface port descriptions ....................................................... 16-3
16.3 Branch status interface ............................................................................. 16-5
Chapter 17 Instruction Timing
17.1 About instruction timing ............................................................................ 17-2
17.2 Processor instruction timings .................................................................... 17-3
17.3 Load-store timings .................................................................................... 17-7
Appendix A Signal Descriptions
A.1 Clocks ......................................................................................................... A-2
A.2 Resets ........................................................................................................ A-3
A.3 Miscellaneous ............................................................................................. A-4
A.4 Interrupt interface ....................................................................................... A-5
A.5 ICode interface ........................................................................................... A-6
A.6 DCode interface .......................................................................................... A-8
A.7 System bus interface .................................................................................. A-9
A.8 Private Peripheral Bus interface ............................................................... A-10
A.9 ITM interface ............................................................................................. A-11
A.10 AHB-AP interface ..................................................................................... A-12
A.11 ETM interface ........................................................................................... A-13
A.12 Test interface ............................................................................................ A-15
Glossary

ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. vii
List of Tables
Cortex-M3 Technical Reference Manual
Change History ............................................................................................................. ii
Table 1-1 16-bit Cortex-M3 instruction summary .................................................................... 1-13
Table 1-2 32-bit Cortex-M3 instruction summary .................................................................... 1-16
Table 2-1 Application Program Status Register bit assignments .............................................. 2-6
Table 2-2 Interrupt Program Status Register bit assignments .................................................. 2-7
Table 2-3 Bit functions of the Execution PSR ........................................................................... 2-8
Table 2-4 Nonsupported Thumb instructions .......................................................................... 2-13
Table 2-5 Supported Thumb-2 instructions ............................................................................. 2-13
Table 3-1 NVIC registers ........................................................................................................... 3-2
Table 3-2 Core debug registers ................................................................................................. 3-5
Table 3-3 Flash patch register summary ................................................................................... 3-6
Table 3-4 DWT register summary ............................................................................................. 3-7
Table 3-5 ITM register summary ............................................................................................... 3-9
Table 3-6 AHB-AP register summary ...................................................................................... 3-10
Table 3-7 Summary of Debug Port registers ........................................................................... 3-11
Table 3-8 MPU registers ......................................................................................................... 3-11
Table 3-9 TPIU registers ......................................................................................................... 3-12
Table 3-10 ETM registers .......................................................................................................... 3-13
Table 4-1 Memory interfaces ..................................................................................................... 4-3
Table 4-2 Memory region permissions ...................................................................................... 4-4
Table 4-3 Cortex-M3 ROM table ............................................................................................... 4-8
Table 5-1 Exception types ......................................................................................................... 5-3
Table 5-2 Priority-based actions of exceptions ......................................................................... 5-5

List of Tables
viii Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
Table 5-3 Priority grouping ........................................................................................................ 5-7
Table 5-4 Exception entry steps ............................................................................................. 5-11
Table 5-5 Exception exit steps ................................................................................................ 5-16
Table 5-6 Exception return behavior ....................................................................................... 5-18
Table 5-7 Reset actions .......................................................................................................... 5-19
Table 5-8 Reset boot-up behavior .......................................................................................... 5-20
Table 5-9 Transferring to exception processing ...................................................................... 5-23
Table 5-10 Faults ...................................................................................................................... 5-27
Table 5-11 Debug faults ............................................................................................................ 5-29
Table 5-12 Fault status and fault address registers .................................................................. 5-30
Table 5-13 Privilege and stack of different activation levels ..................................................... 5-31
Table 5-14 Exception transitions ............................................................................................... 5-31
Table 5-15 Exception subtype transitions ................................................................................. 5-32
Table 6-1 Cortex-M3 processor clocks ..................................................................................... 6-2
Table 6-2 Cortex-M3 macrocell clocks ...................................................................................... 6-2
Table 6-3 Reset inputs .............................................................................................................. 6-4
Table 6-4 Reset modes ............................................................................................................. 6-5
Table 7-1 Supported sleep modes ........................................................................................... 7-3
Table 8-1 NVIC registers .......................................................................................................... 8-3
Table 8-2 Interrupt Controller Type Register bit assignments .................................................. 8-7
Table 8-3 SysTick Control and Status Register bit assignments ............................................. 8-8
Table 8-4 SysTick Reload Value Register bit assignments ...................................................... 8-9
Table 8-5 SysTick Current Value Register bit assignments .................................................... 8-10
Table 8-6 SysTick Calibration Value Register bit assignments .............................................. 8-11
Table 8-7 Bit functions of the Interrupt Set-Enable Register ................................................... 8-12
Table 8-8 Bit functions of the Interrupt Clear-Enable Register ............................................... 8-12
Table 8-9 Bit functions of the Interrupt Set-Pending Register ................................................. 8-13
Table 8-10 Bit functions of the Interrupt Clear-Pending Registers ............................................ 8-14
Table 8-11 Bit functions of the Active Bit Register .................................................................... 8-14
Table 8-12 Interrupt Priority Registers 0-31 bit assignments .................................................... 8-16
Table 8-13 CPUID Base Register bit assignments ................................................................... 8-16
Table 8-14 Interrupt Control State Register bit assignments .................................................... 8-18
Table 8-15 Vector Table Offset Register bit assignments ........................................................ 8-20
Table 8-16 Application Interrupt and Reset Control Register bit assignments ......................... 8-21
Table 8-17 System Control Register bit assignments ............................................................... 8-23
Table 8-18 Configuration Control Register bit assignments ..................................................... 8-24
Table 8-19 System Handler Priority Registers bit assignments ................................................ 8-26
Table 8-20 System Handler Control and State Register bit assignment ................................... 8-27
Table 8-21 Memory Manage Fault Status Register bit assignments ........................................ 8-30
Table 8-22 Bus Fault Status Register bit assignments ............................................................. 8-31
Table 8-23 Usage Fault Status Register bit assignments ......................................................... 8-33
Table 8-24 Hard Fault Status Register bit assignments ........................................................... 8-34
Table 8-25 Debug Fault Status Register bit assignments ......................................................... 8-36
Table 8-26 Bit functions of the Memory Manage Fault Address Register ................................. 8-37
Table 8-27 Bit functions of the Bus Fault Address Register ..................................................... 8-37
Table 8-28 Software Trigger Interrupt Register bit assignments .............................................. 8-38
Table 9-1 MPU registers ........................................................................................................... 9-3

List of Tables
ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. ix
Table 9-2 MPU Type Register bit assignments ......................................................................... 9-4
Table 9-3 MPU Control Register bit assignments ..................................................................... 9-6
Table 9-4 MPU Region Number Register bit assignments ........................................................ 9-7
Table 9-5 MPU Region Base Address Register bit assignments .............................................. 9-8
Table 9-6 MPU Region Attribute and Size Register bit assignments ........................................ 9-9
Table 9-7 MPU protection region size field ............................................................................. 9-11
Table 9-8 TEX, C, B encoding ................................................................................................. 9-14
Table 9-9 Cache policy for memory attribute encoding ........................................................... 9-15
Table 9-10 AP encoding ............................................................................................................ 9-15
Table 9-11 XN encoding ............................................................................................................ 9-15
Table 10-1 Core debug registers ............................................................................................... 10-2
Table 10-2 Debug Halting Control and Status Register ............................................................ 10-4
Table 10-3 Debug Core Selector Register ................................................................................ 10-7
Table 10-4 Debug Exception and Monitor Control Register ...................................................... 10-9
Table 10-5 Application registers for use in core debug ........................................................... 10-13
Table 11-1 Flash patch register summary ................................................................................. 11-7
Table 11-2 Flash Patch Control Register bit assignments ........................................................ 11-8
Table 11-3 COMP mapping ..................................................................................................... 11-10
Table 11-4 Flash Patch Remap Register bit assignments ...................................................... 11-11
Table 11-5 Flash Patch Comparator Registers bit assignments ............................................. 11-12
Table 11-6 DWT register summary ......................................................................................... 11-13
Table 11-7 DWT Control Register bit assignments ................................................................. 11-16
Table 11-8 DWT Current PC Sampler Cycle Count Register bit assignments ........................ 11-19
Table 11-9 DWT CPI Count Register bit assignments ............................................................ 11-20
Table 11-10 DWT Exception Overhead Count Register bit assignments .................................. 11-21
Table 11-11 DWT Sleep Count Register bit assignments ......................................................... 11-21
Table 11-12 DWT LSU Count Register bit assignments ........................................................... 11-22
Table 11-13 DWT Fold Count Register bit assignments ........................................................... 11-23
Table 11-14 DWT Comparator Registers 0-3 bit assignments .................................................. 11-23
Table 11-15 DWT Mask Registers 0-3 bit assignments ............................................................ 11-24
Table 11-16 Bit functions of DWT Function Registers 0-3 ........................................................ 11-25
Table 11-17 Settings for DWT Function Registers .................................................................... 11-26
Table 11-18 ITM register summary ........................................................................................... 11-28
Table 11-19 Bit functions of the ITM Trace Enable Register ..................................................... 11-30
Table 11-20 Bit functions of the ITM Trace Privilege Register .................................................. 11-31
Table 11-21 Bit functions of the ITM Control Register .............................................................. 11-32
Table 11-22 Bit functions of the ITM Integration Write Register ................................................ 11-34
Table 11-23 Bit functions of the ITM Integration Read Register ............................................... 11-34
Table 11-24 Bit functions of the ITM Integration Mode Control Register .................................. 11-35
Table 11-25 Bit functions of the ITM Lock Access Register ...................................................... 11-35
Table 11-26 Bit functions of the ITM Lock Status Register ....................................................... 11-36
Table 11-27 AHB-AP register summary .................................................................................... 11-37
Table 11-28 Bit functions of the AHB-AP Control and Status Word Register ............................ 11-39
Table 11-29 AHB-AP Transfer Address Register bit functions .................................................. 11-40
Table 11-30 Bit functions of the AHB-AP Data Read/Write Register ........................................ 11-41
Table 11-31 Bit functions of the AHB-AP Banked Data Register .............................................. 11-41
Table 11-32 Bit functions of the AHB-AP Debug ROM Address Register ................................. 11-42

List of Tables
x Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
Table 11-33 Bit functions of the AHB-AP ID Register ............................................................... 11-42
Table 12-1 JTAG-DP signal connections .................................................................................. 12-3
Table 12-2 Standard IR instructions ......................................................................................... 12-8
Table 12-3 Recommended implementation-defined IR instructions for IEEE 1149.1-compliance ....
12-9
Table 12-4 DPACC and APACC ACK responses ................................................................... 12-12
Table 12-5 JTAG target response summary ........................................................................... 12-17
Table 12-6 Summary of JTAG host responses ....................................................................... 12-18
Table 12-7 Target response summary for DP read transaction requests ............................... 12-33
Table 12-8 Target response summary for AP read transaction requests ............................... 12-34
Table 12-9 Target response summary for DP write transaction requests ............................... 12-35
Table 12-10 Target response summary for AP write transaction requests ............................... 12-36
Table 12-11 Summary of host (debugger) responses to the SW-DP acknowledge ................. 12-37
Table 12-12 Terms used in SW-DP timing ............................................................................... 12-38
Table 12-13 JTAG-DP register map ......................................................................................... 12-47
Table 12-14 SW-DP register map ............................................................................................. 12-49
Table 12-15 Abort Register bit assignments ............................................................................. 12-50
Table 12-16 Identification Code Register bit assignments ........................................................ 12-52
Table 12-17 JEDEC JEP-106 manufacturer ID code, with ARM Limited values ...................... 12-53
Table 12-18 Control/Status Register bit assignments ............................................................... 12-54
Table 12-19 Control of pushed operation comparisons by MASKLANE ................................... 12-56
Table 12-20 Transfer Mode, TRNMODE, bit definitions ........................................................... 12-57
Table 12-21 Bit assignments for the AP Select Register, SELECT .......................................... 12-58
Table 12-22 CTRLSEL field bit definitions ................................................................................ 12-59
Table 12-23 Bit assignments for the Wire Control Register (SW-DP only) ............................... 12-61
Table 12-24 Turnaround tri-state period field, TURNROUND, bit definitions ........................... 12-61
Table 12-25 Wire operating mode, WIREMODE, bit definitions ............................................... 12-62
Table 13-1 Trace Out Port signals ............................................................................................ 13-5
Table 13-2 ATB Port signals ..................................................................................................... 13-6
Table 13-3 Miscellaneous configuration inputs ......................................................................... 13-7
Table 13-4 TPIU registers ......................................................................................................... 13-8
Table 13-5 Current Output Speed Divisors Register bit assignments ...................................... 13-9
Table 13-6 Selected Pin Protocol Register bit assignments ................................................... 13-10
Table 13-7 Formatter and Flush Status Register bit assignments .......................................... 13-11
Table 13-8 Integration Test Register bit assignments ............................................................ 13-13
Table 13-9 Integration Test Register bit assignments ............................................................ 13-13
Table 14-1 Instruction fetches ................................................................................................... 14-3
Table 14-2 Bus mapper unaligned accesses ............................................................................ 14-9
Table 14-3 Memory attributes ................................................................................................. 14-13
Table 15-1 Cortex-M3 resources .............................................................................................. 15-4
Table 15-2 Exception tracing mapping ................................................................................... 15-11
Table 15-3 ETM registers ....................................................................................................... 15-14
Table 16-1 ETM interface ports ................................................................................................ 16-3
Table 17-1 Instruction timings ................................................................................................... 17-3
Table A-1 Clock signals ............................................................................................................. A-2
Table A-2 Reset signals ............................................................................................................ A-3
Table A-3 Miscellaneous signals ............................................................................................... A-4

List of Tables
ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. xi
Table A-4 Interrupt interface ...................................................................................................... A-5
Table A-5 ICode interface .......................................................................................................... A-6
Table A-6 DCode interface ........................................................................................................ A-8
Table A-7 System bus interface ................................................................................................. A-9
Table A-8 Private Peripheral Bus interface .............................................................................. A-10
Table A-9 ITM interface ........................................................................................................... A-11
Table A-10 AHB-AP interface .................................................................................................... A-12
Table A-11 ETM interface .......................................................................................................... A-13
Table A-12 Test interface .......................................................................................................... A-15

List of Tables
xii Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B

ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. xiii
List of Figures
Cortex-M3 Technical Reference Manual
Key to timing diagram conventions ............................................................................ xxi
Figure 1-1 Cortex-M3 block diagram .......................................................................................... 1-5
Figure 2-1 Cortex-M3 register set ............................................................................................... 2-4
Figure 2-2 Application Program Status Register bit assignments .............................................. 2-5
Figure 2-3 Interrupt Program Status Register bit assignments .................................................. 2-6
Figure 2-4 Execution Program Status Register .......................................................................... 2-8
Figure 2-5 Little-endian and big-endian memory formats ......................................................... 2-12
Figure 4-1 The Cortex-M3 Memory Map .................................................................................... 4-2
Figure 4-2 Bit-band mapping ...................................................................................................... 4-6
Figure 5-1 Stack contents after a pre-emption ......................................................................... 5-10
Figure 5-2 Exception entry timing ............................................................................................. 5-12
Figure 5-3 Tail-chaining timing ................................................................................................. 5-13
Figure 5-4 Late-arriving exception timing ................................................................................. 5-14
Figure 5-5 Exception exit timing ............................................................................................... 5-17
Figure 5-6 Interrupt handling flowchart ..................................................................................... 5-33
Figure 5-7 Pre-emption flowchart ............................................................................................. 5-34
Figure 5-8 Return from interrupt flowchart ................................................................................ 5-35
Figure 6-1 Reset signals ............................................................................................................. 6-6
Figure 6-2 Power-on reset .......................................................................................................... 6-6
Figure 6-3 Internal reset synchronization ................................................................................... 6-7
Figure 7-1 SLEEPING power control example ........................................................................... 7-4
Figure 7-2 SLEEPDEEP power control example ........................................................................ 7-5
Figure 8-1 Interrupt Controller Type Register bit assignments ................................................... 8-7

List of Figures
xiv Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
Figure 8-2 SysTick Control and Status Register bit assignments .............................................. 8-8
Figure 8-3 SysTick Reload Value Register bit assignments ...................................................... 8-9
Figure 8-4 SysTick Current Value Register bit assignments .................................................... 8-10
Figure 8-5 SysTick Calibration Value Register bit assignments .............................................. 8-10
Figure 8-6 Interrupt Priority Registers 0-31 bit assignments .................................................... 8-15
Figure 8-7 CPUID Base Register bit assignments ................................................................... 8-16
Figure 8-8 Interrupt Control State Register bit assignments .................................................... 8-18
Figure 8-9 Vector Table Offset Register bit assignments ........................................................ 8-20
Figure 8-10 Application Interrupt and Reset Control Register bit assignments ......................... 8-21
Figure 8-11 System Control Register bit assignments ............................................................... 8-23
Figure 8-12 Configuration Control Register bit assignments .................................................... 8-24
Figure 8-13 System Handler Priority Registers bit assignments ................................................ 8-26
Figure 8-14 System Handler Control and State Register bit assignments ................................. 8-27
Figure 8-15 Local fault status registers bit assignments ............................................................ 8-29
Figure 8-16 Memory Manage Fault Register bit assignments ................................................... 8-30
Figure 8-17 Bus Fault Status Register bit assignments ............................................................. 8-31
Figure 8-18 Usage Fault Status Register bit assignments ......................................................... 8-33
Figure 8-19 Hard Fault Status Register bit assignments ........................................................... 8-34
Figure 8-20 Debug Fault Status Register bit assignments ......................................................... 8-35
Figure 8-21 Software Trigger Interrupt Register bit assignments .............................................. 8-38
Figure 9-1 MPU Type Register bit assignments ........................................................................ 9-4
Figure 9-2 MPU Control Register bit assignments ..................................................................... 9-5
Figure 9-3 MPU Region Number Register bit assignments ....................................................... 9-7
Figure 9-4 MPU Region Base Address Register bit assignments .............................................. 9-8
Figure 9-5 MPU Region Attribute and Size Register bit assignments ........................................ 9-9
Figure 10-1 Debug Halting Control and Status Register format ................................................. 10-4
Figure 10-2 Debug Core Selector Register format ..................................................................... 10-6
Figure 10-3 Debug Exception and Monitor Control Register format .......................................... 10-9
Figure 11-1 System debug access block diagram ..................................................................... 11-4
Figure 11-2 Flash Patch Control Register bit assignments ........................................................ 11-8
Figure 11-3 Flash Patch Remap Register bit assignments ...................................................... 11-10
Figure 11-4 Flash Patch Comparator Registers bit assignments ............................................. 11-11
Figure 11-5 DWT Control Register bit assignments ................................................................. 11-15
Figure 11-6 DWT CPI Count Register bit assignments ............................................................ 11-20
Figure 11-7 DWT Exception Overhead Count Register bit assignments ................................. 11-20
Figure 11-8 DWT Sleep Count Register bit assignments ........................................................ 11-21
Figure 11-9 DWT LSU Count Register bit assignments ........................................................... 11-22
Figure 11-10 DWT Fold Count Register bit assignments ........................................................... 11-23
Figure 11-11 DWT Mask Registers 0-3 bit assignments ............................................................ 11-24
Figure 11-12 DWT Function Registers 0-3 bit assignments ...................................................... 11-25
Figure 11-13 ITM Trace Privilege Register bit assignments ...................................................... 11-31
Figure 11-14 ITM Control Register bit assignments ................................................................... 11-32
Figure 11-15 ITM Integration Write Register bit assignments .................................................... 11-33
Figure 11-16 ITM Integration Read Register bit assignments .................................................... 11-34
Figure 11-17 ITM Integration Mode Control bit assignments ..................................................... 11-35
Figure 11-18 ITM Lock Status Register bit assignments ........................................................... 11-36
Figure 11-19 AHB-AP Control and Status Word Register .......................................................... 11-38

List of Figures
ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. xv
Figure 11-20 AHB-AP ID Register .............................................................................................. 11-42
Figure 12-1 JTAG-DP physical connection ................................................................................ 12-4
Figure 12-2 The DAP State Machine (JTAG) ............................................................................. 12-5
Figure 12-3 JTAG Instruction Register bit order ......................................................................... 12-7
Figure 12-4 JTAG Bypass Register operation .......................................................................... 12-10
Figure 12-5 JTAG Device ID Code Register bit order .............................................................. 12-11
Figure 12-6 Bit order of JTAG DP and AP Access Registers ................................................... 12-13
Figure 12-7 JTAG-DP ABORT scan chain bit order ................................................................. 12-19
Figure 12-8 Serial Wire Debug successful write operation ....................................................... 12-25
Figure 12-9 Serial Wire Debug successful read operation ....................................................... 12-25
Figure 12-10 Serial Wire Debug WAIT response to a packet request ........................................ 12-26
Figure 12-11 Serial Wire Debug FAULT response to a packet request ..................................... 12-26
Figure 12-12 Serial Wire Debug protocol error after a packet request ....................................... 12-27
Figure 12-13 Serial Wire WAIT or FAULT response to a read operation when overrun detection is en-
abled ..................................................................................................................... 12-31
Figure 12-14 Serial Wire WAIT or FAULT response to a write operation when overrun detection is en-
abled ..................................................................................................................... 12-31
Figure 12-15 SW-DP acknowledgement timing .......................................................................... 12-38
Figure 12-16 SW-DP to DAP bus timing for writes ..................................................................... 12-39
Figure 12-17 SW-DP to DAP bus timing for reads ..................................................................... 12-39
Figure 12-18 SW-DP idle timing ................................................................................................. 12-40
Figure 12-19 Pushed operations overview ................................................................................. 12-44
Figure 12-20 Abort Register bit assignments ............................................................................. 12-50
Figure 12-21 Identification Code Register bit assignments ........................................................ 12-52
Figure 12-22 Control/Status Register bit assignments ............................................................... 12-54
Figure 12-23 Bit assignments for the AP Select Register, SELECT .......................................... 12-58
Figure 12-24 Bit assignments for the Wire Control Register (SW-DP only) ............................... 12-60
Figure 13-1 Block diagram of the TPIU (non-ETM version) ........................................................ 13-3
Figure 13-2 Block diagram of the TPIU (ETM version) ............................................................... 13-4
Figure 13-3 Supported Port Size Register bit assignments ........................................................ 13-9
Figure 13-4 Current Output Speed Divisors Register bit assignments ....................................... 13-9
Figure 13-5 Selected Pin Protocol Register bit assignments .................................................. 13-10
Figure 13-6 Formatter and Flush Status Register bit assignments ......................................... 13-11
Figure 13-7 Integration Test Register bit assignments ............................................................. 13-12
Figure 13-8 Integration Test Register bit assignments ............................................................. 13-13
Figure 15-1 ETM block diagram ................................................................................................. 15-3
Figure 15-2 Exception return packet encoding ......................................................................... 15-10
Figure 15-3 Exception encoding for branch packet .................................................................. 15-13
Figure 16-1 Conditional branch backwards not taken ................................................................ 16-5
Figure 16-2 Conditional branch backwards taken ...................................................................... 16-5
Figure 16-3 Conditional branch forwards not taken .................................................................... 16-6
Figure 16-4 Conditional branch forwards taken ......................................................................... 16-6
Figure 16-5 Unconditional branch without pipeline stalls .......................................................... 16-6
Figure 16-6 Unconditional branch with pipeline stalls ............................................................... 16-7
Figure 16-7 Unconditional branch in execute aligned ................................................................ 16-7
Figure 16-8 Unconditional branch in execute unaligned ............................................................ 16-7

List of Figures
xvi Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B

ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. xvii
Preface
This preface introduces the Cortex-M3 r0p0 Technical Reference Manual. It contains
the following sections:
•About this manual on page xviii
•Feedback on page xxiii.

Preface
xviii Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
About this manual
This is the Technical Reference Manual (TRM) for the Cortex-M3 processor.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This manual is written to help system designers, system integrators, and verification
engineers who are implementing a System-on-a-Chip (SoC) device based on the
Cortex-M3 processor.
Using this manual
This manual is organized into the following chapters:
Chapter 1 Introduction
Read this chapter to learn about the components of the Cortex-M3
processor, and about the processor instruction set.
Chapter 2 Programmer’s Model
Read this chapter to learn about the Cortex-M3 register set, modes of
operation, and other information for programming the Cortex-M3
processor.
Chapter 3 System Control
Read this chapter to learn about the registers and programmer’s model for
system control.
Chapter 4 Memory Map
Read this chapter to learn about the processor memory map and
bit-banding feature.
Chapter 5 Exceptions
Read this chapter to learn about the processor exception model.
Chapter 6 Clocking and Resets
Read this chapter to learn about the processor clocking and resets.

Preface
ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. xix
Chapter 7 Power Management
Read this chapter to learn about the processor power management and
power saving.
Chapter 8 Nested Vectored Interrupt Controller
Read this chapter to learn about the processor interrupt processing and
control.
Chapter 9 Memory Protection Unit
Read this chapter to learn about the processor Memory Protection Unit.
Chapter 10 Core Debug
Read this chapter to learn about debugging and testing the processor
processor core.
Chapter 11 System Debug
Read this chapter to learn about the processor system debug components.
Chapter 12 Debug Port
Read this chapter to learn about the processor debug port, and the JTAG
Debug Port and Serial Wire Debug Port.
Chapter 13 Trace Port Interface Unit
Read this chapter to learn about the processor Trace Port Interface Unit
(TPIU).
Chapter 14 Bus Interface
Read this chapter to learn about the processor Bus Interfaces.
Chapter 15 Embedded Trace Macrocell
Read this chapter to learn about the processor Embedded Trace Macrocell
(ETM).
Chapter 16 Embedded Trace Macrocell Interface
Read this chapter to learn about the processor ETM interface.
Chapter 17 Instruction Timing
Read this chapter to learn about the processor instruction timing and
clock cycles.
Appendix A Signal Descriptions
Read this appendix for a summary of Cortex-M3 signals.

Preface
xx Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
Conventions
Conventions that this manual can use are described in:
•Typographical
•Timing diagrams
•Signals on page xxi
•Numbering on page xxi.
Typographical
The typographical conventions are:
italic Highlights important notes, introduces special terminology,
denotes internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes
signal names. Also used for terms in descriptive lists, where
appropriate.
monospace Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You
can enter the underlined text instead of the full command or option
name.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace bold Denotes language keywords when used outside example code.
< and > Angle brackets enclose replaceable terms for assembler syntax
where they appear in code or code fragments. They appear in
normal font in running text. For example:
•
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
• The Opcode_2 value selects which register is accessed.
Timing diagrams
The figure named Key to timing diagram conventions on page xxi explains the
components used in timing diagrams. Variations, when they occur, have clear labels.
You must not assume any timing information that is not explicit in the diagrams.