Elan EM78P156EL User manual

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/191
1.GENERAL DESCRIPTION
EM78P156EL is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS
technology. It is equipped with 1K*13-bits Electrical One Time Programmable Read Only Memory
(OTP-ROM). It provides a PROTECTION bit to prevent user’s code in the OTP memory from being
intruded. 6 OPTION bits are also available to meet user’s requirements.
With its OTP-ROM feature, the EM78P156EL is able to offer a convenient way of developing and verifying
user’s programs. Moreover, user can take advantage of EMC Writer to easily program his development
code.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/192
2.FEATURES
• Operating voltage range : 2.3V~5.5V
• Operating temperature range: 0°C~70°C
• Operating frequency rang (base on 2 clocks ):
* Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V.
* ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
• Low power consumption:
* Less then 1.6 mA at 5V/4MHz
* Typically 15 µA at 3V/32KHz
* Typically 1 µA during sleep mode
• 1K ×13 bits on chip ROM
• One security register to prevent intrusion of OTP memory codes
• One configuration register to accommodate user’s requirements
• 48×8 bits on chip registers (SRAM, general purpose register)
• 2 bi-directional I/O ports
• 5 level stacks for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
• Two clocks per instruction cycle
• Power down (SLEEP) mode
• Three available interruptions
* TCC overflow interrupt
* Input-port status changed interrupt (wake up from sleep mode)
* External interrupt
• Programmable free running watchdog timer
• 8 programmable pull-high pins
• 7 programmable pull-down pins
• 8 programmable open-drain pins
• 2 programmable R-option pins
• Package types:
* 18 pin DIP 300mil : EM78P156ELP
*18 pin SOP(SOIC) 300mil : EM78P156ELM

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/193
* 20 pin SSOP 209mil : EM78P156ELAS
* 20 pin SSOP 209mil : EM78P156ELKM
• 99.9% single instruction cycle commands
• The transient point of system frequency between HXT and LXT is around 400KHz

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/194
3.PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
DIP
SOP
SOIC
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
NC
P53
TCC
/RESET
VSS
9
10
NC
OSCI
OSCO
P51
P50
P67P60//INT
P61
P62
P63
P52
P66
P65
P64
VDD
SSOP
20
19
18
17
16
15
14
13
12
11
EM78P156ELP
EM78P156ELM
EM78P156ELAS
P53
TCC
/RESET
VSS
P60//INT
P61
P62
P63
P52
OSCI
OSCO
P51
P50
P67
P66
P65
P64
VDD
1
2
3
4
5
6
7
8
VSS
P53
TCC
/RESET
VSS
9
10
VDD
OSCI
OSCO
P51
P50
P67P60//INT
P61
P62
P63
P52
P66
P65
P64
VDD
SSOP
20
19
18
17
16
15
14
13
12
11
EM78P156ELKM
Fig. 1Pin Assignment
Table 1EM78P156ELP and EM78P156ELM Pin Description
Symbol Pin No. Type Function
VDD 14 -* Power supply.
OSCI 16 I* XTAL type: Crystal input terminal or external clock input pin.
* ERC type: RC oscillator input pin.
OSCO 15 I/O * XTAL type: Output terminal for crystal oscillator or external clock input pin.
* RC type: Instruction clock output.
* External clock signal input.
TCC 3I* The real time clock/co
unter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
/RESET 4I
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
P50~P53
17, 18,
1, 2 I/O * P50~P53 are bi-directional I/O pins.
* P50 and P51 can also be defined as the R-option pins.
* P50~P52 can be pulled-down by software.
P60~P67 6~13 I/O * P60~P67 are bi-directional I/O pins. * These can be pulled-high or can be open-drain by software programming.
* P60~P63 can also be pulled-down by software.
/INT 6I* External interrupt pin triggered by falling edge.
VSS 5-* Ground.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/195
Table 2EM78P156ELAS Pin Description
Symbol Pin No. Type Function
VDD 15 -* Power supply.
OSCI 17 I* XTAL type: Crystal input terminal or external clock input pin.
* ERC type: RC oscillator input pin.
OSCO 16 I/O * XTAL type: Output terminal for crystal oscillator or external clock input pin. * RC type: Instruction clock output.
* External clock signal input.
TCC 4I
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
/RESET 5I
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
P50~P53
18, 19,
2, 3I/O * P50~P53 are bi-directional I/O pins.
* P50 and P51 can also be defined as the R-option pins.
* P50~P52 can be pulled-down by software.
P60~P67 7~14I/O * P60~P67 are bi-directional I/O pins.
* These can be pulled-high or can be open-
drain by software programming.
* P60~P63 can also be pulled-down by software.
/INT 7I* External interrupt pin triggered by falling edge.
VSS 6-* Ground.
Table 3EM78P156ELKM Pin Description
Symbol Pin No. Type Function
VDD 15,16 -* Power supply.
OSCI 18 I* XTAL type: Crystal input terminal or external clock input pin.
* ERC type: RC oscillator input pin.
OSCO 17 I/O * XTAL type: Output terminal for crystal oscillator or external clock input pin.
* RC type: Instruction clock output.
* External clock signal input.
TCC 3I
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
/RESET 4I* Input pin with Schmitt trigger. If this pin remains at logic low, the controll
er
will also remain in reset condition.
P50~P53
19, 20,
1, 2I/O * P50~P53 are bi-directional I/O pins.
* P50 and P51 can also be defined as the R-option pins.
* P50~P52 can be pulled-down by software.
P60~P67 7~14I/O * P60~P67 are bi-directional I/O pins. * These can be pulled-high or can be open-
drain by software programming.
* P60~P63 can also be pulled-down by software.
/INT 7I* External interrupt pin triggered by falling edge.
VSS 5, 6 -* Ground.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/196
4.FUNCTION DESCRIPTION
IOC5
R5
P
5
0
P
5
1
P
5
2
P
5
3
IOC6
R6
AC
R3
STACK 1
STACK 2
STACK 3
STACK 4
STACK 5
P C
ROM
Instruction
Register
Instruction
Decoder
ALU
Interrupt
Control
R4
RAM
WDT Timer
Prescale
r
Oscillator/Timing
Control
WDT
Time-out
R1(TCC)
Sleep
& Wake
Control
DATA & CONTROL BUS
/INTTCC
OSCI OSCO /RESET
P
6
0
P
6
1
P
6
2
P
6
3
P
6
4
P
6
5
P
6
6
P
6
7
IOCA
Internal C
External R
oscillator
Fig. 2Function Block Diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select
Register (R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or
by the instruction cycle clock.
• Writable and readable as any other registers.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/197
• Defined by resetting PAB(CONT-3).
• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
• The contents of the prescaler counter will be cleared only when TCC register is written with a value.
3. R2 (Program Counter) & Stack
• Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in
Fig.3.
• Generating 1024×13 bits on-chip OTP ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
• R2 is set as all "0"s when under RESET condition.
• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC
to go to any location within a page.
• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus,
the subroutine entry address can be located anywhere within a page.
• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level
stack.
• "ADD R2, A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of
the PC are cleared.
• "MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the
ninth and tenth bits of the PC are cleared.
• Any instruction that writes to R2 (e.g., "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the ninth
and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256
locations of a page.
• All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would
change the contents of R2. Such instruction will need one more instruction cycle.
PC CALL
RET
RETL
RETL K
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
000
3FF
PAGE 0
A9 A8 A7 ~ A0
Fig. 3Program Counter Organization

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/198
00 R0
R1(TCC)
R2(PC)
R3(Status)
R4(RSR)
R5(Port5)
R6(Port6)
IOCA
IOCB
IOCC
IOCD
IOCE
RF
48x8
Common
Register
IOC5
IOC6
IOCF
Stack
(5 level)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
:
:
3F
R10
:
:
R3F
Fig. 4Data Memory Configuration
4. R3 (Status Register)
76543210
GP2 GP1 GP0 TPZDC C
• Bit 0 (C) Carry flag
• Bit 1 (DC) Auxiliary carry flag
• Bit 2 (Z) Zero flag.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/199
Set to "1" if the result of an arithmetic or logic operation is zero.
• Bit 3 (P) Power down bit.
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
• Bit 4 (T) Time-out bit.
Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by WDT
time-out.
• Bit5 ~7(GP0 ~ 2)General-purpose read/write bits.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select registers (address: 00~06, 0F~3F) in the indirect addressing mode.
• Bits 6~7 are not used (read only).
• The Bits 6~7 set to “1” at all time.
• Z flag of R3 will set to “1” when R4 content is equal to “3F.” When R4=R4+1, R4 content will select
as R0.
• See the configuration of the data memory in Fig. 4.
6. R5 ~ R6 (Port 5 ~ Port 6)
• R5 and R6 are I/O registers.
• Only the lower 4 bits of R5 are available.
7. RF (Interrupt Status Register)
76543210
-----EXIF ICIF TCIF
“1” means interrupt request, and “0” means no interrupt occurs.
• Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
• Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by
software.
• Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
• Bits 3 ~ 7 Not used.
• RF can be cleared by instruction but cannot be set.
• IOCF is the interrupt mask register.
• Note that the result of reading RF is the "logic AND" of RF and IOCF.
8. R10 ~ R3F
• All of these are 8-bit general-purpose registers.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1910
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding
• It cannot be addressed.
2. CONT (Control Register)
76543210
-/INT TS TE PAB PSR2 PSR1 PSR0
• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2 PSR1 PSR0 TCC Rate WDT Rate
0001:2 1:1
0011:4 1:2
0101:8 1:4
0111:16 1:8
1001:32 1:16
1011:64 1:32
1101:128 1:64
1111:256 1:128
• Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
• Bit 4 (TE) TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
• Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
• Bit 6 (/INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
• Bit 7 Not used.
• CONT register is both readable and writable.
3. IOC5 ~ IOC6 (I/O Port Control Register)
• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.
• Only the lower 4 bits of IOC5 can be defined.
• IOC5 and IOC6 registers are both readable and writable.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1911
4. IOCA (Prescaler Counter Register)
• IOCA register is readable.
• The value of IOCA is equal to the contents of Prescaler counter.
• Down counter.
5. IOCB (Pull-down Control Register)
76543210
/PD7 /PD6 /PD5 /PD4 -/PD2 /PD1 /PD0
• Bit 0 (/PD0) Control bit is used to enable the pull-down of P50 pin.
0: Enable internal pull-down
1: Disable internal pull-down
• Bit 1 (/PD1) Control bit is used to enable the pull-down of P51 pin.
• Bit 2 (/PD2) Control bit is used to enable the pull-down of P52 pin.
• Bit 3 Not used.
• Bit 4 (/PD4) Control bit is used to enable the pull-down of P60 pin.
• Bit 5 (/PD5) Control bit is used to enable the pull-down of P61 pin.
• Bit 6 (/PD6) Control bit is used to enable the pull-down of P62 pin.
• Bit 7 (/PD7) Control bit is used to enable the pull-down of P63pin.
• IOCB Register is both readable and writable.
6. IOCC (Open-drain Control Register)
76543210
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
• Bit 0 (OD0) Control bit is used to enable the open-drain of P60 pin.
0: Disable open-drain output
1: Enable open-drain output
• Bit 1 (OD1) Control bit is used to enable the open-drain of P61 pin.
• Bit 2 (OD2) Control bit is used to enable the open-drain of P62 pin.
• Bit 3(OD3)Control bit is used to enable the open-drain of P63pin.
• Bit 4 (OD4) Control bit is used to enable the open-drain of P64 pin.
• Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin.
• Bit 6 (OD6) Control bit is used to enable the open-drain of P66 pin.
• Bit 7 (OD7) Control bit is used to enable the open-drain of P67 pin.
• IOCC Register is both readable and writable.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1912
7. IOCD (Pull-high Control Register)
76543210
/PH7 /PH6 /PH5 /PH4 /PH3/PH2 /PH1 /PH0
• Bit 0 (/PH0) Control bit is used to enable the pull-high of P60 pin.
0: Enable internal pull-high
1: Disable internal pull-high
• Bit 1 (/PH1) Control bit is used to enable the pull-high of P61 pin.
• Bit 2 (/PH2) Control bit is used to enable the pull-high of P62 pin.
• Bit 3(/PH3)Control bit is used to enable the pull-high of P63pin.
• Bit 4 (/PH4) Control bit is used to enable the pull-high of P64 pin.
• Bit 5 (/PH5) Control bit is used to enable the pull-high of P65 pin.
• Bit 6 (/PH6) Control bit is used to enable the pull-high of P66 pin.
• Bit 7 (/PH7) Control bit is used to enable the pull-high of P67 pin.
• IOCD Register is both readable and writable.
8. IOCE (WDT Control Register)
76543210
WDTE EIS -ROC ----
• Bit 7 (WDTE) Control bit used to enable Watchdog timer.
0: Disable WDT.
1: Enable WDT.
WDTE is both readable and writable.
• Bit 6 (EIS) Control bit is used to define the function of P60 (/INT) pin.
0: P60, bi-directional I/O pin.
1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (bit 0 of IOC6) must be set to "1".
When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read
by way of reading Port 6 (R6). Refer to Fig. 7(a).
EIS is both readable and writable.
•Bit 4(ROC) ROC is used for the R-option.
Setting the ROC to "1" will enable the status of R-option pins (P50∼P51) that are read by the
controller. Clearing the ROC will disable the R-option function. If the R-option function is selected,
user must connect the P51 pin or/and P50 pin to VSS with a 430KΩexternal resistor (Rex). If the
Rex is connected/disconnected, the status of P50 (P51) is read as "0"/"1". Refer to Fig. 8.
• Bits 0~3,5Not used.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1913
9. IOCF (Interrupt Mask Register)
76543210
-----EXIE ICIE TCIE
• Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
• Bit 1 (ICIE) ICIF interrupt enable bit.
0: disable ICIF interrupt
1: enable ICIF interrupt
• Bit 2 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
• Bits 3~7 Not used.
• Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
• Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.Refer to Fig.
10.
• IOCF register is both readable and writable.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1914
4.3 TCC/WDT & Prescaler
An 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for either the
TCC or WDT only at any given time, and the PAB bit of the CONT register is used to determine the
prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the
instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode,
are cleared by the “WDTC” or “SLEP” instructions. Fig. 5 depicts the circuit diagram of TCC/WDT.
• R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input
(edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at
every instruction cycle (without prescaler). Referring to Fig. 5, CLK=Fosc/2 or CLK=Fosc/4 application
is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0", and
CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external clock input, TCC is
increased by 1 at every falling edge or rising edge of TCC pin.
• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when
the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a
WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any
time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms1(default).
WDT
TE
TCC
8-bit Counter
2 cycles TCC (R1)
SYNC
Pin
M
X
U
M
X
U
M
X
U
8-to-1 MUX
MUX
TS
0
PSR0~PSR2
WDT time-out
PAB TCC overflow interrupt
CLK(=Fosc/2 or Fosc/4)
PAB
(in IOCE)
WTE
Data Bus
PAB
10
1
0
1
0 1
IOCAM
X
U
Initial
value
PAB
Fig. 5Block Diagram of TCC and WDT
1<Note>: Vdd = 5V, set up time period = 16.5ms ± 5%
Vdd = 3V, set up time period = 18ms ± 5%

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1915
4.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled high
internally by software. In addition, Port 6 can also have open-drain output by software. Input status
change interrupt (or wake-up) function on Port 6. P50 ~ P52 and P60 ~ P63 pins can be pulled down by
software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6).
P50~P51 are the R-option pins enabled by setting the ROC bit in the IOCE register to 1. When the
R-option function is used, it is recommended that P50~P51 are used as output pins. When R-option is in
enable state, P50~P51 must be programmed as input pins. Under R-option mode, the current/power
consumption by Rex should be taken into the consideration to promote energy conservation.
The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for
Port 5 and Port 6 are shown in the following Figures 6, 7(a), 7(b), and Figure 8.
PCWR
PCRD
PDWR
PDRD
IOD
0
1
M
U
X
PORT Q
Q
_
D
D
Q
Q
_
CLK
P
R
C
L
CLK
P
R
C
L
NOTE: Pull-down is not shown in the figure.
Fig. 6The Circuit of I/O Port and I/O Control Register for Port 5

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1916
PCRD
IOD
PCWR
PDWR
PDRD
Bit 6 of IOCE
PORT
P60 /INT
T10
INT
M
U
X
0
1
CLK
CLK
CLK
CLK
P
P
P
P
R
R
R
R
C
L
L
L
L
C
C
C
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
_
_
_
_
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 7(a) The Circuit of I/O Port and I/O Control Register for P60 (/INT)
PCRD
PCWR
PDWR
PDRD TIN
IOD
P61~P67
PORT
0
1M
U
X
CLK
CLK
CLK
P
P
P
L
L
L
R
R
R
C
C
C
D
D
D
Q
Q
Q
Q
Q
Q
_
_
_
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1917
/SLEP
T17
T10
T11
IOCE.1
Interrupt
ENI Instruction
DISI Instruction
Interrupt
(Wake-up from SLEEP)
Next Instruction
(Wake-up from SLEEP)
CLK
CLK
CLK
Q
Q
Q
Q
Q
Q
_
_
_
D
D
D
P
P
P
L
L
L
R
R
R
C
C
C
RE.1
Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up
Table 4Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 input status changed Wake-up/Interrupt
(I) Wake-up from Port 6 Input Status Change (II) Port 6 Input Status Change Interrupt
(a) Before SLEEP 1. Read I/O Port 6 (MOV R6,R6)
1. Disable WDT1(using very carefully) 2. Execute "ENI"
2. Read I/O Port 6 (MOV R6,R6) 3. Enable interrupt (Set IOCF.1)
3. Execute "ENI" or "DISI" 4. IF Port 6 change (interrupt)
4. Enable interrupt (Set IOCF.1) →Interrupt vector (008H)
5. Execute "SLEP" instruction
(b) After Wake-up
1. IF "ENI" →Interrupt vector (008H)
2. IF "DISI" →Next instruction
1NOTE: Software disables WDT (watchdog timer) but hardware must be enabled before applying
Port 6 Change Wake-Up function. (CODE Option Register and Bit 11 (ENWDTB-) set to
“1”).

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1918
VCC
ROC
PCRD
PCWR
IOD
PDWR
PDRD
Weakly
Pull-up
PORT
Q
Q
P
R
C
L
D
CLK
Q
Q
D
P
R
C
L
M
U
X
Rex* 1
0
*TheRexis430Kohmexternalresistor
Fig. 8The Circuit of I/O Port with R-option(P50,P51)

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1919
4.5 RESET and Wake-up
1. RESET
A RESET is initiated by one of the following events-
(1) Power on reset.
(2) /RESET pin input "low", or
(3) WDT time-out (if enabled).
The device is kept in a RESET condition for a period of approx. 18ms1(one oscillator start-up timer
period) after the reset is detected. Once the RESET occurs, the following functions are performed.
Refer to Fig.9.
• The oscillator is running, or will be started.
• The Program Counter (R2) is set to all "0".
• All I/O port pins are configured as input mode (high-impedance state).
• The Watchdog timer and prescaler are cleared.
• When power is switched on, the upper 3 bits of R3 are cleared.
• The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag).
• The bits of the IOCA register are set to all "1".
• The bits of the IOCB register are set to all "1".
• The IOCC register is cleared.
• The bits of the IOCD register are set to all "1".
• Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared.
• Bits 0~2 of RF and bits 0~2 of IOCF register are cleared.
The sleep (power down) mode is asserted by executing the “SLEP” instruction. While entering sleep
mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by-
(1) External reset input on /RESET pin,
(2) WDT time-out (if enabled), or
(3) Port 6 input status changes (if enabled).
The first two cases will cause the EM78P156EL to reset. The T and P flags of R3 can be used to
determine the source of the reset (wake-up). The last case is considered the continuation of program
execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the
1NOTE: Vdd = 5V, set up time period = 16.8ms ± 5%
Vdd = 3V, set up time period = 19ms ± 5%

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1920
controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the
instruction will begin to execute from the address 008H after wake-up. If DISI is executed before
SLEP, the operation will restart from the succeeding instruction right next to SLEP after wake-up.
Only one of Cases 2 and 3 can be enabled before entering the sleep mode. That is,
[a] if Port 6 Input Status Change Interrupt is enabled before SLEP , WDT must be disabled. by
software. However, the WDT bit in the option register remains enabled. Hence, the
EM78P156EL can be awakened only by Case 1 or 3.
[b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be disabled. Hence,
the EM78P156EL can be awakened only by Case 1 or 2. Refer to the section on Interrupt.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78P156EL (Case [a] above), the
following instructions must be executed before SLEP:
MOV A, @xx000110b ; Select internal TCC clock
CONTW
CLR R1 ; Clear TCC and prescaler
MOV A, @xxxx1110b ; Select WDT prescaler
CONTW
WDTC ; Clear WDT and prescaler
MOV A, @0xxxxxxxb ; Disable WDT
IOW RE
MOV R6, R6 ; Read Port 6
MOV A, @00000x1xb ; Enable Port 6 input change interrupt
IOW RF
ENI (or DISI) ; Enable (or disable) global interrupt
SLEP ; Sleep
NOP
One problem user should be aware of, is that after waking up from the sleep mode, WDT would
enable automatically. The WDT operation (being enabled or disabled) should be handled
appropriately by software after waking up from the sleep mode.