Elan EM78P156EL User manual

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/191
1.GENERAL DESCRIPTION
EM78P156EL is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS
technology. It is equipped with 1K*13-bits Electrical One Time Programmable Read Only Memory
(OTP-ROM). It provides a PROTECTION bit to prevent user’s code in the OTP memory from being
intruded. 6 OPTION bits are also available to meet user’s requirements.
With its OTP-ROM feature, the EM78P156EL is able to offer a convenient way of developing and verifying
user’s programs. Moreover, user can take advantage of EMC Writer to easily program his development
code.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/192
2.FEATURES
• Operating voltage range : 2.3V~5.5V
• Operating temperature range: 0°C~70°C
• Operating frequency rang (base on 2 clocks ):
* Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V.
* ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
• Low power consumption:
* Less then 1.6 mA at 5V/4MHz
* Typically 15 µA at 3V/32KHz
* Typically 1 µA during sleep mode
• 1K ×13 bits on chip ROM
• One security register to prevent intrusion of OTP memory codes
• One configuration register to accommodate user’s requirements
• 48×8 bits on chip registers (SRAM, general purpose register)
• 2 bi-directional I/O ports
• 5 level stacks for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
• Two clocks per instruction cycle
• Power down (SLEEP) mode
• Three available interruptions
* TCC overflow interrupt
* Input-port status changed interrupt (wake up from sleep mode)
* External interrupt
• Programmable free running watchdog timer
• 8 programmable pull-high pins
• 7 programmable pull-down pins
• 8 programmable open-drain pins
• 2 programmable R-option pins
• Package types:
* 18 pin DIP 300mil : EM78P156ELP
*18 pin SOP(SOIC) 300mil : EM78P156ELM

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/193
* 20 pin SSOP 209mil : EM78P156ELAS
* 20 pin SSOP 209mil : EM78P156ELKM
• 99.9% single instruction cycle commands
• The transient point of system frequency between HXT and LXT is around 400KHz

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/194
3.PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
DIP
SOP
SOIC
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
NC
P53
TCC
/RESET
VSS
9
10
NC
OSCI
OSCO
P51
P50
P67P60//INT
P61
P62
P63
P52
P66
P65
P64
VDD
SSOP
20
19
18
17
16
15
14
13
12
11
EM78P156ELP
EM78P156ELM
EM78P156ELAS
P53
TCC
/RESET
VSS
P60//INT
P61
P62
P63
P52
OSCI
OSCO
P51
P50
P67
P66
P65
P64
VDD
1
2
3
4
5
6
7
8
VSS
P53
TCC
/RESET
VSS
9
10
VDD
OSCI
OSCO
P51
P50
P67P60//INT
P61
P62
P63
P52
P66
P65
P64
VDD
SSOP
20
19
18
17
16
15
14
13
12
11
EM78P156ELKM
Fig. 1Pin Assignment
Table 1EM78P156ELP and EM78P156ELM Pin Description
Symbol Pin No. Type Function
VDD 14 -* Power supply.
OSCI 16 I* XTAL type: Crystal input terminal or external clock input pin.
* ERC type: RC oscillator input pin.
OSCO 15 I/O * XTAL type: Output terminal for crystal oscillator or external clock input pin.
* RC type: Instruction clock output.
* External clock signal input.
TCC 3I* The real time clock/co
unter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
/RESET 4I
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
P50~P53
17, 18,
1, 2 I/O * P50~P53 are bi-directional I/O pins.
* P50 and P51 can also be defined as the R-option pins.
* P50~P52 can be pulled-down by software.
P60~P67 6~13 I/O * P60~P67 are bi-directional I/O pins. * These can be pulled-high or can be open-drain by software programming.
* P60~P63 can also be pulled-down by software.
/INT 6I* External interrupt pin triggered by falling edge.
VSS 5-* Ground.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/195
Table 2EM78P156ELAS Pin Description
Symbol Pin No. Type Function
VDD 15 -* Power supply.
OSCI 17 I* XTAL type: Crystal input terminal or external clock input pin.
* ERC type: RC oscillator input pin.
OSCO 16 I/O * XTAL type: Output terminal for crystal oscillator or external clock input pin. * RC type: Instruction clock output.
* External clock signal input.
TCC 4I
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
/RESET 5I
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
P50~P53
18, 19,
2, 3I/O * P50~P53 are bi-directional I/O pins.
* P50 and P51 can also be defined as the R-option pins.
* P50~P52 can be pulled-down by software.
P60~P67 7~14I/O * P60~P67 are bi-directional I/O pins.
* These can be pulled-high or can be open-
drain by software programming.
* P60~P63 can also be pulled-down by software.
/INT 7I* External interrupt pin triggered by falling edge.
VSS 6-* Ground.
Table 3EM78P156ELKM Pin Description
Symbol Pin No. Type Function
VDD 15,16 -* Power supply.
OSCI 18 I* XTAL type: Crystal input terminal or external clock input pin.
* ERC type: RC oscillator input pin.
OSCO 17 I/O * XTAL type: Output terminal for crystal oscillator or external clock input pin.
* RC type: Instruction clock output.
* External clock signal input.
TCC 3I
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
/RESET 4I* Input pin with Schmitt trigger. If this pin remains at logic low, the controll
er
will also remain in reset condition.
P50~P53
19, 20,
1, 2I/O * P50~P53 are bi-directional I/O pins.
* P50 and P51 can also be defined as the R-option pins.
* P50~P52 can be pulled-down by software.
P60~P67 7~14I/O * P60~P67 are bi-directional I/O pins. * These can be pulled-high or can be open-
drain by software programming.
* P60~P63 can also be pulled-down by software.
/INT 7I* External interrupt pin triggered by falling edge.
VSS 5, 6 -* Ground.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/196
4.FUNCTION DESCRIPTION
IOC5
R5
P
5
0
P
5
1
P
5
2
P
5
3
IOC6
R6
AC
R3
STACK 1
STACK 2
STACK 3
STACK 4
STACK 5
P C
ROM
Instruction
Register
Instruction
Decoder
ALU
Interrupt
Control
R4
RAM
WDT Timer
Prescale
r
Oscillator/Timing
Control
WDT
Time-out
R1(TCC)
Sleep
& Wake
Control
DATA & CONTROL BUS
/INTTCC
OSCI OSCO /RESET
P
6
0
P
6
1
P
6
2
P
6
3
P
6
4
P
6
5
P
6
6
P
6
7
IOCA
Internal C
External R
oscillator
Fig. 2Function Block Diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select
Register (R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or
by the instruction cycle clock.
• Writable and readable as any other registers.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/197
• Defined by resetting PAB(CONT-3).
• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
• The contents of the prescaler counter will be cleared only when TCC register is written with a value.
3. R2 (Program Counter) & Stack
• Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in
Fig.3.
• Generating 1024×13 bits on-chip OTP ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
• R2 is set as all "0"s when under RESET condition.
• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC
to go to any location within a page.
• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus,
the subroutine entry address can be located anywhere within a page.
• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level
stack.
• "ADD R2, A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of
the PC are cleared.
• "MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the
ninth and tenth bits of the PC are cleared.
• Any instruction that writes to R2 (e.g., "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the ninth
and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256
locations of a page.
• All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would
change the contents of R2. Such instruction will need one more instruction cycle.
PC CALL
RET
RETL
RETL K
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
000
3FF
PAGE 0
A9 A8 A7 ~ A0
Fig. 3Program Counter Organization

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/198
00 R0
R1(TCC)
R2(PC)
R3(Status)
R4(RSR)
R5(Port5)
R6(Port6)
IOCA
IOCB
IOCC
IOCD
IOCE
RF
48x8
Common
Register
IOC5
IOC6
IOCF
Stack
(5 level)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
:
:
3F
R10
:
:
R3F
Fig. 4Data Memory Configuration
4. R3 (Status Register)
76543210
GP2 GP1 GP0 TPZDC C
• Bit 0 (C) Carry flag
• Bit 1 (DC) Auxiliary carry flag
• Bit 2 (Z) Zero flag.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/199
Set to "1" if the result of an arithmetic or logic operation is zero.
• Bit 3 (P) Power down bit.
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
• Bit 4 (T) Time-out bit.
Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by WDT
time-out.
• Bit5 ~7(GP0 ~ 2)General-purpose read/write bits.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select registers (address: 00~06, 0F~3F) in the indirect addressing mode.
• Bits 6~7 are not used (read only).
• The Bits 6~7 set to “1” at all time.
• Z flag of R3 will set to “1” when R4 content is equal to “3F.” When R4=R4+1, R4 content will select
as R0.
• See the configuration of the data memory in Fig. 4.
6. R5 ~ R6 (Port 5 ~ Port 6)
• R5 and R6 are I/O registers.
• Only the lower 4 bits of R5 are available.
7. RF (Interrupt Status Register)
76543210
-----EXIF ICIF TCIF
“1” means interrupt request, and “0” means no interrupt occurs.
• Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
• Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by
software.
• Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
• Bits 3 ~ 7 Not used.
• RF can be cleared by instruction but cannot be set.
• IOCF is the interrupt mask register.
• Note that the result of reading RF is the "logic AND" of RF and IOCF.
8. R10 ~ R3F
• All of these are 8-bit general-purpose registers.

EM78P156EL
OTP ROM
This specification is subject to change without prior notice. 2002/04/1910
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding
• It cannot be addressed.
2. CONT (Control Register)
76543210
-/INT TS TE PAB PSR2 PSR1 PSR0
• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2 PSR1 PSR0 TCC Rate WDT Rate
0001:2 1:1
0011:4 1:2
0101:8 1:4
0111:16 1:8
1001:32 1:16
1011:64 1:32
1101:128 1:64
1111:256 1:128
• Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
• Bit 4 (TE) TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
• Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
• Bit 6 (/INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
• Bit 7 Not used.
• CONT register is both readable and writable.
3. IOC5 ~ IOC6 (I/O Port Control Register)
• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.
• Only the lower 4 bits of IOC5 can be defined.
• IOC5 and IOC6 registers are both readable and writable.