Texas Instruments DS90Ux941AS-Q1EVM User manual

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DS90Ux941AS-Q1EVM User's Guide
User's Guide
SNLU241A–December 2018–Revised April 2019
DS90Ux941AS-Q1EVM User's Guide
The DS90Ux941AS-Q1EVM (Evaluation Module) converts DSI to FPD-Link III. This kit will demonstrate
the functionality and operation of the DS90Ux941AS-Q1. The DS90Ux941AS-Q1 is a DSI to FPD-Link III
Serializer which, in conjunction with the DS90Ux940-Q1/DS90Ux948-Q1 Deserializers, takes the data
from a DSI serial stream and translates it into either single- or dual-lane FPD-Link III interface. The
DS90Ux941AS-Q1 serializes a MIPI DSI input supporting video resolutions up to 2K, WUXGA and
1080p60 with 24-bit color depth.
Contents
1 General Description ......................................................................................................... 3
2 Features....................................................................................................................... 3
3 System Requirements....................................................................................................... 4
4 Contents of the Demo Evaluation Kit ..................................................................................... 4
5 Applications Diagram........................................................................................................ 4
6 Typical Configuration........................................................................................................ 4
7 Quick Start Guide............................................................................................................ 5
8 Default Jumper Settings .................................................................................................... 6
9 Default Switch Settings ..................................................................................................... 6
10 Demo Board Connections .................................................................................................. 6
11 ALP Software Setup ....................................................................................................... 10
12 Troubleshooting ALP Software........................................................................................... 19
13 Typical Connection and Test Equipment................................................................................ 23
14 Equipment References .................................................................................................... 24
15 Cable References .......................................................................................................... 24
Appendix A EVM PCB Schematics............................................................................................ 29
Appendix B Board Layout....................................................................................................... 36
List of Figures
1 Applications Diagram........................................................................................................ 4
2 Typical Configuration........................................................................................................ 4
3 Interfacing to the EVM ...................................................................................................... 5
4 Launching ALP ............................................................................................................. 11
5 Initial ALP Screen .......................................................................................................... 11
6 Follow-Up Screen .......................................................................................................... 12
7 ALP Information Tab....................................................................................................... 13
8 ALP Pattern Generator Tab............................................................................................... 14
9 ALP Registers Tab......................................................................................................... 15
10 ALP Device ID Selected................................................................................................... 16
11 ALP Device ID Expanded................................................................................................. 17
12 ALP Scripting Tab.......................................................................................................... 18
13 USB2ANY Setup ........................................................................................................... 19
14 Remove Incorrect Profile.................................................................................................. 19
15 Add Correct Profile......................................................................................................... 20
16 Finish Setup................................................................................................................. 20
17 ALP No Devices Error ..................................................................................................... 21

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18 Windows 10, ALP USB Driver............................................................................................ 21
19 ALP in Demo Mode ........................................................................................................ 22
20 ALP Preferences Menu.................................................................................................... 22
21 Typical Test Setup for Video Application ............................................................................... 23
22 Typical Test Setup for Evaluation ....................................................................................... 23
23 Top Level Schematic ...................................................................................................... 29
24 Main Schematic ............................................................................................................ 30
25 Configuration Schematic .................................................................................................. 31
26 Schematic Connectors .................................................................................................... 32
27 Power Schematic........................................................................................................... 33
28 Audio Schematic ........................................................................................................... 34
29 USB2Any Schematic....................................................................................................... 35
30 Top Overlay................................................................................................................. 36
31 Top Solder .................................................................................................................. 37
32 Layer1 Top.................................................................................................................. 38
33 Layer 6 Bottom ............................................................................................................. 39
34 Layer6 Solder Bottom ..................................................................................................... 40
35 Layer6 Bottom Overlay.................................................................................................... 41
36 Drill Drawing ................................................................................................................ 42
37 Board Dimensions.......................................................................................................... 43
List of Tables
1 Default Board Jumper Settings ............................................................................................ 6
2 Default Board Switch Settings ............................................................................................. 6
3 Power Supply ................................................................................................................ 6
4 FPD-Link III Output Signals P1 ............................................................................................ 6
5 DSI Input Signals ............................................................................................................ 7
6 USB2ANY Connector ....................................................................................................... 7
7 I2C/CCI Interface Header................................................................................................... 7
8 GPIO/Audio Interface ....................................................................................................... 7
9 SPI/D_GPIO Interface....................................................................................................... 8
10 MODE_SEL[1:0] Settings................................................................................................... 8
11 Configuration Select (MODE_SEL0) - SW-DIP8 - S2 .................................................................. 8
12 Configuration Select (MODE_SEL1) - SW-DIP8 - S6 .................................................................. 9
13 IDx SW-DIP8 - S3 .......................................................................................................... 9
14 Bill of Materials ............................................................................................................. 25
Trademarks
All trademarks are the property of their respective owners.

www.ti.com General Description
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1 General Description
The DS90Ux941AS-Q1EVM (Evaluation Module) converts DSI to FPD-Link III. This kit will demonstrate
the functionality and operation of the DS90Ux941AS-Q1. The DS90Ux941AS-Q1 is a DSI to FPD-Link III
Serializer which, in conjunction with the DS90Ux940-Q1/DS90Ux948-Q1 Deserializers, takes the data
from a DSI serial stream and translates it into either single- or dual-lane FPD-Link III interface. The
DS90Ux941AS-Q1 serializes a MIPI DSI input supporting video resolutions up to 2K, WUXGA and
1080p60 with 24-bit color depth.
The FPD-Link III interface supports video and audio data transmission and full duplex control, including
I2C communication, over the same differential link. Consolidation of video data and control over two
differential pairs reduces the interconnect size and weight and simplifies system design. EMI is minimized
by the use of low voltage differential signaling, data scrambling, and randomization.
The demo board is not intended for EMI testing. The demo board was designed for easy accessibility to
device pins with tap points for monitoring or applying signals, additional pads for termination, and multiple
connector options.
2 Features
• Qualified for Automotive Applications
• AEC-Q100 Qualified for Automotive Applications With the Following Results:
– Device Temperature Grade 2: −40℃to +105℃Ambient Operating Temperature
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C5
• Supports Pixel Clock Frequency up to 210 MHz for 2K (2880x1080), WUXGA (1920x1200), or
1080p60 (1920x1080) Resolutions with 24-Bit Color Depth
• MIPI D-PHY / Display Serial Interface (DSI) Receiver Provides a High-Bandwidth Interface to Video
Processor or FPGA
– DSI Input Port with Up to 4 Data Lanes
– Up to 1.5 Gbps Per Lane
– ECC and CRC Generation
– Virtual Channel Capability
• Single and Dual FPD-Link III Outputs
– Single Link: Up to 105-MHz Pixel Clock
– Dual Link: Up to 210-MHz Pixel Clock

DS90Ux941AS
FPD- Link III
Deserializer
Video
Processor
Video Processor Board
Cluster, Head Unit
Dual FPD- LINK III
Display
( Video Data+ Ctrl+ PCLK)
(I2C)
(I2C)
( OpenLDI)
FPD-Link III
IDx
DOUT0+
DOUT0-
DOUT1+
DOUT1-
RIN0+
RIN0-
RIN1+
RIN1-
CLK0+/-
CLK1+/-
FPD-Link
(Open LDI)
D0+/-
D1+/-
D2+/-
D3+/-
D4+/-
D5+/-
D6+/-
D7+/-
DS90Ux941AS
Serializer
DS90Ux948
Deserializer
IDx
HS_GPIO
(SPI)
HS_GPIO
(SPI)
LVDS
Display
or Graphic
Processor
Processor
I2C I2C
CLK+/-
D0+/-
D1+/-
D2+/-
D3+/-
DSI
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3 System Requirements
To demonstrate, the following is required:
1. FPD-Link III compatible Deserializer
1. DS90Ux940-Q1, DS90Ux948-Q1 up to 1080p60
2. DSI source
3. Optional I2C controller
4. Power supply for 12 V at 1 A (required)
4 Contents of the Demo Evaluation Kit
One EVM board with the DS90Ux941A-Q1
5 Applications Diagram
Figure 1. Applications Diagram
6 Typical Configuration
Figure 2. Typical Configuration
Figure 1 and Figure 2 show the use of the chipset in a display application.

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7 Quick Start Guide
1. Configure switches S2, S3, S5 and S6 to set device’s operating modes
• S2: MODE_SEL0 = 4 (default factory setting)
• S3: IDx = 1 (address 0x18 - default factory setting)
• S6: MODE_SEL1 = 1 (default factory setting)
• S5: PDB and INTB = OFF (PDB and INTB will be pulled up to VDDIO - default factory setting)
2. Connect P1 (DOUT[1:0]+/-) to a compatible Deserializer (for example, the DS90Ux940-
Q1/DS90Ux948-Q1) using STP cable (default)
3. Connect J28 to 12V.
a. Optional power options available (see Table 3)
4. Plug in DSI source to J8
5. Connect J14 with miniUSB (5-pin_ to USB A (4-pin)) cable to PC USB port
For details of pin names and pin functions, refer to the DS90Ux941AS-Q1 data sheets.
Figure 3. Interfacing to the EVM

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8 Default Jumper Settings
Ensure that the board has the default board jumper settings:
Table 1. Default Board Jumper Settings
JUMPER JUMPER SETTINGS
J3 Connect 2 and 3
J22/J23 Connect J22 pin 2 to J23 pin 2
J24 Connect 1 and 2
J25 Connect 1 and 2
J32 Connect 1 and 2
9 Default Switch Settings
Ensure that the board has the default board switch settings:
Table 2. Default Board Switch Settings
SWITCH SWITCH SETTINGS
S1 1-3 ON
S2 4 ON, 1-3, 5-8 OFF
S3 1 ON, 2-8 OFF
S5 1-2 OFF
S6 1 ON, 2-8 OFF
10 Demo Board Connections
Table 3. Power Supply
DESIGNATOR SIGNAL DESCRIPTION
J28 +12 V 12 V ±5% Main Power
Single +12V power connector that supplies power to the entire board.
J27.1 (Optional) +1.1 V 1.1 V ±5%
Alternative to Main Power. If used, remove R103.
J30.1 (Optional) +1.8 V 1.8 V ±5%
Alternative to Main Power. If used, remove R109.
J31.1 (Optional) +3.3 V 3.3 V ±5%
Alternative to Main Power. If used, remove R113.
J23.1 (Optional) +5 V 5 V ±5%
Alternative to Main Power. If used, remove jumper to J22.
Table 4. FPD-Link III Output Signals P1
DESIGNATOR PORT SIGNAL
P1.1 FPD-Link III Port 0 DOUT0-
P1.3 DOUT0+
P1.2 FPD-Link III Port 1 DOUT1-
P1.4 DOUT1+

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Table 5. DSI Input Signals
DESIGNATOR SIGNAL DESCRIPTION
J8.33
J8.35 DSI0_D0_P DSI0_D0_N DSI0 D0 input
J8.25
J8.27 DSI0_D1_P DSI0_D1_N DSI0 D1 input
J8.17
J8.19 DSI0_CLK_P DSI0_CLK_N DSI0 CLK input
J8.9
J8.11 DSI0_D2_P DSI0_D2_N DSI0 D2 input
J8.1
J8.3 DSI0_D3_P DSI0_D3_N DSI0 D3 input
J8.34
J8.36 DSI1_D0_P DSI1_D0_N DSI1 D0 input
J8.26
J8.28 DSI1_D1_P DSI1_D1_N DSI1 D1 input
J8.18
J8.20 DSI1_CLK_P DSI1_CLK_N DSI1 CLK input
J8.10
J8.12 DSI1_D2_P DSI1_D2_N DSI1 D2 input
J8.2
J8.4 DSI1_D3_P DSI1_D3_N DSI1 D3 input
Table 6. USB2ANY Connector
DESIGNATOR DESCRIPTION
J14 mini USB 5 pin
Table 7. I2C/CCI Interface Header
DESIGNATOR SIGNAL
J11.1 VDDI2C
J11.2 SCL
J11.3 SDA
J1.4 GND
Table 8. GPIO/Audio Interface
DESIGNAT
OR SIGNAL DESCRIPTION
J12.2 I2S_DC/GPIO2 Slave Mode I2S Data Input / Remote or Local I/O
J12.4 I2S_DD/GPIO3 Slave Mode I2S Data Input / Remote or Local I/O
J12.8 I2S_DB/GPIO5_REG Slave Mode I2S Data Input / Remote or Local I/O
J12.10 I2S_DA/GPIO6_REG Slave Mode I2S Data Input / Remote or Local I/O
J12.12 I2S_WC/GPIO7_REG Slave Mode I2S Word Clock Input / Remote or Local I/O
J12.14 I2S_CLK/GPIO8_REG Slave Mode I2S Clock Input / Remote or Local I/O
J12.18 SDIN/GPIO0 Master I2S Data Input / Remote or Local I/O
J12.20 SWC/GPIO1 Master I2S Word Clock Input / Remote or Local I/O
J12.22 SCLK Master I2S Clock Input
J12.24 MCLK Master Mode I2S System Clock

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Table 9. SPI/D_GPIO Interface
DESIGNATOR SIGNAL DESCRIPTION
J12.26 D_GPIO0/MOSI I/O in FPD-Link III mode / Master
Out, Slave In
J12.28 D_GPIO1/MISO I/O in FPD-Link III mode / Master
In, Slave Out
J12.30 D_GPIO2/SPLK I/O in FPD-Link III mode / Serial
Clock
J12.32 D_GPIO3/SS I/O in FPD-Link III mode / Slave
Select
Configuration of the device may be done through the MODE_SEL[1:0]. These modes are latched into
register location during power-up:
Table 10. MODE_SEL[1:0] Settings
MODE SETTING FUNCTION
Split 0 Disable
1 Enable
DSI Lanes
00 1 DSI Lane
01 2 DSI Lanes
10 3 DSI Lanes
11 4 DSI Lanes
Non-continuous Clock Mode 0 Continuous mode
1 Non-continuous mode
COAX 0 Enable FPD-Link III for twisted pair cabling
1 Enable FPD-Link III for coaxial cabling
Disable DSI 0 Enable DSI
1 Disable DSI
(1) Only set one high
Table 11. Configuration Select (MODE_SEL0) - SW-DIP8 - S2(1)
MODE
NO.
VTARGET VOLTAGE RANGE VTARGET STRAP
VOLTAGE
SUGGESTED STRAP
RESISTORS (1% TOL) SPLIT DSI LANES
VMIN VTYP VMAX (V); V(VDD18) =
1.8 V R3(kΩ) R4(kΩ)
0 0 0 0.126 ×
V(VDD18)
0 OPEN 10.0 0 1
1 0.179 ×
V(VDD18)
0.211 ×
V(VDD18)
0.244 ×
V(VDD18) 0.380 73.2 20.0 0 2
2 0.272 ×
V(VDD18)
0.325 ×
V(VDD18)
0.364 ×
V(VDD18) 0.585 60.4 30.1 0 3
3 0.404 ×
V(VDD18)
0.441 ×
V(VDD18)
0.472 ×
V(VDD18) 0.794 51.1 40.2 0 4
4 0.526 ×
V(VDD18)
0.556 ×
V(VDD18)
0.590 ×
V(VDD18)
1.001 40.2 51.1 1 1
5 0.643 ×
V(VDD18)
0.673 ×
V(VDD18)
0.708 ×
V(VDD18) 1.211 30.1 61.9 1 2
6 0.763 ×
V(VDD18)
0.790 ×
V(VDD18)
0.825 ×
V(VDD18) 1.421 18.7 71.5 1 3
7 0.880 ×
V(VDD18) V(VDD18) V(VDD18) 1.8 10 OPEN 1 4

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(1) Only set one high
Table 12. Configuration Select (MODE_SEL1) - SW-DIP8 - S6(1)
MODE
NO.
VTARGET VOLTAGE RANGE VTARGET STRAP
VOLTAGE
SUGGESTED STRAP
RESISTORS (1% TOL) CLOCK COAX DISABLE
DSI
VMIN VTYP VMAX (V); V(VDD18)
= 1.8 V R5(kΩ) R6(kΩ)
0 0 0 0.126 ×
V(VDD18)
0 OPEN 10.0 0 0 0
1 0.179 ×
V(VDD18)
0.211 ×
V(VDD18)
0.244 ×
V(VDD18) 0.380 73.2 20.0 0 0 1
2 0.272 ×
V(VDD18)
0.325 ×
V(VDD18)
0.364 ×
V(VDD18) 0.585 60.4 30.1 0 1 0
3 0.404 ×
V(VDD18)
0.441 ×
V(VDD18)
0.472 ×
V(VDD18) 0.794 51.1 40.2 0 1 1
4 0.526 ×
V(VDD18)
0.556 ×
V(VDD18)
0.590 ×
V(VDD18)
1.001 40.2 51.1 1 0 0
5 0.643 ×
V(VDD18)
0.673 ×
V(VDD18)
0.708 ×
V(VDD18) 1.211 30.1 61.9 1 0 1
6 0.763 ×
V(VDD18)
0.790 ×
V(VDD18)
0.825 ×
V(VDD18) 1.421 18.7 71.5 1 1 0
7 0.880 ×
V(VDD18) V(VDD18) V(VDD18) 1.8 10 OPEN 1 1 1
The strapped values can be viewed and/or modified in the following register locations:
• SPLIT : Latched into DUAL_CTL(0x5B[2:0]).
• DSI LANES : Latched into BRIDGE_CTL (0x4F[3:2]).
• CLOCK : Latched into BRIDGE_CTL (0x4F[7]).
• COAX : Latched into DUAL_CTL(0x5B[7]).
• DISABLE DSI : Latched into RESET (0x01[3]).
(1) Only set one high.
Table 13. IDx SW-DIP8 - S3(1)
DESIGNATOR 7-BIT ADDRESS 8-BIT ADDRESS
S3.1 (Default) 0x0C 0x18
S3.2 0x0E 0x1C
S3.3 0x10 0x20
S3.4 0x12 0x24
S3.5 0x14 0x28
S3.6 0x16 0x2C
S3.7 0x18 0x30
S3.8 0x1A 0x34

1 3 42 A
1 2 3 4 MINI
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11 ALP Software Setup
11.1 System Requirements
Operating System: Windows 10 64-bit
USB: USB2ANY
USB2ANY Firmware Version: 2.7.0.0
11.2 Download Contents
TI Analog LaunchPAD can be downloaded from: http://www.ti.com/tool/alp.
Download and extract the “snlc048.zip” file to a temporary location that can be deleted later.
Make sure J14 on the DS90Ux941AS-Q1 is connected to a PC USB port with USB cable and power is
applied to the DS90Ux941AS-Q1 EVM.
The following installation instructions are for the Windows 10 64-bit Operating System.
11.3 Installation of the ALP Software
Execute the ALP Setup Wizard program called “ALPF_setup_v_x_x_x.exe” that was extracted to a
temporary location on the local drive of your PC.
There are 7 steps to the installation once the setup wizard is started:
1. Select the "Next" button.
2. Select “I accept the agreement” and then select the “Next” button.
3. Select the location to install the ALP software and then select the “Next” button.
4. Select the location for the start menu shortcut and then select the “Next” button.
5. There will then be a screen that allows the creation of a desktop icon. After selecting the desired
choices select the “Next” button.
6. Select the “Install” button, and the software will then be installed to the selected location.
7. Uncheck “Launch Analog LaunchPAD” and select the “Finish” button. The ALP software will start if
“Launch Analog LaunchPAD” is checked, but it will not be useful until the USB driver is installed and
board is attached.
Connect J14 USB jack of the DS90Ux941AS-Q1Q EVM board to a PC/laptop USB port using a Type A
to mini-B USB cable. Power the DS90Ux941AS-Q1Q EVB board with a 12
VDC power supply. The “Found New Hardware Wizard” will open on the PC/laptop.
11.4 Installation of the Device Profiles
There are 2 steps to add the DS90Ux941AS-Q1 profile:
1. Download the ALP-PROFILE-UPDATE, snlc062.zip, from the TI Analog LaunchPAD page:
http://www.ti.com/tool/alp.
2. Extract the files and run the executable file ALP_PROFILE_UPDATE_v02_setup_v_x_x_x.exe. The
profile will be installed to the profile folder found at: C:\Program Files (x64)\Texas Instruments\Analog
LaunchPAD vx.x.x\Profiles\.

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11.5 Start-Up - Software Description
Make sure all the software has been installed and the hardware is powered on and connected to the PC.
Execute “Analog LaunchPAD” shortcut from the start menu. The default start menu location is under All
Programs > Texas Instruments > Analog LaunchPAD vx.x.x > Analog LaunchPAD to start MainGUI.exe.
Figure 4. Launching ALP
The application should come up in the state shown in the figure below. If it does not, see Section 12,
“Troubleshooting ALP Software”.
Under the Devices tab click on “DS90Ux941AS-Q1” to select the device and open up the device profile
and its associated tabs.
Figure 5. Initial ALP Screen

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After selecting the DS90Ux941AS-Q1, the screen shown in Figure 6 should appear.
Figure 6. Follow-Up Screen

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11.6 Information Tab
The Information tab is shown in Figure 7. Note that the device revision could be different.
Figure 7. ALP Information Tab

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11.7 Pattern Generator Tab
The SER Pattern Generator tab is shown in Figure 8.
Figure 8. ALP Pattern Generator Tab

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11.8 Registers Tab
The Register tab is shown in Figure 9.
Figure 9. ALP Registers Tab

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11.9 Registers Tab - Address 0x00 Selected
Figure 10 shows the Address 0x00 selected. Note that the “Value:” box ( ) will now show the
hex value of that register.
Figure 10. ALP Device ID Selected

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11.10 Registers Tab - Address 0x00 Expanded
To expand Address 0x00, double-click the Address bar
or single-click the . The expanded Address 0x00 reveals the content for each bits. Any register
address displayed can be expanded.
Figure 11. ALP Device ID Expanded
Users can change any RW Type register ( ) by writing the hex value into the “Value:” box (
) or by clicking the checkboxes next to each register bit. A check mark indicates a "1" or R,
while a blank checkbox indicates a “0” or W. Click the “Apply” button to write to the register, and “refresh”
to see the new value of the selected (highlighted) register.
The box toggles on every mouse click.

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11.11 Scripting Tab
The Scripting tab is shown in Figure 12.
Figure 12. ALP Scripting Tab
The script window provides a full Python scripting environment to run scripts and interact with the device
in an interactive or automated fashion.
WARNING
Directly interacting with devices either through register
modifications or calling device support library functions can effect
the performance and/or functionality of the user interface and may
even crash the ALP Framework application.

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12 Troubleshooting ALP Software
12.1 ALP Loads the Incorrect Profile
If ALP opens with the incorrect profile loaded the correct profile can be loaded from the
USB2ANY/Aardvark Setup found under the tools menu.
Figure 13. USB2ANY Setup
Highlight the incorrect profile in the Defined ALP Devices list and press the remove button.
Figure 14. Remove Incorrect Profile
Find the correct profile under the Select a Daughter Board list, highlight the profile and press Add.

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Figure 15. Add Correct Profile
Select Ok and the correct profile should now be loaded.
Figure 16. Finish Setup