Toshiba TLCS-900/H1 Series Product guide

Data Book
32bit Micro controller
TLCS-900/H1 series
TMP92CH21FG
Rev0.92 11th/Jul./2002
TENTATIVE
Since this Revision 0.92 is still under working, there may be
some mistakes in it.
When you will start to design, please order the latest one.


 
--------- Contents--------
1. Outline and Device Characteristics ･･･････････････････････ 92CH21-1
2. Pin Assignment and Functions ････････････････････････ 92CH21-5
2.1 Pin Assignment ･･･････････････････････････････････ 92CH21-5
2.2 Pin name and functions ････････････････････････････ 92CH21-6
3. Oepration ･･･････････････････････････････････････････ 92CH21-12
3.1 CPU ･････････････････････････････････････････････ 92CH21-12
3.2 Memory Map ･････････････････････････････････････ 92CH21-14
3.3 Clock Function and Standby Function ････････････････ 92CH21-15
3.4 Interrupts ･････････････････････････････････････････ 92CH21-36
3.5 Function of Ports ･･････････････････････････････････ 92CH21-56
3.5.1 Port 1 ･････････････････････････････････････ 92CH21-
3.5.2 Port 2 ･････････････････････････････････････ 92CH21-
3.5.3 Port 3 ･････････････････････････････････････ 92CH21-
3.5.4 Port 4 ･････････････････････････････････････ 92CH21-
3.5.5 Port 5 ･････････････････････････････････････ 92CH21-
3.5.6 Port 6 ･････････････････････････････････････ 92CH21-
3.5.7 Port 7 ･････････････････････････････････････ 92CH21-
3.5.8 Port 8 ･･････････････････････････････････････ 92CH21-69
3.5.9 Port 9 ･････････････････････････････････････ 92CH21-
3.5.10 Port A ･････････････････････････････････････ 92CH21-
3.5.11 Port C ･････････････････････････････････････ 92CH21-
3.5.12 Port F ･････････････････････････････････････ 92CH21-
3.5.13 Port G ･････････････････････････････････････ 92CH21-
3.5.14 Port J ･････････････････････････････････････ 92CH21-
3.5.15 Port K ･････････････････････････････････････ 92CH21-
3.5.16 Port L ･････････････････････････････････････ 92CH21-
3.5.17 Port M ･････････････････････････････････････ 92CH21-
3.6 Memory Controller ･････････････････････････････････ 92CH21-93
3.7 8-bit Timers (TMRA) ･･･････････････････････････････ 92CH21-111
3.8 MMU ･････････････････････････････････････････････ 92CH21-132
3.9 Serial Channel ････････････････････････････････････ 92CH21-143
3.10 USB Controller ･･･････････････････････････････ 92CH21-177
3.11 Analog/Digital Converter ･･･････････････････････････ 92CH21-281
3.12 Watch Dog Timer ･････････････････････････････････ 92CH21-291
3.13 RTC ････････････････････････････････････････････ 92CH21-296
3.14 LCD Controller ･･･････････････････････････････････ 92CH21-310
3.15 Melody / Alarm Generator ･･････････････････････････ 92CH21-351
3.16 SDRAM Controller ････････････････････････････････ 92CH21-357
3.17 NAND-Flash Controller ･･････････････････････････ 92CH21-367

3.18 16-bit Timers (TMRB) ･････････････････････････････ 92CH21-385
3.19 Touch Screen interface･････････････････････････････ 92CH21-395
3.20 I
2
S ･･････････････････････････ 92CH21-401
3.21 BootROM ･･････････････････････････ 92CH21-408
3.22 Power Supply Backup ････････････････････ 92CH21-426
4. Electrical Charactoristics ･･･････････････････････････････ 92CH21-428
5. Table of Speial function registers (SFRs) ･････････････････ 92CH21-449
6. Package ･････････････････････････････････････  92CH21-492


DataBook Modification History
Rev/Data Page Modification item Reason
0.91
/20-Apr-2002 New release
1,3,6 Product name : JTMP92CH21 explanation New added
4,7,431 Modified Pin assignment for S0ALEL/H,S1ALEL/H
5 Deleted Port0 in Pin assignment
9 Modified attribute(I/O) for MX,MY
13 Modified Figure 3.1
71 Separated Figure 3.5.11
80 Deleted PC7F,PC6F explanation
Mistake
98 Added (Note) for Bus sizing
105 Added connection example for NOR-Flash
110 Added Note the NAND-Flash area setting
New added
114 Modified Table 3.7.2
120,121 Modified Figure 3.7.8, 3.7.9 Mistake
136 Added explanationfor MMU
141 Added example howto use MMU New added
145,146 Modified Figure 3.9.2
147 Modified Table3.9.2
149 Modified baud rate calculation formula
150 Added (Note)
151 Modified (3)Seirial clock generation circuit
157,158 Modified Figure 3.9.7, 3.9.8
167,169,171 Modified setting example
Mistake
175 Added (6)Using IrDA 115.2Kbps with USB New added
311 Modified Table 3.14.1 Mistake
313 Added (Note) New added
315,316 Added (Note)
323 Modified bit number for LD-bus Mistake
325 Added page, explanation of LD-busfor 4096 STN color
336 Modified diagram example
337 Added program example
New added
358 Added(Note3) for SDACR1
358 Modified SDACR2<SDRS1 to 0> explanation
366 Modified Figure 3.16.2(2)
374 Modified comment in Note1
387 Modified Table3.8.2
404,406 Added comment in Setting example
Mistake
408-425 Modified 3.21 Boot-ROM New added
435,436 Modified pins for shmitt-level
0.92
/10-Jul-2002
(Shown by
Blue-color)
475 Modified explanation in BnCSL-registers Mistake

UnderDevelopment TMP92CH21
92CH21 - 1
CMOS 32-bit Micro-controller
TMP92CH21FG / JTMP92CH21
1. Outline and Device Characteristics
TMP92CH21 is high-speed advanced 32-bitmicro-controller developed for controlling
equipment which processes mass data.
TMP92CH21 is a micro-controller which has a high-performance CPU (900/H1 CPU) and various
built-in I/Os.
TMP92CH21FG is housed in a 144-pin flat package. JTMP92CH21 is a chip form product.
Device characteristics are as follows:
(1) CPU : 32-bit CPU(900/H1 CPU)
•Compatible with TLCS-900/L1 instruction code
•16Mbytes of linear address space
•General-purpose register and register banks
•Micro DMA : 8channels (250ns/4bytes at fc = 40MHz, best case)
(2) Minimum instruction execution time : 50ns(at fc=40MHz)
(3) Internal memory
•Internal RAM : 16K-byte (can be used for program and data memory)
•Internal ROM : 8K-byte (used as boot-prgram )
Possible downloading user’s download-program through either USB,
UART or NAND-Flash.
(4) External memory expansion
•Expandable up to 512M bytes (shared program/data area)
•Can simultaneously support 8/16/32-bit width external data bus
…Dynamic data bus sizing
•Separate bus system
(5) Memory controller
•Chip select output : 4 channel
(6) 8-bit timers: 4 channels
(7) 16-bit timer/event counter : 1 channel
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance /
Handling Precautions.
• TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due
to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of
safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In
developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also,
please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
• The products described in this document are subject to foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for
any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any
intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
980508TBA1

UnderDevelopment TMP92CH21
92CH21 - 2
(8) General-purpose serial interface: 2 channels
•UART/Synchronous mode: 2 channels (ch.0 and 1)
•IrDA Ver.1.0(115kbps) mode selectable: 1channel (ch.0)
(9) USB(Universal Serial Bus) Controller : 1 channel
•Compliant with USB rev1.1
•Full-speed (12MHz) (LOW-spped is not supported.)
•Endpoints spec
Endpoint-0 : Control 64Bytes*1 -FIFO
Endpoint-1 : BULK(out) 64Bytes*2 -FIFO
Endpoint-2 : BULK(in) 64Bytes*2 -FIFO
Endpoint-3 : Interrupt(in) 8Bytes*1 -FIFO
•Descripter-RAM : 384Bytes
(10) I
2
S(Inter-IC Sound) interface: 1 channel
•I
2
Sbus-mode/SIO-mode selectable (Master, transmittion only)
•32-byte FIFO buffer
(11) LCD controller
•Supported up to 4096-color for TFT, 256-color,16,8,4Gray-levels and B/W for STN
•Shift register/built-in RAM LCD driver
(12) SDRAM Controller: 1 channel
•Supported 16M,64M,128M,256M even 512Mbit SDR-SDRAM
•Possible to execute instruction on SDRAM
(13) Timer for real-time clock (RTC)
(14) Key-on wake up (Interrupt key input)
(15) 10-bit A/D converter: 4 channels
(16) Touch screen interface
•Available to reduce external components
(17) Watch dog timer
(18) Melody/alarm generator
•Melody: Output of clock 4 to 5461Hz
•Alarm: Output of the 8 kinds of alarm pattern and 5 kinds of interval interrupt
(19) MMU
•Expandable up to 512M bytes (3 local area/bank method)
•Independent bank for each Program,Read-data,Write-data and LCD-display-data

UnderDevelopment TMP92CH21
92CH21 - 3
(21) Interrupts: 51 interrupts
•9 CPU interrupts: Software interrupt instruction and illegal instruction
•34 internal interrupts: Seven selectable priority levels
•7 external interrupts: Seven selectable priority levels(6-edge selectable)
(22)Input/output ports: 126 pins
(23) NAND Flash interface: 2 channel
•Available to connect directly with NAND-Flash
•ECC calculation
(24)Stand-by function
•Three Halt modes: Idle2 (programmable), Idle1, Stop
•Isolated Power supply : RTCVCC controlled by /BE-pin
•Each pin status programmable for stand-by mode
(25)Triple-clock controller
•Clock doubler (PLL) supplies 48MHz for USB, 36MHz system-clock for others
•Clock gear function: Select a High-frequency clock fc to fc/16
•RTC (fs=32.768kHz)
(26)Operating voltage:
•VCC = 3.0 V to 3.6 V (fc max = 40MHz)
•VCC = 2.7 V to 3.6 V (fc max = 27MHz)
(27) Package:
•144-pin QFP (P-LQFP144 -1616 - 0.40)
•144-pin Chip form is also available. For details, contact your local Toshiba
sales representative.

UnderDevelopment TMP92CH21
92CH21 - 4
Figure 1.1 TMP92CH21 block diagram
(PY,INT5)P9
7
IX
IY
IZ
SP
LH ED CB AW
XSP
XIZ
XIY
XI
X
XHL
XDE
XB
C
XW
A
900/H1 CPU
FS
R
32bit
P
C
16KB RAM
SERIAL I/O
SIO0
(
RXD0,RXD1
)
P
F
1
(TXD0,TXD1
)
PF
0
(S
CLK0
,/SCLK0)
PF2
DVSS
[
3
]
DVC
C
[
3
],
RTCVC
C
/
RESE
T
A
M0
A
M1
10-bit 4ch
AD
Converter
VREFH,VREF
L
A
VCC,AVS
S
A
N3/MY/ADTRG
(
PG3
)
A
N2/MX(PG2
)
PG0 to PG1
(
AN0 to AN1
)
8BIT TIMER
(T
IMERA0
)
8BIT TIMER
(T
IMERA1
)
(TA1OUT,INT0)
P
C
0
8BIT TIMER
(T
IMERA2
)
8BIT TIME
R
(T
IMERA3
)
(
T
A
3OUT
,
INT1
)P
C1
16BIT TIMER
(TIMERB0)
WATCH-DOG TIMER
X1
H
-
OS
C
X2
Clock Gear
INTERRUPT
Controller
MMU
(INT3
)
P
C
3
(
TB0OUT0,INT2
)
P
C2
X
T
1
L
-
OS
C
X
T
2
(PX,INT4)P9
6
SERIAL I/O
SIO1
Touch Screen
I/F(TSI)
LCD
Controller
(LC
P
0)
P
K
0
(LLP)
P
K1
(
LF
R
)P
K
2
(LCD)
P
K
3
PL0 to PL
7
(
LD0 to LD7
)
USB
Controller
D
+
D
-
(LGOE0)P9
3
(LGOE1)P9
4
(LGOE2)P9
5
SDRAM
Controller
(
SDCLK
)
PF
7
(
/SDRA
S
,/SRLLB
)
PJ
0
(
/SDCA
S
,/SRLUB
)
PJ1
(
/SDW
E
,/SRW
R
)
PJ
2
(
SDLLDQM
)
PJ
3
(
SDLUDQM
)
PJ
4
(
SDCKE
)
PJ
7
PORT8
P84(/CSZB,/WRUL,/ND0CE)
P80
(
/CS0
)
P82
(
/CS2
,
/CSZA
,
/SDCS
)
P81
(
CS1
,
/SDCS
)
P83(/CS3)
P85(/CSZC,/WRUU,/ND1CE)
PORT0
(D0 to D7
)
PORT5
PORT1
PORT2
PORT3
PORT4
PORT6
P10 to P17
(
D8 to D15
)
P20 to P27
(
D16 to D23
,
KO0 to KO7
)
P30 to P37
(
D24 to D31
)
P40 to P47
(
A0 to A7
)
P50 to P57
(
A8 to A15
)
P60 to P67
(
A16 to A23
)
PORT7
P70(/RD
)
P71(/WRLL,/NDRE
)
P72(/WRLU,/NDWE
)
P30,3
3
P31,3
4
P32,3
5
RTC
MELODY/
A
LARM
-
OU
T
KEY-BOARD
I/F
PA0 to PA7(KI0 to KI7,
LD8 to LD11)
PM2(/ALARM,/MLDALM
)
PM1(MLDALM
)
8KB Masked-ROM
(Boot program)
I
2
S
PLL
NAND-FLASH
I/F(2ch)
(
I2
S
D
O,
RXD
0
)
P
9
1
(I2SCKO,TX
D
0
)
P
9
0
(I2SWS,
S
CLK0,/CTS0
)
P
92
(NDALE,SDULDQM)PJ
5
(NDCLE,SDUUDQM)PJ
6
/BE
P73(EA24)
P74 (EA25)
P75 (R/W,NDR/B
)
P76 (/WAIT
)
P86(/CSZD,/SRULB)
P87(/CSZE,/SRUUB)
PC7(/CSZF,LCP1)
PC6(KO8,LDIV
)

TMP92CH21
92CH21 -5
PL6,LD6
PG3,AN3,/ADTRG,M
Y
PJ7,SDCKE
PA0,KI0
AVSS
TMP92CH21FG
QFP144
TOPVIEW
1
5
10
15
20
25
30
40
45
50
55
60
75
80
85
90
95
110
115
120 125
PA1,KI1
PA2,KI2
PA3,KI3,LD8
PA4,KI4,LD9
PA5,KI5,LD10
PA6,KI6,LD11
PA7,KI7
PK0,LCP0
PK1,LLP
PK2,LFR
PK3,LBCD
PM2,/ALARM,/MLDALM
PL0,LD0
PL1,LD1
PL2,LD2
PL3,LD3
PL5,LD5
PL7,LD7
P56,A14
P55,A13
P54,A12
P53,A11
P52,A10
P51,A9
P50,A8
P47,A7
P44,A4
P45,A5
P43,A3
P42,A2
P41,A1
P40,A0
P37,D31
P36,D30
P35,D29
DVSS3
P34,D28
P33,D27
P32,D26
P31,D25,
P30,D24
P27,D23
P26,D22
P13,D11
P12,D10
P11,D9
P10,D8
D7 D6 D5 D4
X2
DVSS1
X1
/BE
RTCVCC
PF7,SDCLK
PF2,SCLK0,/CTS0,SCLK1,/CTS1
PF0,TXD0,TXD1 P76,/WAIT
VREFH
P84,/CSZB,/WRUL,/ND0CE
P83,/CS3
P82,/CS2,/CSZA,/SDCS P81,/CS1,/SDCS P80,/CS0 P75,RW,NDR/B P74,EA25 P73,EA24 P72,/WRLU,/NDWE P71,/WRLL,/NDRE P70,/RD
35
65
70
100
105
130 135
140
AM0 AM1
/RESET
P90,TXD0,I2SCKO
PC3,INT3
D0 D1 D2 PF1,RXD0,RXD1D3
P46,A6
PC7,/CSZF,LCP1
PG0,AN0
PG2,AN2,M
X
PG1,AN1
VREFL
AVCC
PJ6,SDUUDQM,NDCLE PJ5,SDULDQM,NDALE PJ4,SDLUDQM PJ3,SDLLDQM
PJ2,/SDWE,/SRWR PJ1,/SDCAS,/SRLUB PJ0,/SDRAS,/SRLLB
P87,/CSZE,/SRUUB P86,/CSZD,/SRULB
P85,/CSZC,/WRUU,/ND1CE
PL4,LD4
DVCC1
DVSS2
DVCC2
P14,D12 P15,D13 P16,D14 P17,D15 P20,D16 P21,D17 P22,D18 P23,D19
P24,D20
P25,D21
P57,A15
P60,A16
P61,A17
P62,A18
P63,A19
DVCC3
P64,A20
P65,A21
P66,A22
P67,A23
P96,PX,INT4
P97,PY,INT5
P91,RXD0,I2SDO
P92,SCLK0,/CTS0,I2SWS
P93,LGOE0
P94,LGOE1
P95,LGOE2
PC0,TA1OUT,INT0
PC1,TA3OUT,INT1
PC2,TB0OUT0,INT2
PM1,MLDALM
PC6,KO8,LDIV
XT1
XT2
D+
D-
2. Pin Assignment and Functions
The assignment of input/output pins for the TMP92CH21FG, their names and functions are
as follows:
2.1 Pin Assignment
Figure2.1.1 Pin assignment diagram (144-pin QFP)

TMP92CH21
92CH21 -6
2.2 PAD Assignment
(Chipsize 5.98mm ×6.42mm)
Table2.2.1 Pad assignment diagram (144-pin chip) Unit: μm
PIN
No Name X point Y point PIN No Name X point Y point PIN No Name X point Y point
1
VREFL -2852 2671 49 DVSS2 -488 -3072 97 P55 2848 815
2
VREFH -2852 2546 50 DVCC2 -338 -3072 98 P56 2848 941
3
PG0 -2852 2421
51 D0 -200 -3072 99 P57 2848 1066
4
PG1 -2852 2296 52 D1 -75 -3072 100 P60 2848 1191
5
PG2 -2852 2171 53 D2 49 -3072 101 P61 2848 1316
6
PG3 -2852 2045
54 D3 174 -3072 102 P62 2848 1441
7 P96 -2852 1920 55 D4 300 -3072 103 P63 2848 1566
8 P97 -2852 1795 56 D5 425 -3072 104 DVCC3 2848 1692
9 PA3 -2852 1270 57 D6 550 -3072 105 P64 2848 1823
10 PA4 -2852 1145 58 D7 675 -3072 106 P65 2848 1974
11 PA5 -2852 1020 59 P10 800 -3072 107 P66 2848 2130
12 PA6 -2852 895 60 P11 925 -3072 108 P67 2848 2292
13 PA7 -2852 769 61 P12 1050 -3072 109 P70 2460 3065
14 P90 -2852 644 62 P13 1176 -3072 110 P71 2295 3065
15 P91 -2852 519 63 P14 1301 -3072 111 P72 2127 3065
16 P92 -2852 394 64 P15 1426 -3072 112 P73 1964 3065
17 P93 -2852 269 65 P16 1551 -3072 113 P74 1807 3065
18 P94 -2852 144 66 P17 1676 -3072 114 P75 1654 3065
19 P95 -2852 18 67 P20 1801 -3072 115 P76 1506 3065
20 PC2 -2852 -106 68 P21 1927 -3072 116 P80 1361 3065
21 PL0 -2852 -231 69 P22 2052 -3072 117 PC6 1226 3065
22 PL1 -2852 -356 70 P23 2177 -3072 118 P81 1101 3065
23 PL2 -2852 -481 71 P24 2303 -3072 119 P82 976 3065
24 PL3 -2852 -606 72 P25 2460 -3072 120 P83 851 3065
25 PL4 -2852 -732 73 P26 2848 -2279 121 P84 726 3065
26 PL5 -2852 -857 74 P27 2848 -2138 122 P85 600 3065
27 PL6 -2852 -982 75 P30 2848 -1982 123 P86 475 3065
28 PL7 -2852 -1107 76 P31 2848 -1831 124 P87 350 3065
29 PK0 -2852 -1232 77 P32 2848 -1687 125 PC7 225 3065
30 PK1 -2852 -1357 78 P33 2848 -1562 126 PF0 100 3065
31 PK2 -2852 -1482 79 P34 2848 -1437 127 PF1 -24 3065
32 PK3 -2852 -1608 80 P35 2848 -1311 128 PF2 -150 3065
33 PM2 -2852 -1892 81 DVSS3 2848 -1186 129 PC0 -275 3065
34 PM1 -2852 -2017 82 P36 2848 -1061 130 PC1 -400 3065
35 XT1 -2852 -2142 83 P37 2848 -936 131 PF7 -525 3065
36 XT2 -2852 -2444 84 P40 2848 -811 132 PJ0 -650 3065
37 RTCVCC -2465 -3072 85 P41 2848 -686 133 PJ1 -775 3065
38 /BE -2339 -3072 86 P42 2848 -560 134 PJ2 -901 3065
39 D+ -2062 -3072 87 P43 2848 -435 135 PJ3 -1026 3065
40 D- -1875 -3072 88 P44 2848 -310 136 PJ4 -1151 3065
41 DVCC1 -1598 -3072 89 P45 2848 -185 137 PJ5 -1276 3065
42 X1 -1472 -3072 90 P46 2848 -60 138 PJ6 -1401 3065
43 DVSS1 -1347 -3072 91 P47 2848 65 139 PJ7 -1526 3065
44 X2 -1126 -3072 92 P50 2848 190 140 PA0 -1652 3065
45 AM0 -1001 -3072 93 P51 2848 315 141 PA1 -1777 3065
46 AM1 -876 -3072 94 P52 2848 440 142 PA2 -1902 3065
47 /RESET -750 -3072 95 P53 2848 565 143 AVSS -2275 3065
48 PC3 -625 -3072 96 P54 2848 690 144 AVCC -2400 3065

TMP92CH21
92CH21 -7
2.3 Pin names and functions
The following table shows the names andfunctions of the input/outputpins
Table2.3.1 Pin names and functions (1/5)
Pin Name Number of
pins I/O Function
D0 to D7 8 I/O Data:Data bus 0 to 7
P10 toP17
D8 to D15 8 I/O
I/O Port 1: I/O portInput or output specifiable in units of bits Data: Data bus 8to 15
P20 toP27
D16 to D23
KO0toKO7 8 I/O
I/O
Output
Port 2: I/O port Input or output specifiable in units of bits
Data: Data bus 16to 23
Key Output 0 to 7 : pins used of Key-scan strobe (Open drain-output programmable)
P30
D24 1 I/O I/O Port 30: I/O port Data24: Data bus 24
P31
D25 1 I/O I/O Port 31: I/O port Data25: Data bus 25
P32
D26 1 I/O
I/O Port 32: I/O port Data26: Data bus 26
P33
D27 1 I/O
I/O Port 33: I/O port Data27: Data bus 27
P34
D28 1 I/O
I/O Port 34: I/O port Data28: Data bus 28
P35
D29 1 I/O I/O Port 35: I/O port Data29: Data bus 29
P36 toP37
D30 to D31 2 I/O I/O Port 3: I/O portInput or output specifiable in units of bits Data: Data bus 30o 31
P40 toP47
A0toA7 8 I/O
Output Port 4: I/O portInput or output specifiable in units of bits Address: Address bus 0to 7
P50 toP57
A8toA15 8 I/O Output Port 5: I/O portInput or output specifiable in units of bits Address: Address bus 8to 15
P60 toP67
A16toA23 8 I/O
Output Port 6: I/O portInput or output specifiable in units of bits Address: Address bus 16to 23
P70
/RD 1 Output Output Port70: Output port Read: Outputs strobe signal to read external memory
P71
/WRLL
/NDRE 1 I/O
Output
Output
Port 71: I/O port
Write: Outputstrobe signalfor writing data on pins D0 to D7
NAND-Flash read: Outputsstrobe signalto read external NAND-Flash
P72
/WRLU
/NDWE 1 I/O
Output
Output
Port 72: I/O port
Write: Outputstrobe signalfor writing data on pins D8 to D15
Write Enablefor NAND-Flash
P73
EA24 1 I/O
Output Port 73: Output port Extended Address 24
P74
EA25 1 I/O Output Port 74: Output port Extended Address 25
P75
R/W
NDR/B 1 Output
Output
Input
Port 75: Output port
Read/Write: 1 representsRead or Dummycycle; 0 represents write cycle
NAND-Flash Ready(1)/Busy(0) input
P76
/WAIT 1 I/O
Input Port 76: I/O port Wait: Signal used to request CPU bus wait

TMP92CH21
92CH21 -8
Table2.3.1Pin namesand functions (2/5)
Pin Name Number of
pins I/O Function
P80
/CS0 1 Output
Output Port80:Output port Chip select 0: Outputs “Low” when address is within specified address area
P81
/CS1
/SDCS 1 Output
Output
Output
Port81:Output port
Chip select 1: Outputs “Low” when address is within specified address area
Chip Select for SDRAM:Outputs “0” when address is within SDRAM -addressarea
P82
/CS2
/CSZA
/SDCS
1
Output
Output
Output
Output
Port82:Output port
Chip select 2: Outputs “Low” when address is within specified address area
Expand Chip Select: ZA: outputs “0” when address is within specified address area
Chip Select for SDRAM:Outputs “0” when address is within SDRAM -addressarea
P83
/CS3 1 Output Output Port83:Output port Chip select 3: Outputs “Low” when address is within specified address area
P84
/WRUL
/CSZB
/ND0CE
1
Output
Output
Output
Output
Port84:Output port
Write: Outputstrobe signalfor writing data on pins D16 to D23
Expand Chip Select: ZB: outputs “0” when address is within specified address area
Chip select for NAND-Flash0: Outputs “0” when NAND-Flash-0 is accessed
P85
/WRUU
/CSZC
/ND1CE
1
Output
Output
Output
Output
Port85: Output port
Write: Outputstrobe signalfor writing data on pins D24 to D31
Expand Chip Select: ZC: outputs “0” when address is within specified address area
Chip select for NAND-Flash1: Outputs “0” when NAND-Flash-1 is accessed
P86
/CSZD
/SRULB 1 Output
Output
Output
Port86: Output port
Expand Chip Select: ZD: outputs “0” when address is within specified address area
Data enable for SRAM on pins D16 toD23
P87
/CSZE
/SRUUB 1 Output
Output
Output
Port87: Output port
Expand Chip Select: ZE: outputs “0” when address is within specified address area
Data enable for SRAM on pins D24 toD31
P90
TXD0
I2SCKO 1 I/O
Output
Output
Port90: I/O port
Serial 0 send data: Open drain-output programmable
I2S Clock Output
P91
RXD0
I2SDO 1 I/O
Input
Output
Port91: I/O port
Serial 0 receive data
I2SData Output
P92
SCLK0
/CTS0
I2SWS
1
I/O
I/O
Input
Output
Port92: I/O port
Serial 0 clock I/O
Serial 0 data send enable (Clear to Send)
I2S Word Select Output
P93
LGOE0 1 I/O Output Port93: I/O port Output Enable-0 for external TFT-LCDDriver
P94
LGOE1 1 I/O
Output Port94: I/O port Output Enable-1 for external TFT-LCDDriver
P95
LGOE2 1 I/O Output Port95: Outputport Output Enable-2 for external TFT-LCDDriver
P96
INT4
PX
1 I/O
Input
Output
Port 96: Input port
Interrupt request pin4:Interrupt request with programmable rising/falling edge
X-Plus : Pin connectted to X+ for Touch Screen Panel
P97
INT5
PY
1 I/O
Input
Output
Port 97: Input port
Interrupt request pin5:Interrupt request with programmable rising/falling edge
Y-Plus : Pin connectted to Y+ for Touch Screen Panel
PA0to PA2
KI0to KI2 3 Input Input Port: A0 toA2 port: Pin used toinput ports Key input 0 to 2: Pin used of Key on wake-up 0 to 2 (shummit input, with pull-up register)
PA3to PA6
KI3to KI6
LD8 to LD11 4 Input
Input
Output
Port: A3to A6port: Pinused toinputports
Key input 3 to 6: Pin used of Key on wake-up 3 to 6 (shummit input, with pull-up register)
Data Bus for LCD-driver
PA7
KI7 1 Input Input Port: A7 port: Pin used to input ports Key input 7: Pin used of Keyon wake-up 7 (shummit input, with pull-up register)

TMP92CH21
92CH21 -9
Table2.3.1Pin namesand functions (3/5)
Pin Name Number of
pins I/O Function
PC0
INT0
TA1OUT 1 I/O
Input
Output
PortC0: I/O port
Interrupt request pin0 : Interrupt request pin with programmable level / rising /falling edge
8bit timer 1 output: Timer 1 output
PC1
INT1
TA3OUT 1 I/O
Input
Output
PortC1: I/O port
Interrupt request pin1 : Interrupt request pin with programmable rising/falling edge
8bit timer 3 output: Timer 3 output
PC2
INT2
TB0OUT0 1 I/O
Input
Output
PortC2 : I/Oport
Interrupt request pin2: Interrupt requestpin with programmable rising /falling edge
Timer B0 output
PC3
INT3 1 I/O
Input PortC3: I/O port Interrupt request pin3 : Interrupt request pin with programmable rising/falling edge
PC6
KO8
LDIV 1 I/O
Output
Output
PortC6 : I/Oport
Key Output 8 : pin used of Key-scan strobe (Open drain-output programmable)
Data Invert enablefor external TFT-LCD Driver
PC7
/CSZF
LCP1 1 I/O
Output
Output
PortC7 : I/Oport
Expand Chip Select: ZF: outputs “0” when address is within specified address area
Shift-clock-1for externalTFT-LCD Driver
PF0
TXD0
TXD1 1 I/O
Output
Output
PortF0: I/O port
Serial 0 send data: Open drain-output programmable
Serial 1 send data: Open drain-output programmable
PF1
RXD0
RXD1 1 I/O
Input
Input
PortF1: I/O port
Serial 0 receive data
Serial 1 receive data
PF2
SCLK0
/CTS0
SCLK1
/CTS1
1
I/O
I/O
Input
I/O
Input
PortF2: I/O port
Serial 0 clock I/O
Serial 0 data send enable (Clear to Send)
Serial 1 clock I/O
Serial 1 data send enable (Clear to Send)
PF7
SDCLK 1 Output Output PortF7: Outputport Clock for SDRAM
PG0 toPG1
AN0toAN1 2 Input
Input Port G0 to G1port: Pin used to input ports Analog input 0 to 1: Pin used to Input toA/D conveter
PG2
AN2
MX 1 Input
Input
Output
Port G2 port: Pin used to input ports
Analog input 2: Pin usedto Input to A/D conveter
X-Minus: Pinconnectted to X- for Touch Screen Panel
PG3
AN3
MY
/ADTRG
1
Input
Input
Output
Intput
Port G3 port: Pin used to input ports
Analog input 3: Pin usedto Input to A/D conveter
Y-Minus: Pin connectted to Y- for Touch Screen Panel
A/D trigger: Signal used to request A/D start

TMP92CH21
92CH21 -10
Table2.3.1 Pin names and functions (4/5)
Pin Name Number of
pins I/O Function
PJ0
/SDRAS
/SRLLB 1 Output
Output
Output
PortJ0: Output port
RowAddress StorobeforSDRAM
Data enable for SRAM on pins D0 to D7
PJ1
/SDCAS
/SRLUB 1 Output
Output
Output
PortJ1: Output port
Column Address Storobe forSDRAM
Data enable for SRAM on pins D8to D15
PJ2
/SDWE
/SRWR 1 Output
Output
Output
PortJ2: Output port
WriteEnable for SDRAM
Write for SRAM: strobe signal for writing data
PJ3
SDLLDQM 1 Output
Output PortJ3: Outputport Data enable for SDRAM on pins D0 toD7
PJ4
SDLUDQM 1 Output Output PortJ4: Output port Data enable for SDRAM on pins D8 toD15
PJ5
SDULDQM
NDALE 1 Output
Output
Output
PortJ5: I/O port
Data enable for SDRAM on pins D16 to D23
Address LatchEnablefor NAND-Flash
PJ6
SDUUDQM
NDCLE 1 Output
Output
Output
PortJ6: I/O port
Data enable for SDRAM on pins D24 to D31
Command Latch Enablefor NAND-Flash
PJ7
SDCKE 1 Output Output PortJ7: Outputport Clock Enable for SDRAM
PK0
LCP0 1 Output Output PortK0: Output port LCD driver output pin
PK1
LLP 1 Output
Output PortK1: Output port LCD driver output pin
PK2
LFR 1 Output Output PortK2: Output port LCD driver output pin
PK3
LBCD 1 Output
Output PortK3: Output port LCD driver output pin
PL0 toPL3
LD0 to LD3 4 Output Output PortL0 to L7: Output port Data Bus for LCD-driver
PL4 toPL7
LD4 to LD7 4 I/O Output Port L0 to L7: I/O port Data Bus for LCD-driver
/BE 1 Input Back-up enable
PM1
MLDALM 1 Output
Output PortM1: Output port Melody / Alarm output pin
PM2
/ALARM
/MLDALM 1 Output
Output
Output
PortM2: Output port
RTC alarm output pin
Melody / Alarm output pin (inverted)

TMP92CH21
92CH21 -11
Table2.3.1 Pin names and functions (5/5)
Pin Name Number of
pins I/O Function
D+, D- 2 I/O USB-data Connecting pin
AM0,AM1 2 in
Operation mode:
Fix to AM1=”0”,AM0=”1” for 16-bit external busstarting
Fix to AM1=”1”,AM0=”0” for 32-bit external busstarting
Fix to AM1=”1”,AM0=”1” for BOOT(32-bit internal-MROM ) starting
X1/X2 2 I/O High-frequency oscillator connection pins
XT1/XT2 2 I/O Low-frequencyoscillatorconnection pins
/RESET 1 in Reset: initializes TMP92CH21 (With pull-up resistor)
VREFH 1 in Pin for reference voltage input to ADconverter (H)
VREFL 1 in Pin for reference voltage input to ADconverter (L)
AVCC 1 - Power supply pin forAD converter
AVSS 1 - GND pin for ADconverter (0V)
DVCC 3 - Power supplypins (AllVcc pins shouldbe connected with the power Supply pin)
DVSS 3 - GND pins (0 V) (All pins shuold beconnected with GND(0V)
RTCVCC 1 - Power supply pin for RTC, low-frequency oscillator and portM

TMP92CH21
92CH21 - 12
3. OPERATION
This section describes the basic components, functions and operation of the TMP92CH21.
3.1 CPU
The TMP92CH21 contains an advanced high-speed 32-bit CPU(900/H1 CPU)
3.1.1 CPU Outline
900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1 CPU has
expanded 32-bit internal data bus to process Instructions more quickly.
Outline of 900/H1 CPU are as follows:
Parameter 900/H1 CPU
Width of CPU Address Bus 24-bit
Width of CPU Data Bus 32-bit
Internal Operating Frequency max.20MHz (at fc=40MHz)
Minimum Bus Cycle 1-clock access(50ns)
Internal RAM 32-bit 1-clock access
Internal Boot-ROM 32-bit 2-clock access
Internal I/O 8/16-bit 2-clock access
8/16-bit 5 to 6-clock access
External Device 8/16/32-bit 2-clock access
(can insert some waits)
Minimum Instruction
Execution Cycle
1-clock(50ns)
Conditional Jump 2-clock(100ns)
Instruction Queue Buffer 12-byte
Instruction Set Compatible with
TLCS-900/L1,TLCS-900/H2
(LDX instruction is deleted)
CPU mode Only maximum mode
Micro DMA 8-channel
3.1.2 Reset Operation
When resetting the TMP92CH21 microcontroller, ensure that the power supply voltage is
within the operating voltage range, and that the internal high-frequency oscillator has stabilized.
Then hold the /RESET input Low for at least 20 system clocks(16µs at 40MHz).
At reset, since the clock doubler(PLL) is bypassed and clock-gear is set to 1/16,
system clock operates at 1.25MHz(fc=40MHz).
When the Reset has been accepted, the CPU performs the following:
• Sets the Program Counter (PC) as follows in accordance with the Reset Vector stored
at address FFFF00H~FFFF02H:
PC<0~7> ←data in location FFFF00H
PC<8~15> ←data in location FFFF01H
PC<16~23> ←data in location FFFF02H
• Sets the Stack Pointer (XSP) to 00000000H.
• Sets bits <IFF0 to IFF2> of the Status Register (SR) to 111 (thereby setting the Interrupt
Level Mask Register to level 7).
• Clears bits <RFP0 to RFP1> of the Status Register to 00 (thereby selecting Register

TMP92CH21
92CH21 - 13
Bank 0).
When the Reset is released, the CPU starts executing instructions according to the
Program Counter settings. CPU internal registers not mentioned above do not change
when the Reset is released.
When the Reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
• Initializes the internal I/O registers as table of “Special Function Register” in Section 5.
• Sets the port pins, including the pins that also act as internal I/O, to General-Purpose
Input or Output Port Mode.
Internal reset is released as soon as external reset is released.
The operation of memory controller cannot be insured until power supply becomes stable
after power-on reset. The external RAM data provided before turning on the TMP92CH21 may
be spoiled because the control signals are unstable until power supply becomes stable after
power on reset.
High frequency oscillation warming up time
+ 20 system clock
VCC
(
3.3V
)
/RESET
Min.0s
Figure 3.1 Power on Reset Timing Example
3.1.3 Setting of AM0 and AM1
Set AM1 and AM0 pins like Table3.1 according to system usage.
Table 3.1 Operation Mode Setup Table
Mode Setup input pin
Operation Mode /RESET AM1 AM0
16-bit external bus starting
0 1
32-bit external bus starting
1 0
BOOT(32-bit internal-MROM ) starting
1 1

TMP92CH21
92CH21 - 14
3.2 Memory Map
Figure 3.2 is a memory map of the TMP92CH21.
000000H
002000H
16Mbyte area
(R)
(
−R)
(R+)
(R
+R8/16)
(R
+d8/16)
(nnn)
Direct area (n)
64Kbyte area
(nn)
Internal I/O
(8 KByte)
Internal RAM
(16 KByte)
006000H
010000H
( =Internal area)
FFFF00H
FFFFFFH Vector table (256 Byte)
External memory
000100H
External memory
001D00H
Provisional Emulator Control Area
(64K Byte)
F00000H
F10000H
BOOT(Internal MROM)
(8 KByte)
3FE000H
400000H
Figure 3.2 Memory Map
(
Note2
)
(
Note3
)
Note1: BOOT-prgram(Internal MROM) is mapped only for BOOT-mode. At another starting mode,
its area(3FE000H to 3FFFFFH) is mapped to external-memory.
Note2: Provisional emulator control area is for an emulator, it is mapped F00000H to F0FFFFH
after reset.
Note3: Don’t use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved for an emulator.
Note4: On emulator /WR signal and /RD signal are asserted, when provisional emulator control
area is accessed.
Be carefull to use external memory.
(
Note1
)

TMP92CH21
92CH21 - 15
3.3 Clock Function and Standby Function
TMP92CH21 contains (1)clock gear, (2)clock doubler(PLL), (3) standby controller
and (4) noise-reducing circuit. They are used for low-power, low-noise systems.
This chapter is organized as follows:
3.3.1 Block diagram of system clock
3.3.2 SFRs
3.3.3 System clock controller
3.3.4 Prescaler clock controller
3.3.5 Noise-reducing circuit
3.3.7 Standby controller

TMP92CH21
92CH21 - 16
The clock operating modes are as follows: (a) Single Clock Mode (X1, X2 pins only),
(b) Dual Clock Mode (X1, X2, XT1 and XT2 pins) and (c) Triple Clock Mode (X1, X2, XT1 and XT2
pins and PLL). Figure 3.3.1 shows a transition figure.
Reset
(fOSCH/32)
release Reset
instruction
interrupt STOP mode
(Stops all circuits)
NORMAL mode
(f
OSCH
/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
(a) Single clock mode transition figure
(b) Dual clock mode transition figure
SLOW mode
(fs/2)
Reset
(fOSCH/32)
release Reset
NORMAL mode
(f
OSCH
/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
instruction
instruction
interrupt
interrupt
instruction
instruction
interrupt
interrupt
instruction
instruction
interrupt
interrupt
instruction
interrupt STOP mode
(Stops all circuits)
instruction
interrupt STOP mode
(Stops all circuits)
Using PLL
*NOTE
Reset
(fOSCH/32)
release Reset
NORMAL mode
(f
OSCH
/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
STOP mode
(Stops all circuits)
SLOW mode
(fs/2)
NORMAL mode
(4 ×fOSCH/gear
value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate oscillator and PLL)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
(c) Triple clock mode transition Figure
instruction
instruction
interrupt
interrupt
instruction instruction
instruction interrupt
*NOTE
instruction
*NOTE)
・ It’s prohibited to control PLL in SLOW mode when shifting from SLOW mode to NORMAL mode with
use of PLL.（PLL Start up/Stop/Change Write to PLLCR0<PLLON>,PLLCR1<FCSEL> resister）
・ If you shift from NORMAL mode with use of PLL to NORMAL mode, execute following setting in the
same order.
1) Change CPU clock(PLLCR0<FCSEL> <- “0” 2)Stop PLL circuit(PLLCR1<PLLON><-“0”)
・ It’s prohibited to shift from NORMAL mode with use of PLL to STOP mode directly.
You should set NORMAL mode once, and then shift to STOP mode.(You should stop high
frequency oscillator after you stop PLL.)
Figure 3.3.1 System clock block diagram
The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called
fs. The clock frequency selected by SYSCR1<SYSCK> is called the system clock f
FPH
. The system clock f
SYS
is defined as the
divided clock of f
FPH
, and one cycle of f
SYS
is defined to as one state.