Toshiba TMPM3H User manual

TXZ+ Family
TMPM3H Group(2)
Clock Control and Operation Mode
2023-04-28
Rev. 1.0
© 2022-2023
Toshiba Electronic Devices & Storage Corporation
1 / 71
2023-04
32-bit RISC Microcontroller
TXZ+ Family
TMPM3H Group(2)
Reference Manual
Clock Control and Operation Mode
(CG-M3H(2)-D)
Revision 1.0

TXZ+ Family
TMPM3H Group(2)
Clock Control and Operation Mode
2023-04-28
Rev. 1.0
2 / 71
Contents
Contents............................................................................................................................................................... 2
List of Figures....................................................................................................................................................... 5
List to Tables........................................................................................................................................................5
Preface................................................................................................................................................................. 6
Related documents...................................................................................................................................................6
Conventions ............................................................................................................................................................7
Terms and Abbreviations..........................................................................................................................................9
1. Clock Control and Operation Mode............................................................................................................10
1.1. Outlines............................................................................................................................................................10
1.2. Clock control ....................................................................................................................................................11
1.2.1. Clock type...................................................................................................................................................................11
1.2.2. The initial value by a reset operation..........................................................................................................................11
1.2.3. Clock System diagram................................................................................................................................................12
1.2.4. Warming up function...................................................................................................................................................13
1.2.4.1. The warming up timer for a high speed oscillation.........................................................................................................13
1.2.4.2. The warming up timer for a low speed oscillation..........................................................................................................14
1.2.4.3. The directions for warming up timer ..............................................................................................................................14
1.2.5. Clock multiplying circuit (PLL) for fsys........................................................................................................................15
1.2.5.1. A PLL setup after reset release.....................................................................................................................................15
1.2.5.2. The formula and the example of a setting of a PLL multiplication value ........................................................................15
1.2.5.3. Change of the PLL multiplication value under operation................................................................................................17
1.2.5.4. PLL operation start/stop/switching procedure................................................................................................................17
1.2.6. System clock ..............................................................................................................................................................18
1.2.6.1. The setting method of a system clock ...........................................................................................................................19
1.2.7. Clock supply setting function......................................................................................................................................21
1.2.8. The output function of a clock in the terminal .............................................................................................................21
1.2.9. Prescaler clock...........................................................................................................................................................21
1.3. Operation mode...............................................................................................................................................22
1.3.1. Details of an Operation mode.....................................................................................................................................22
1.3.1.1. The feature in each mode .............................................................................................................................................22
1.3.1.2. Low Power Consumption mode.....................................................................................................................................23
1.3.1.3. Selection of a Low Power Consumption mode..............................................................................................................23
1.3.1.4. The peripheral function state in a Low power consumption mode.................................................................................23
1.3.2. Mode State Transition ................................................................................................................................................26
1.3.2.1. IDLE mode transition flow .............................................................................................................................................26
1.3.2.2. STOP1 mode transition flow..........................................................................................................................................27
1.3.2.3. STOP2 mode transition flow..........................................................................................................................................28
1.3.3. The return operation from a Low Power Consumption mode .....................................................................................29
1.3.3.1. The release source of a Low Power Consumption mode ..............................................................................................29
1.3.3.2. Warming up at the release of Low Power Consumption mode......................................................................................31
1.3.3.3. The restart operation from the STOP2 mode.................................................................................................................32
1.3.4. Clock operation by mode transition ............................................................................................................................33

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TMPM3H Group(2)
Clock Control and Operation Mode
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1.3.4.1. NORMAL →IDLE →NORMAL Operation mode transition...........................................................................................33
1.3.4.2. NORMAL →STOP1 →NORMAL Operation mode transition.......................................................................................33
1.3.4.3. NORMAL →STOP2 →RESET →NORMAL Operation mode transition......................................................................34
1.4. Explanation of register.....................................................................................................................................35
1.4.1. Register list.................................................................................................................................................................35
1.4.1.1. Clock and mode control.................................................................................................................................................35
1.4.1.2. Low speed oscillation/power control (Note)...................................................................................................................35
1.4.2. Register description....................................................................................................................................................36
1.4.2.1. [CGPROTECT] (CG write protection register)...............................................................................................................36
1.4.2.2. [CGOSCCR] (Oscillation control register)......................................................................................................................36
1.4.2.3. [CGSYSCR] (System clock control register)..................................................................................................................37
1.4.2.4. [CGSTBYCR] (Standby control register) .......................................................................................................................38
1.4.2.5. [CGSCOCR] (SCOUT Output control register)..............................................................................................................38
1.4.2.6. [CGPLL0SEL] (PLL selection register for fsys)..............................................................................................................39
1.4.2.7. [CGWUPHCR] (High speed oscillation warming up register).........................................................................................39
1.4.2.8. [CGWUPLCR] (Low speed oscillation warming up register)..........................................................................................40
1.4.2.9. [CGFSYSMENB] (Clock supply and stop register B for fsysm)......................................................................................41
1.4.2.10. [CGFSYSENA] (Clock supply and stop register A for fsys)..........................................................................................42
1.4.2.11. [CGFSYSENB] (Clock supply and stop register B for fsys)..........................................................................................44
1.4.2.12. [CGFCEN] (Clock supply and stop register for fc) .......................................................................................................46
1.4.2.13. [CGSPCLKEN] (Clock supply and stop register for ADC and Debug circuit)...............................................................46
1.4.2.14. [RLMLOSCCR] (Low speed oscillation control register)..............................................................................................46
1.4.2.15. [RLMSHTDNOP] (Power supply cut off control register) .............................................................................................46
1.4.2.16. [RLMPROTECT] (RLM write protection register).........................................................................................................47
1.5. Information according to product .....................................................................................................................48
1.5.1. [CGFSYSMENB] ........................................................................................................................................................48
1.5.2. [CGFSYSENA] ...........................................................................................................................................................49
1.5.3. [CGFSYSENB] ...........................................................................................................................................................50
2. Memory Map............................................................................................................................................... 51
2.1. Overview..........................................................................................................................................................51
2.1.1. TMPM3HxF10B.........................................................................................................................................................52
2.1.2. TMPM3HxFDB..........................................................................................................................................................53
2.2. Bus Matrix........................................................................................................................................................54
2.2.1. Structure.....................................................................................................................................................................54
2.2.1.1. Single chip mode...........................................................................................................................................................54
2.2.1.2. Single boot mode ..........................................................................................................................................................55
2.2.2. Connection table.........................................................................................................................................................56
2.2.2.1. Code area/ SRAM area.................................................................................................................................................56
2.2.2.2. Peripheral area..............................................................................................................................................................57
3. Power Supply and Reset Operation ...........................................................................................................58
3.1. Outline..............................................................................................................................................................58
3.2. Function and Operation ...................................................................................................................................59
3.2.1. Cold reset...................................................................................................................................................................59
3.2.1.1. Reset by a Power On Reset Circuit (without using a RESET_N pin).............................................................................60
3.2.1.2. Reset by a RESET_N pin..............................................................................................................................................61

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Clock Control and Operation Mode
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3.2.1.3. Continuation of reset by LVD.........................................................................................................................................63
3.2.2. Warm reset.................................................................................................................................................................64
3.2.2.1. Warm reset by RESET_N pin........................................................................................................................................64
3.2.2.2. Warm reset by internal reset .........................................................................................................................................64
3.2.3. Reset by STOP2 mode release..................................................................................................................................65
3.2.4. Starting in reset and single boot mode.......................................................................................................................65
3.2.5. Power On Reset Circuit..............................................................................................................................................67
3.2.5.1. Operation at the time of turn on.....................................................................................................................................67
3.2.5.2. Operation at the time of turn off.....................................................................................................................................67
3.2.6. About turn on power supply after turn off....................................................................................................................68
3.2.6.1. When using external reset circuit or internal LVD reset output ......................................................................................68
3.2.6.2. When not using external reset circuit and internal LVD reset output .............................................................................68
3.2.7. After reset release......................................................................................................................................................68
3.2.7.1. A reset factor and the reset initialized range..................................................................................................................69
4. Revision History..........................................................................................................................................70
RESTRICTIONS ON PRODUCT USE............................................................................................................... 71

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TMPM3H Group(2)
Clock Control and Operation Mode
2023-04-28
Rev. 1.0
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List of Figures
Figure 1.1 Clock system diagram.............................................................................................................12
Figure 1.2 Mode State Transition............................................................................................................. 26
Figure 1.3 STOP2 mode restart operation flow.......................................................................................32
Figure 1.4 NORMAL →STOP1 →NORMAL Operation mode transition...............................................33
Figure 1.5 NORMAL →STOP2 →RESET →NORMAL Operation mode transition.............................34
Figure 2.1 TMPM3HxF10.........................................................................................................................52
Figure 2.2 TMPM3HxFD .......................................................................................................................... 53
Figure 2.3 Single chip mode .................................................................................................................... 54
Figure 2.4 Single boot mode.................................................................................................................... 55
Figure 3.1 The reset operation by a Power On Reset Circuit..................................................................60
Figure 3.2 Reset operation by a RESET_N pin (1)..................................................................................61
Figure 3.3 Reset operation by a RESET_N pin (2)..................................................................................62
Figure 3.4 Reset operation by LVD reset.................................................................................................63
Figure 3.5 Warm reset action...................................................................................................................64
Figure 3.6 Starting in power supply is on and single boot mode.............................................................65
Figure 3.7 Starting in the single boot mode when power supply is stable...............................................66
Figure 3.8 Power On Reset Circuit.......................................................................................................... 67
List to Tables
Table 1.1 Details of a [CGPLL0SEL]<PLL0SET[23:0]> setup.................................................................15
Table 1.2 PLL correction (example).........................................................................................................16
Table 1.3 PLL0SET set point (example)..................................................................................................16
Table 1.4 The example of operation frequency (unit: MHz) ....................................................................18
Table 1.5 List of Use propriety in each operation mode.......................................................................... 21
Table 1.6 Low Power Consumption mode selection................................................................................23
Table 1.7 Block operation status in each Low Power Consumption mode............................................. 24
Table 1.8 Release source list...................................................................................................................29
Table 1.9 Warming up.............................................................................................................................. 31
Table 1.10 Allocation of [CGFSYSMENB] by product............................................................................. 48
Table 1.11 Allocation of [CGFSYSENA] by product................................................................................49
Table 1.12 Allocation of [CGFSYSENB] by product................................................................................50
Table 2.1 Single chip mode......................................................................................................................56
Table 2.2 Single boot mode.....................................................................................................................56
Table 2.3 Peripheral area......................................................................................................................... 57
Table 3.1 A reset factor and the initialized range .................................................................................... 69
Table 4.1 Revision History....................................................................................................................... 70

TXZ+ Family
TMPM3H Group(2)
Clock Control and Operation Mode
2023-04-28
Rev. 1.0
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Preface
Related documents
Document name
ARM®Cortex®-M3 Processor Technical Reference Manual
The datasheet of each product (Electrical Characteristics)
Exception
Oscillation Frequency Detector
Voltage Detection Circuit
Clock Selective Watchdog Timer
Flash Memory

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TMPM3H Group(2)
Clock Control and Operation Mode
2023-04-28
Rev. 1.0
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Conventions
●Numeric formats follow the rules as shown below:
Hexadecimal: 0xABC
Decimal: 123 or 0d123 (Only when it needs to be explicitly shown that they are decimal numbers.)
Binary: 0b111 (It is possible to omit the "0b" when the number of bits can be distinctly
understood from a sentence.)
●"_N" is added to the end of signal names to indicate low active signals.
●It is called "assert" that a signal moves to its active level, "deassert" to its inactive level.
●When two or more signal names are referred, they are described like as [m: n].
Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.
●The characters surrounded by [ ] defines the register.
Example: [ABCD]
●"n" substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], [XYZ3] →[XYZn]
●"x" substitutes suffix number or character of units and channels in the Register List.
In case of unit, "x" means A, B, and C …
Example: [ADACR0], [ADBCR0], [ADCCR0] →[ADxCR0]
In case of channel, "x" means 0, 1, and 2…
Example: [T32A0RUNA], [T32A1RUNA], [T32A2RUNA] →[T32AxRUNA]
●The bit range of a register is written like as [m: n].
Example: Bit[3: 0] expresses the range of bit 3 to 0.
●The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD]<EFG> = 0x01 (hexadecimal), [XYZn]<VW> = 1 (binary)
●Word and Byte represent the following bit length.
Byte: 8 bits
Half word: 16 bits
Word: 32 bits
Double word: 64 bits
●Properties of each bit in a register are expressed as follows:
R: Read only
W: Write only
R/W: Read and Write are possible
●Unless otherwise specified, register access supports only word access.
●The register defined as reserved must not be rewritten. Moreover, do not use the read value.
●The value read from the bit having default value of "-" is unknown.
●When a register containing both of writable bits and read-only bits is written, read-only bits should be written
with their default value, In the cases that default is "-", follow the definition of each register.
●Reserved bits of the Write-only register should be written with their default value. In the cases that default is
"-", follow the definition of each register.
●Do not use read-modified-write processing to the register of a definition which is different by writing and
read out.

TXZ+ Family
TMPM3H Group(2)
Clock Control and Operation Mode
2023-04-28
Rev. 1.0
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All other company names, product names, and service names mentioned herein may be trademarks of their
respective companies.
************************************************************************************************************************
Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
************************************************************************************************************************

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TMPM3H Group(2)
Clock Control and Operation Mode
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Terms and Abbreviations
Some of abbreviations used in this document are as follows:
ADC Analog to Digital Converter
A-ENC32 Advanced Encoder input Circuit (32-bit)
APB Advanced Peripheral Bus
A-PMD Advanced Programmable Motor Control Circuit
CG Clock control and Operation Mode
COMP Comparator
CRC Cyclic Redundancy Check
DAC Digital to Analog Converter
DMAC Direct Memory Access Controller
DNF Digital Noise Filter
ELOSC External Low Speed Oscillator
EHOSC External High Speed Oscillator
EI2C I2C Interface Version A
fsys frequency of SYSTEM Clock
I2C Inter-Integrated Circuit
I2CS Wake-up function by address matching
IHOSC Internal High speed Oscillator
IA (INTIF) Interrupt control register A
IB (INTIF) Interrupt control register B
I-Bus ICode memory interface
IMN Interrupt Monitor
INT Interrupt
IO IO Bus (32bit Peripheral Bus)
LCD Liquid Crystal Display
LVD Voltage Detection Circuit
NMI Non-Maskable Interrupt
OFD Oscillation Frequency Detector
POR Power On Reset Circuit
RAMP RAM Parity Circuit
RLM Low speed oscillation/power supply control/reset
RMC Remote Control Signal Preprocessor
RTC Real Time Clock
S-Bus System interface
SCOUT Source Clock Output
SIWDT Clock Selective Watchdog Timer
TPIU Trace Port Interface Unit
TRGSEL Trigger Selection Circuit
TRM Trimming Circuit
TSPI Serial Peripheral Interface
T32A 32-bit Timer Event Counter
UART Universal Asynchronous Receiver Transmitter

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Clock Control and Operation Mode
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1. Clock Control and Operation Mode
1.1. Outlines
The clock/mode control block can select a clock gear and prescaler clock and set the warm up of oscillator and so
on.
Furthermore, it has NORMAL mode and a Low Power Consumption mode in order to reduce power consumption
using mode transition.
Functions related to a clock are as follows.
●System clock control
●Prescaler clock control

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1.2. Clock control
1.2.1. Clock type
This section shows a list of clocks.
EHCLKIN: The clock input from the external.
fOSC: A clock generated in the internal oscillation circuit or input from the X1 and X2 pins
fPLL: A clock multiplied by PLL
fc: A clock selected by [CGPLL0SEL]<PLL0SEL> (high speed clock)
fs: A clock output from an external low speed oscillator
fsys: A system clock selected by [CGSYSCR]<GEAR[2:0]>
ΦT0: A clock selected by [CGSYSCR]<PRCK[3:0]> (prescaler clock)
fIHOSC1: A clock generated with the internal high speed oscillator 1
fIHOSC2: A clock generated with the internal high speed oscillator 2
ADCLK: A conversion clock for AD converter
TRCLKIN: A clock for tracing facilities of a debugging circuit (Trace/SWV)
1.2.2. The initial value by a reset operation
A clock setting is initialized to the following states by a reset operation.
External high speed oscillator: Stop
Internal high speed oscillator 1: Oscillation
Internal high speed oscillator 2: Stop
External low speed oscillator: Stop
PLL (multiplying circuit): Stop
Gear clock: fc (no frequency dividing)

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1.2.3. Clock System diagram
The figure below shows a clock system diagram.
Figure 1.1 Clock system diagram
Internal
High Speed
oscillator1
External
High speed
oscillator
X2
X1
[CGOSCCR]<EOSCEN[1:0]>
After Reset: Stop fOSC
[CGOSCCR]<IHOSC1EN>
After reset :Oscillation
fIHOSC1
[CGWUPHCR]
<WUCLK>
High Speed
Warming up timer
[CGWUPHCR]<WUON>
[CGWUPHCR]<WUPT[15:4]>
Internal
High speed
oscillator2
[CGOSCCR]<IHOSC2EN>
After reset：Stop
OFD
[CGOSCCR]
<OSCSEL>
fEHOSC
PLL0
PLL for fsys fPLL
[CGPLL0SEL]
<PLL0SEL>
fc fc (to fsys and ΦT0 generation)
[CGSPCLKEN]
<ADCKEN>
ADC
SCOUT
[CGSCOCR]
<SCOEN>
1/161/81/41/2 [CGSCOCR]<SCODIV[2:0]>
[CGSCOCR]<SCOSEL[2:0]>
fOSC
fc
No dividing when fsis selected.
External
Low speed
Oscillator
XT2
XT1
Low speed
Warming up timer
[CGWUPLCR]<WULON>
[CGWUPLCR]<WUPTL[18:4]>
fs RTC, RMC, T32A (TRGSEL)
fs
fc
【Peripheral function prescaler inputs】
T32A, UART, TSPI
fsys
[RLMLOSCCR]<XTEN>
After Reset: Stop
[CGSYSCR]
<PRCK[3:0]>
ΦT0
[CGSYSCR]
<GEAR[2:0]>
fsys
TRCLKIN
[CGSPCLKEN]
<TRCKEN>
1/64 SysTick
TRCK 1/2
1/64 1/1281/161/81/41/2 1/32 1/256 1/512
fc 1/2 1/4 1/8 1/16
DMAC, TSPI, I2C, EI2C,
UART, SIWDT, T32A, RTC,
A-PMD, A-ENC32, RMC,
ADC, DAC, OFD, PORT,
TRM, TRGSEL, CRC, RAMP
CPU
fOSC
SIWDT
Flash
SIWDT
LCD
[CGFSYSENB]<IPENBxx>
[CGFSYSENA]<IPENAxx>
[CGFSYSMENB]<IPMENBxx>
ADCLK
fIHOSC2
OSCPRO
TPIU
EHCLKIN
DEBUG
Flash, RAM, INTIF
fsys
DNF
[CGFCEN]<FCIPEN07>
LCD
fIHOSC2

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Clock Control and Operation Mode
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1.2.4. Warming up function
A warming up function is used to secure the oscillation stable time at the time of the STOP1 mode release which
starts the warming up timer for high speed oscillation automatically.
It is available also as a count up timer which uses the exclusive warming up timer of high speed clock /each low
speed clock for the waiting for the stability of an external oscillator or an internal oscillator.
This chapter explains the setting method to the register for warming up timers, and the case where it is used as a
count up timer. The detailed explanation at the time of STOP1 mode release, refer to "1.3.3.2 Warming up at the
release of Low Power Consumption mode".
1.2.4.1. The warming up timer for a high speed oscillation
A 16-bit up counter is built in as a warming up timer only for a high speed oscillation. Also when setting before
changing to the STOP1 mode, the setting value is calculated in the following formula, set
[CGWUPHCR]<WUPT[15:4]> to the upper 12 bits of the setting value. Lower 4 bits are ignored.
＜Formula＞
(Using EHOSC)
Warming up timer setting value (16 bits)
= - (warming up time (s) / clock period (s)) -16
(Example) When 5 ms of warming up time is set up with 10MHz (100ns of clock periods) of oscillators
Warming up timer setting value (16 bits) = (5ms / 100ns) - 16
= 50000 - 16
= 49984
= 0xC340
Since upper 12 bits are set to a register, they are set as follows.
[CGWUPHCR]<WUPT[15:4]> = 0xC34
(Using IHOSC1)
Warming up timer setting value (16 bits)
= - ((warming up time (s) -63.3 (μs)) / clock period (s)) -41
(Example) When 163.4μs of warming up time is set up with 10MHz (100ns of clock periods) of oscillators
Warming up timer setting value (16 bits) = ((163.4-63.3) / 100ns) - 41
= (100.1μs / 100ns) - 41
= 960
= 0x03C0
Since upper 12 bits are set to register, they are set as follows.
[CGWUPHCR]<WUPT[15:4]> = 0x03C
In the case of 10MHz, the setting range is 0x03C ≤<WUPT[15:4]> ≤0xFFF, the warming up time is set from
163.4μs to 6.6194ms.

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1.2.4.2. The warming up timer for a low speed oscillation
A 19-bit up-timer is built in as a warming up timer only for a low speed oscillation. The setting value is calculated
in the following formula, set [CGWUPLCR]<WUPT[18:4]> to the upper 15 bits of the setting value. Lower 4 bits
are ignored. 16 is subtracted in order to perform the count for 4 bits of low ranks, even when a set point is "0".
＜Formula＞
Warming up timer setting value (19 bits)
= (warming up time (s) / clock period (s)) - 16
(Example) When 50ms of warming up time is set up with 32kHz (clock period 31.25μs) of oscillators
Warming up timer setting value (19 bits) = (50ms / 31.25μs) - 16
= 1600 - 16
= 1584
= 0x00630
Since upper 15 bits are set to a register, they are set as follows.
[CGWUPLCR]<WUPTL[18:4]> = 0x0063
In the case of 32kHz, the setting range is 0 ≤<WUPTL[18:4]> ≤0x7FFF, the warming up time is set from 500μs
to 16.384s.
1.2.4.3. The directions for warming up timer
The directions for a warming up function are explained.
(1) Selection of a clock
In a high speed oscillation, the clock classification (internal oscillation/external oscillation) counted with a
warming up timer is selected by [CGWUPHCR]<WUCLK>.
(2) Calculation of warming up timer setting value
The warming up time can set any value to the timer for a high speed oscillation/for a low speed oscillation.
Please compute and set up from each formula.
(3) The start of warming up, and termination confirmation
When software (instruction) performs to start warming up and to confirms termination of warming up, a
warming up timer starts by setting [CGWUPHCR]<WUON> (or [CGWUPLCR] <WULON>) to "1".
Termination is confirmed with [CGWUPHCR]<WUEF> (or [CGWUPLCR]<WULEF>) that becomes from
"1" to "0". "1" indicates under warming up and "0" indicates termination. After a counting end, a timer is
reset and returns to an initial state.
It is not forced to terminate, although "0" is written to [CGWUPHCR]<WUON> (or [CGWUPLCR]
<WULON>) during timer operation. Writing "0" is ignored.
Note: Since it is operating with the oscillating clock, a warming up timer includes an error, when Oscillation
frequency has fluctuation. Therefore, it should be taken as an approximate time.

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1.2.5. Clock multiplying circuit (PLL) for fsys
The clock multiplying circuit outputs the fPLL clock (up to 120MHz) multiplied by the optimum condition for the
frequency (6MHz to 12MHz) of the output clock fOSC of the high speed oscillator.
So, it is possible to make the input frequency to an oscillator low speed and to make an internal clock high speed
by this circuit.
1.2.5.1. A PLL setup after reset release
The PLL is disabled after reset release.
In order to use the PLL, set [CGPLL0SEL]<PLL0SET> to a multiplication value while [CGPLL0SEL]
<PLL0ON> is "0". Then wait until approximately 100 μs has elapsed as a PLL initial stabilization time, and set
<PLL0ON> to "1" to start PLL operation.
After that, to use fPLL clock which is multiplied fOSC, wait until approximately 400 μs has elapsed as a lock up
time. Then set "1" to [CGPLL0SEL]<PLL0SEL>.
Note that a warm up time is required until PLL operation becomes stable using the warm up function, etc.
1.2.5.2. The formula and the example of a setting of a PLL multiplication value
The details of the items of [CGPLL0SEL]<PLL0SET[23:0]> which set up a PLL multiplication value are shown
below.
Table 1.1 Details of a [CGPLL0SEL]<PLL0SET[23:0]> setup
The items of PLL0SET
Function
[23:17]
Correction value
setting
The quotient of fOSC/450k (integer). For detail refer to Table 1.2
[16:14]
fOSC setting
000: 6 ≤fOSC ≤7 100: 12 < fOSC ≤15
001: 7 < fOSC ≤8 101: 15 < fOSC ≤19
010: 8 < fOSC ≤10 110: 19 < fOSC ≤24
011: 10 < fOSC ≤12 111: Reserved
(Unit: MHz)
[13:12]
Dividing setting
00: Reserved
01: 2 dividing (× 1 / 2)
10: 4 dividing (× 1 / 4)
11: 8 dividing (× 1 / 8)
[11:8]
Fraction part
Multiplication setting
0000: 0.0000 1000: 0.5000
0001: 0.0625 1001: 0.5625
0010: 0.1250 1010: 0.6250
0011: 0.1875 1011: 0.6875
0100: 0.2500 1100: 0.7500
0101: 0.3125 1101: 0.8125
0110: 0.3750 1110: 0.8750
0111: 0.4375 1111: 0.9375
[7:0]
Integer part
Multiplication setting
0x00: 0
0x01: 1
0x02: 2
:
0xFD: 253
0xFE: 254
0xFF: 255
Note: A multiplication value is the total of <PLL0SET[7:0]> (integer part) and <PLL0SET[11:8]> (fraction
part).

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Clock Control and Operation Mode
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fPLL is denoted by the following formulas.
fPLL= fOSC× ([CGPLL0SEL]<PLL0SET[7:0]> + [CGPLL0SEL]<PLL0SET[11:8]>) ×
([CGPLL0SEL] <PLL0SET[13:12]>)
Note1. The absolute value of frequency accuracy is not guaranteed.
Note2. There is no Linearity in the frequency by the fractional part Multiplication setup.
Note3: fPLL ≤(Maximum Operating Frequency)
Table 1.2 PLL correction (example)
fOSC (MHz)
<PLL0SET [23:17]> (a decimal, an integral value)
6.00
14
8.00
18
10.00
23
12.00
27
A PLL correction can be calculated below.
When fOSC = 6.0MHz, 6.0 / 0.45 = 13.33 ≈ 14 ; A fractional part is rounded up.
The main examples of a setting of [CGPLL0SEL]<PLL0SET[23:0]> are shown below.
(1) It multiplies by PLL, and dividing is carried out and the target Clock frequency (fPLL) is generated for input
frequency (fOSC).
(2) A dividing value is chosen from 1/2, 1/4, and 1/8.
(3) Moreover, set up the frequency after multiplication in the following ranges.
200MHz ≤(fOSC × multiplication value) ≤ 320MHz
Table 1.3 PLL0SET set point (example)
fOSC (MHz)
Multiplication
value
Dividing
value
fPLL (MHz)
<PLL0SET[23:0]>
6.00
40.0000
1/2
120.00
0x1C1028
8.00
30.0000
1/2
120.00
0x24501E
10.00
24.0000
1/2
120.00
0x2E9018
12.00
20.0000
1/2
120.00
0x36D014
6.00
53.3125
1/4
79.97
0x1C2535
8.00
40.0000
1/4
80.00
0x246028
10.00
32.0000
1/4
80.00
0x2EA020
12.00
26.6250
1/4
79.88
0x36EA1A
6.00
53.3125
1/8
39.98
0x1C3535
8.00
40.0000
1/8
40.00
0x247028
10.00
32.0000
1/8
40.00
0x2EB020
12.00
26.6250
1/8
39.94
0x36FA1A

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1.2.5.3. Change of the PLL multiplication value under operation
It changes to a setup which sets "0" to [CGPLL0SEL]<PLL0SEL> first, and does not use a PLL multiplication
clock during PLL multiplication clock operation when changing a multiplication value. And [CGPLL0SEL]
<PLL0ST> = 0 is read, after checking having changed to a setup which does not use a multiplication clock,
[CGPLL0SEL]<PLL0ON> is set to "0", and PLL is stopped.
Then, the multiplication value of [CGPLL0SEL]<PLL0SET> is changed, as reset time of PLL, after about 100μs
progress, [CGPLL0SEL]<PLL0ON> is set to "1", and operation of PLL is started.
Then, [CGPLL0SEL]<PLL0SEL> is set to "1" after lock up time (about 400μs) has elapsed.
Finally, [CGPLL0SEL]<PLL0ST> is read and it checks having changed.
1.2.5.4. PLL operation start/stop/switching procedure
(1) fc setup (PLL stop →PLL start)
As an fc setup, the example of switching procedure from the PLL stop state to the PLL operation state is as
follows.
<<The example of switching procedure>>
1
[CGPLL0SEL]<PLL0SET> = 0xX
A PLL multiplication value setup is chosen.
2
Wait 100µs or more
Latency time after a multiplication setup
3
[CGPLL0SEL]<PLL0ON> = 1
PLL operation for fsys is carried out to an oscillation.
4
Wait 400µs or more
PLL output clock stable latency time
5
[CGPLL0SEL]<PLL0SEL> = 1
PLL selection for fsys is carried out to PLL use (fPLL).
6
Read [CGPLL0SEL]<PLL0ST>
It waits until the PLL selection status for fsys becomes "PLL use (fPLL)
(= 1)".
Note: 1 to 4 is unnecessary when the state before switching is [CGPLL0SEL]<PLL0ON> = 1. When changing
from the state where the PLL Output clock was stabilized, it can change to the conduct PLL state by
execution of only 5 and 6.
(2) fc setup (PLL operation →PLL stop)
As an fc setup, the example of switching procedure from the PLL operation state to a PLL stop state is as
follows.
<<The example of switching procedure>>
1
[CGPLL0SEL]<PLL0SEL> = 0
Selects the PLL for fsys to "PLL is unused (fOSC)".
2
[CGPLL0SEL]<PLL0ST> , it read.
Waits until the status of the PLL for fsys becomes "PLL is unused
(fOSC) (= 0)".
3
[CGPLL0SEL]<PLL0ON> = 0
Sets the PLL operation for fsys to stop.
<<The state before switching>>
[CGPLL0SEL]<PLL0ON> = 0
Stops the PLL operation for fsys.
[CGPLL0SEL]<PLL0SEL> = 0
Selects the setting of the PLL for fsys to "PLL is unused (fOSC)".
[CGPLL0SEL]<PLL0ST> = 0
Indicates the status of the PLL for fsys to "PLL is unused (fOSC)".
<<The state before switching>>
[CGPLL0SEL]<PLL0ON> = 1
Sets the PLL oscillation for fsys.
[CGPLL0SEL]<PLL0SEL> = 1
Selects the PLL for fsys to "PLL is used (fPLL)".
[CGPLL0SEL]<PLL0ST> = 1
Indicates the status of the PLL for fsys to "PLL is used (fPLL)".

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1.2.6. System clock
An internal high speed oscillation clock or external high speed oscillation clock (connected oscillator or clock
input) can be used as a source of system clock.
Dividing is possible for a system clock at [CGSYSCR]<GEAR[2:0]> (clock gear). Although a setup can be
changed during operation, after register writing before a clock actually changes, a maximum of 16-clock time is
required of fc. Check completion of a clock change by [CGSYSCR]<GEARST[2:0]>.
Note: Do not change a clock gear during operation of peripheral functions, such as a timer counter.
Table 1.4 shows the example of operation frequency by the clock gear ratio (1/1 to 1/16) to the frequency fc set up
with oscillation frequency, a PLL multiplication value, etc.
Table 1.4 The example of operation frequency (unit: MHz)
External
oscillation
(MHz)
External
Clock
input
(MHz)
Internal
oscillation
IHOSC1
(MHz)
PLL
Multiplication
value
(After
dividing)
Maximum
Frequency
(fc) (MHz)
Clock gear
PLL = ON
Clock gear
PLL = OFF
1/1
1/2
1/4
1/8
1/16
1/1
1/2
1/4
1/8
1/16
6
6
-
20
120
120
60
30
15
7.5
6
3
1.5
-
-
8
8
-
15
120
120
60
30
15
7.5
8
4
2
1
-
10
10
10
12
120
120
60
30
15
7.5
10
5
2.5
1.25
-
12
12
-
10
120
120
60
30
15
7.5
12
6
3
1.5
-
6
6
-
13.329
79.97
79.97
39.99
20
10
5
6
3
1.5
-
-
8
8
-
10
80
80
40
20
10
5
8
4
2
1
-
10
10
10
8
80
80
40
20
10
5
10
5
2.5
1.25
-
12
12
-
6.657
79.88
79.88
39.95
19.98
9.99
4.99
12
6
3
1.5
-
6
6
-
6.625
39.75
39.75
19.9
9.94
4.97
2.48
6
3
1.5
-
-
8
8
-
5
40
40
20
10
5
2.5
8
4
2
1
-
10
10
10
4
40
40
20
10
5
2.5
10
5
2.5
1.25
-
12
12
-
3.3125
39.75
39.75
19.9
9.94
4.97
2.48
12
6
3
1.5
-

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1.2.6.1. The setting method of a system clock
(1) fOSC setup (internal oscillation →external oscillation)
As a fOSC setup, the example of switching procedure to the external oscillation (EHOSC) from an internal
oscillation (IHOSC1) is shown below.
Note: Do not connect except a resonator.
<<The example of switching procedure>>
1
[PHPDN]<bit[1:0]> = 00
[PHIE]<bit[1:0]> = 00
Disable the pull-down of X1/X2 pin.
Disable input control of X1/X2 pin.
2
[CGOSCCR]<EOSCEN[1:0]> = 01
It is an external oscillation (EHOSC) about selection of an external
oscillation of operation.
3
[CGWUPHCR]<WUCLK> = 1
[CGWUPHCR]<WUPT[18:4]> = "arbitrary
value"
It is the external (EHOSC) about high speed oscillation warming up
clock selection.
Oscillator stable time is set to a warming up timer setting value.
4
[CGWUPHCR]<WUON> = 1
High speed oscillation warming up is started.
5
[CGWUPHCR]<WUEF> is read.
It waits until it becomes the termination of high speed oscillation
warming up (= 0).
6
[CGOSCCR]<OSCSEL> = 1
It is high speed oscillation selection for fOSC to the exterior (EHOSC).
7
[CGOSCCR]<OSCF> is read.
It waits until the high speed oscillation selection status for fOSC
becomes outside (= 1).
8
[CGOSCCR]<IHOSC1EN> = 0
An internal high speed oscillator 1 is suspended.
(2) fOSC setup ( internal oscillation →external clock input)
As a fOSC setup, the example of switching procedure to the external clock input (EHCLKIN) from an internal
oscillation 1 (IHOSC1) is shown below.
<<The example of switching procedure>>
1
[PHPDN]<bit[0]> = 0
[PHIE]<bit[0]> = 1
Disable the pull-down of X1 pin.
Enable the input control of an X1/EHCLKIN pin.
2
[CGOSCCR]<EOSCEN[1:0]> = 10
Selection of an external oscillation of operation is carried out to an
external clock input (EHCLKIN).
3
[CGOSCCR]<OSCSEL> = 1
It is high speed oscillation selection for fOSC to an external clock.
4
[CGOSCCR]<OSCF> is read.
It waits until the high speed oscillation selection status for fOSC
becomes outside (= 1).
5
[CGOSCCR]<IHOSC1EN> = 0
An internal high speed oscillator 1 is suspended.
<<The state before switching>>
[CGOSCCR]<IHOSC1EN> = 1
An internal high speed oscillator 1 oscillates.
[CGOSCCR]<OSCSEL> = 0
The high speed oscillation selection for fOSC is an inside (IHOSC1).
[CGOSCCR]<OSCF> = 0
The high speed oscillation selection status for fOSC is an inside
(IHOSC1).
An oscillator is connected to X1/X2 pin. (Note)
<<The state before switching>>
[CGOSCCR]<IHOSC1EN> = 1
An internal high speed oscillator 1 oscillates.
[CGOSCCR]<OSCSEL> = 0
The high speed oscillation selection for fOSC is an inside (IHOSC1).
[CGOSCCR]<OSCF> = 0
The high speed oscillation selection status for fOSC is an inside
(IHOSC1).
Clock input to EHCLKIN
Input in the proper voltage range.

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(3) fOSC setup (an external oscillation/external clock input →an internal oscillation)
As a fOSC setup, the example of switching procedure to the internal oscillation (IHOSC1) from an external
oscillation (EHOSC) or an external clock input (EHCLKIN) is shown below.
<< The example of switching procedure >>
1
[CGWUPHCR]<WUCLK> = 0
Set the warming-up clock selection to internal high speed oscillator 1
(IHOSC1).
2
[CGWUPHCR]<WUPT[15:4]> = 0x03C
Set the high speed oscillation warming-up timer setting value of
163.4μs (= 0x3C) or more.
3
[CGOSCCR]<IHOSC1EN> = 1
An internal high speed oscillator 1 oscillates.
4
[CGWUPHCR]<WUON> = 1
Start the high speed oscillation warming-up timer
5
[CGWUPHCR]<WUEF> is read.
Wait until an warming-up timer status flag becomes ends (= 1).
6
[CGOSCCR]<OSCSEL> = 0
Set the high speed oscillation selection for fOSC to internal high-speed
oscillator1 (IHOSC1).
7
[CGOSCCR]<OSCF> is read.
It waits until the high speed oscillation selection status for fOSC
becomes an inside (= 0).
8
[CGOSCCR]<EOSCEN[1:0]> = 00
Set the selection of an external oscillator operation to unused.
<< The state before switching >>
[CGOSCCR]<EOSCEN[1:0]> = 01 or 10
Selection of an external oscillator of operation is an external oscillator
(EHOSC) or external clock input.
[CGOSCCR]<OSCSEL> = 1
The high speed oscillation selection for fOSC is the exterior (EHOSC).
[CGOSCCR]<OSCF> = 1
The high speed oscillation selection status for fOSC is the exterior
(EHOSC).