Sharp PC-6220 User manual

-
PC-6220
SHARP
SERVICE MANUAL
CODE: 00ZPC6220SM-E
PERSONAL COMPUTER
MODEL PC-6220
OPTION: CE-621NK
CE-621A
CE-621B
CE-621EV
CE-621F
~----------- CONTENTS -------------."
CHAPTER 1. Out line of the PC-6220 .............................. 1
CHAPTER
2. Disassembly and assembly ........................... 9
CHAPTER
3. System block diagram .............................. 12
CHAPTER
4. Theory of operation ................................ 15
CHAPTER
5. HOD ............................................ 31
CHAPTER 6. LCD ............................................ 35
CHAPTER
7. Power supply unit .................................. 38
CHAPTER
8. Keyboard (CE-621 NK) .............................. 46
CHAPTER
9. Description of LSls ................................. 51
CHAPTER 10. CRT IIF UNIT (CE-621 A) ............................ 86
CHAPTER
11. Add-on Battery pack (CE-621 EV) ...................... 90
CHAPTER 12. 3.5 inch FDD unit (CE-621 F) : ........................ 93
CHAPTER
13. Circuit diagrams and PWB layouts ..................... 95
Parts Guide
SHARP CORPORATION
This document has been published to be used
for after sales service only.
The contents are subject to change without notice.

CHAPTER 1. OUTLINE OF THE
PC-6220
1-1. Features
1} Equipped with a 20MB hard diskas a standard
component.
The PC-6220 is equipped with a 20MB hard disk as a standard
component.
This is great enough for salesmen to store customer information and
product information and for busy business men to stofe conference
materials, reports, and other information, allowing them to be
retrieved at once when needed.
2} World's lightest, thinnest (lettersize) booktype
personal computer with
HOD.
The PC-6220 is in letter size (11.0"W x 8.5"W x 1.4"H/279mm Wide x
216mm Deep), smaller than A4 size. Its thickness is only 34mm, and
the volume
is approx. 60% of the conventional note size personal
computers with FDD. It can be put in a half side of an attache case,
and even in a clutch bag. Its light weight (2kg) and the battery drive
system allows easy carrying in business trip.
6} System configuration
-
PC-£220
3} Black-and-white TST LCD with backlight
The black-and-white Triple Super Twist Liquid Crystal Display (TST
LCD) with back light (side light) gives clear screen in
16 gradations,
allowing to be used in a hotel room or other insufficiently illuminated
place.
The screen size is greater than any other conventional note size
personal computers and displays more Jines of characters. (PC-6220:
640 x 480 dots)
4} MODEM, mJmloIY and OJbeI buiIJ-inoptions_
available
Built-in options are available such as a MODEM board (2400bps,
class 5), CRT interface. Max. 2MB additional memory can be added
(total 3MB) without extending the external dimensions.
5} The expansion units (option) provide as high a
level
of expansion as laptop PC's of higher
class.
The combination with expansion units (option) such as a 3.5 inch
FDD and expansion slot (AT spec. half and full size card), provides
as
high a level of expansion as laptop PC's of higher class. This allows
to use a variety of PC/AT peripheral devices and to connect with a
host computer, forming a LAN system.
Full keyboard (PS/2 Keyboard)
5.25"
FDD UNIT
(CE-452F)
@/~z~
Add-on battery pack (CE-621 EV)
j
Modem card
fl /
CRT IIF card IY ~
fl /--
IY
(CE-621A)
80287
Serial paralle!
IIF (Standard)
/
Fig.1-1
-1-
ISM card
IJ
FullX1
. Half X1
L_.D"Il---"
. \ :ff5
\
RAM card (1 Mbyte)
(CE-621B)
£junits
Numeric keyboard
(CE-621NK)

..
.-'-'..-,..-,. .c- - ~ -~ -_',
".C2." C. PU f- ~ 80C287- i
J6I7.1~12MHz) , I _! Coprpcessor ,
~ ____ ._.J
Rdf..1
(BIOS)
·Lr
1-1 'i I Keyboard
~~
ROM /' ,LCD ,'\
_~~_~~!~M~~~OQOS~'~'_F=FJ~,~ '~.~·~f~-~··:-~.c-
LAPUNK) -\:::W/EdgSlight )
RAM
(1MB)
i-+-'-
___ L: __ ,
--------,
1 RAM'card .
, -(1MB) - ,
~~~---C..l
. Serial IfF H·} ! RS-232C -.
" f-. (RS-232C)'; _. --~-! ~periph'~ral !
.t:..;; •• _.~ .. _.J
! RAM card '
, (1MB) ,
L ______ .J
l
20MB-f--
HOD J
- - -, I
___ I MODEM card ~-( .: ......... Telephone
--},,~~~;-:;;~-~ I· /"::;""""
L'j C~:{A !-~ .. :.----( monitor )
'--.. _____ .1 , ___ ~
...........,
Add on battery :
CE-621EV '
~'Exp~i~~}--j or !-~.-.-.--! E~;_~~~'~:~~~"
CE-621E .' 1'·
i--------, I '3.5"FOO,""'- ")«_,..1 '~-1 ,
! JlQ cards I !<C------l GE-621F 'T j '.j .
J (Fuhize X 1, .!. ,,_.,' . ___ .1
, Half size X1) I I '-----.~ .. .:_.J
L___________ 0 __ -----,
~---------- .. f External I
L_~~~~_.i
~J: Options
Fig_1-2
(PS/2 Key board)
-2-
1-2. Specification" ..
1) Hardware
CPU:
CO-PROCESSOR:
ROM:
RAM:
DATA STORAGE:
DISPLAY:
KEYBOARD:
INTERFACE:
80C286 (6/7_16/12MHz)
• Clock speed can be chan~ed in Setup
screen.
Socket lor 80C287A, 80C287XL, 80287
1 rvi byte Mask ROM" l'
• Contents: IPL, Sell check, -Setup-, AT
------:ST<JS,VGA BIOS, OOS system; ,Ulilily
Software C
1M byte standard
.1M bit PS-RAM x 8
6401( byte for conveniional, 360K byte
ior EXpandedQr'EXtended.memoiy
LIM/EMS 4.0 support
Bus width: 16bit
·. i wail· stale (i2MHz) o wait state
(617016MHz) .
Expandal)leup
10 3M byte in 1M byte in-
creITIents by optional RAM card. (CE-
621B) . . ,
.• Two (2) RAM cards can be installed as
a Maxiinum.,
2_5 inch 20M byte Hard disk drive
• Average access time: 23m sec.
TST (Triple Super Twisted) LCD wilh
CCFT (Cold Cathode. Fluorescent Tube)
backlight
• Resolution: 640 x 480 pixels
• VGAcompatible
16 Gradations
Viewing area: 8" x
6"
• Aspect ratio: 1:1
• Dot pitch: 0.31 mm
LCD contrast and backlight brighlness
are adjustable by each volume.
Selectable normal/reverse screen by
hardware switch.
CRT I/F (optional) (CE-621
A)
• Analog RGB output
VGAcompalible
D-sub 15 pin female connector
Selectable LCD/CRT mode by
Hardware switch.
LCD and CRT can not be used simul-
taneously.
Alternative use with MODEM card.
IBM 101/102 like keyboard layout
79 keys (US layout)
80 keys (UK/German layoul)
Integrated numeric keypad
• 'Set Up' key for Setup screen
• Fn key for special function
~12.pmgrammable function keys
• 19mm pitch (type writer key part), 2mm
stroke
Detachable structure for installing inter-
nal options. (Co-processor,
RAM cards)
Serial (RS-232C) x 1
• D-sub 9 pin male connector
• Baud rate, data bits, stop bits and
parity are selectable in Setup screen.
Paraliel (centronics) x 1
Specialized
26 pin connector
With conversion adaptor to D-sub 25
pin female standard connector

SLOT/CONNECTOR:
POWER SUPPLY:
BATTERY LIFE:
Numeric keypad x 1
(CE-B21 NK)
• Optional Numeric keypad can be con-
nected.
1 slot for internal options
• Optional MODEM card or CRT adaptor
can be connected.
2 slots for RAM cards
• Optional 1M byte RAM cards can be
connected.
1 Expansion connector
• Optional 3.5" FDD unit. or E'plInsion
unit can be connected.
Ni-Cd battery
Rechargeable and replaceable
9.B V, 11.5 WH
2 hours fast charging in charge mode
and trickle charging while operating.
AC adaptor
• Input: 1 OOV -240V AC 50/BOHz
• Output: 15V DC
• AC cord is detachable from AC adaptor.
Add-on batery pack (optional) (CE-B21 EV)
Rechargeable with AC adaptor for main
unit.
3.5 hours fast charging in charge mode
and triele charging while operating.
Only with internal battery:
1.7H
• Hard disk access 10%, backlight
midium, without options.
With internal battery and add-on battery:
4.7H
Hard disk access 10%, backlight
midium, without options.
POWER SAVE FUNCTION:
CPU:
• Standby mode
Hard disk drive:
• Spindle motor off
Backlight:
• Backlight timeout
LOW BATTERYALARM: 1st-step:
CHARGING INDICATOR:
With the battery in the normally
charged state, LOW BATTERY in-
dicator remains off.
2nd-step:
When the battery is more than roughly
90% discharged, LOW BATTERY in-
dicator turns red and an alarm beeps
for about 15 seconds.
3rd-step:
After LOW BATTERY indicator blinking
and an alarm beeping for about 30
seconds, the system will shut off the
power automatically.
Main unit:
CHARGE indicator blinks while the
battery is being charged, and il~
luminates when the battery is at least
90% charged.
Add-on battery pack:
CHARGE indicator blinks while the
-
PC-6220
2) Mechanical
CONNECTORS:
External connectors for:
Serial interface:
Parallel interface:
Numeric keypad:
AC adaptor:
System expansion bus:
Add-on battery pack:
Internal connectors for:
Modem card or
D~sub 9 pin connector
SpeCialized 26 pin con~
nectar
Specialized 10 pin con~
nectar
2 conductor phone jack
120 pin connector
4-pin connector-
CRT adaptor: 68 pin connector
RAM card x 2: 50 pin connector
SWITCHES: Power switch (seesaw switch)
LCD standard/reverse screen switch 9slide switch)
LCD/CRT select switch (slide switch)
Speaker controll switch
Switch on the main PWB
BUZZER ON/OFF HIGH
BUZZER
Volume swich HIGH/LOW
VOLUMES: LCD contrast adjust volume (rotary volume)
LCD brightness adjust volume (rotary volume)
LEDS:
Power indicator (green or orange)
Low battery indicator (red)
Charge indicator (green)
FDD indicator (green)
HDD indicator (green)
Caps lock indicator (green)
Num lock indicator (green)
Scroll lock indicator (green)
DIMENSIONS:
8.5"(D) x
11 .O"(W) x1.4"(H)
21 Bmm(D) x279mm(W) x34mm(H)
WEIGHT: 2 Kg (4.4lbs)
(Including battery, excluding AC adaptor)
battery-is-beiAg--c-n
ar
gea ,---amJ-iI---------------- --- ----------
luminates when the battery is at least
70% charged.
POWER CONSUMPTION: Typ. 7 W (without options)
-3-

Key board Layout
a) US version
b) UK version
c) German version
Fig.1-3
Fig.1-4
Fig.1-S
-4-

3) Software
OPERATING SYSTEM: MS-DOS 4.01
Including SHELL 1.01
Compressed and stored in Mask ROM
MS~DOS must be installed into Hard
Disk when initializing the system.
Language:
English
BUILT-IN SOFTWARE: LAP-LINK 2.16 self install version
Stored in Mask ROM
With connecting cable
{To-serial D~sub 9- or 25 pin connector)
Language: English
4) Operational and storage range
Operational range:
Storage range:
50 to 95 degrees F
10to 35 degrees C
20 to 80% humidity (Non-condensing)
-4 to 140 degrees F
-2010 60 degrees C
10 to 90% humidity (non-condensing)
1-3. Software description
1) BIOS
The BIOS of the PC-6220 is included in a 1 MBit one"time ROM.
The system BIOS and the video BIOS are stored in the ROM and
attached to a separate PWB other than the main PWB.
Special function of the BIOS in PC·6220 are described below:
1-1) Power saving
The PC-6220 is equipped with three levels ofpower saving.
CD Display power saving
(2) Hard disk power saving
ell System power saving
These power saving functions
are performed with the time-out values
set
by SETUP. The system power saving can be also executed by key
input. Some application software may not work correctly with system
power saving function. If there are any problems in the power saving
function, Please disable
the function by SET_UP.
-5-
1-2) Automatic setting of hardware -
PC-6220
The PC-6220 hardware setting is performed for the following items.
CD Built-in VGA mode setting
® Display adapter setting
@ Each device 110 port setting
@ FDD/HDD assignment
® Built-in memory seHing
The following items are automatically detected and proper settings
are made automatically.
CD FDD presence
® FDD type
@ HDDtype
@ Main memory and expansion memory capacity
When no FDD is connected, BIOS Jevel emulation is performed. Then
the machine works
as if two FDDs are connected without disk inser-
tion.
1-3) ROM disk
To use ROM disk, set Drive C to ROM disk in hardware installation.
With the ROM disk, only the following three items can be executed.
Gl MS-DOS installation
<ID Diag. program execution
® Setup execution
1 -4) SpeCial functions with key operation
SETUP key: "SET UP" ODH character line is displayed.
CTRL +
ALT + SETUP: Setup program execution
Fn + SETUP: Displayed pallet number change
(Fn + PAUSE) : System power saving execution/return
(CTRL + ALT + PAUSE)
• CTRL+ALT+ 1': CPU clock UP (6 .... 7.16 .... 12 MHz)
CTRL + ALT + ~ : CPU clock down (12 .... 7.16 .... 6MHz)
2) Setup
2-1) Setup procedure
There are following two procedures for entering the setup mode.
Gl Execute SET UP command of MS DOS.
<ID Press CTRL + ALT +SETUP keys while the system is operating.
This procedure is effected by the key interruption. When, there-
fore, the
cQntrQI e.xits from the setup mode, the system is
rebooted.

-
"~BC;;---6~2Q~
2-2) Setup contents
o !;;[ock
, "-)
lime setting of the real time clock is made in Hour/Minute!
Second/AM or PM and Year/Month/Day. The days of the week are
automatically set.
o Disp[ay
This setup is made for the built-in VGA.
*Cursor type: Underline/Under bar/Block
Set the cursor from when booting the system or when changing
the video mode.
;, LCD mode: Standard/Expanded
Set the LCD screen displayed size when booijng the system or
when changing the video mode.
o Keyboard
This setup is made forthe keypoard.
;, NUM LOCK: ON/OFF
NUM LOCK state a~ booting isset.
;, CAPS LOCK: ON/OFF
CAPS LOCK state atbooting is set.
;, s!;;ROLL LQ!;;K: ON/OFF
SCROLL LOCK at booiing is set.
;, Repeat rate: Standard/Fast
Keyboard repeat rate at booting and after setup is set.
o Serial [/0
Serial 1/0 at booting and after setup is set.
1:1 Internal SIO
Baud rate: 9600 -11 0
Data bits: af7
Stop bits: 2/1
Parity bits: None/Odd/Even
Various settings of built-in 810 are performed.
;, Optional S[O
Baud rate: 9600 -110
Data bits: 8/7
Stop bits: 2/1
Parity bits: None/Odd/Even
Optional
SIO (Modem card) settings are performed.
Setup default parameters
SHARP PERSONALCOMPUTER SET-UP
PROGRAM
01 Power saving
The following power saving" functio.ns are set, ,
r:r Display timeout: 1 =-10 minut,es/A1ways ON
When the keyb9ard has nqt:been-, pressed and no disk drives
have nqt been accessed
for ~h,e specified period, the display
un~ goes into:the low pow~r m,ode.
r:r System timeout: 1 -10 mhiutes/Always ON
When the ,keybo_ard has not been pressed and no disk drives
have not bee:n ~,ccesse~, for the specified period, the system is
temporarily,stopped goes ,into the standby mode.
" __ ~~EL[lQ\'LeL,,=um[>tilmJJLs~s1et1LlimaQUUaJQ\'Ler than dis-
playtimeout.-' -" .. -.. ..
r:r HOD timeout: 30 sec -1 0 minutes/Always ON
When the hard disk ·haJ:! nQt- b~en: ,c:lCge,sse~: ,for the; l;ipeCified
period, the hard disk motor is stopped to cut power consump-
tion. -
-,' , '
© System cOnfigW~tion _
System settings are
,pe~ormed.
;, QU[CK BOOT: ON/OFF
fv1er:nory che,c~ aqd oth4?r tilJle~consuming checks are skipped
and only minimum system checks are made for quick
boot of
the system.
{> SPEED KEY: ENABLE/D[SABLE
Used to set enable/disable of changing the CPU speed
by the
keyboard operation.
{> STANDBY KEY: ENABLE/D[SABLE
Used
to set enable/disable of transition to the system power
saving;mode by the keyboard operation.
;, CPU SPEED, 12f7.16/6 MHz
Used to selthe. CPU clock speedat booting and after setup.
Since' At DUS dock is' arso changed at this setting, the bus
clock
is also displayed.
-----------------,--------C[ock----------------------
~~-~~~~~~~~~~~~~~~~~-Power Saving-~~-~~~--~~-~~~-~~-~
-------------------------Seria[ [/0------------------------
Standard S[O
Time: 2:07:06 p.m.
Date: TUE MAYOa, 1990
-------------------------Disp[ay-------------------------
CursorType:
LCD Mode: Underline Standard
-------------------------Keyboard------------------------
Caps Lock:
Num Lock:
Scroll Lock:
Off
Off
Off
Repeat Rate: Fast
1. Position Cursor using cursor keypad
Display Timeout: 1 minute
HOD Motor Off: 1 minute
System Timeout: Always ON
~~~~~~-~~-~~-~~System Co nfigurations-~~~-~~~-~~~--~~
CPU Speed: 12MHz
BUS Speed: 6MHz
Quick Boot: On
Standby Key:
Enaib[e
Speed Key:
Enaib[e
2. Press Space Bar to change
-6-
Baud Rate: 9600
Data Bits: 8
Stop Bits: 1
Partty:
Optional S[O
Baud Rate:
Data Bits:
Stop bits:
Parity:
None
9600
a
None
3. Press Set-Up
Key to exit

3) Hardware installation
3-1) Hardware installation procedure
There are three procedures for hardware installation.
CD Perform hardware installation during user diagnosis.
(2) Press ENTER key when "Invalid Configuration Information" error,
etc. occurs.
(;ll Press CTRL +ALT+SET UP keys during setup operation.
3-2. Hardware installation
-0 Bisplay configuration
-{:; Display mode: VGAlEGAlCGAlMDAlHGC
Used to
set built-in VGA.
-(:; Display adaptor: Internal VGAlCGABO/CGA40/MDAlOthers
Used to set the display adaptor state when the expansion box
is connected. By this setting, the display adaptor can be used
instead of the
built~in VGA when the builHn VGA is not used
and the expansion box is connected.
If the expansion box is not connected, the built~in VGA is used
regardless of this setting.
€) Drive assignment
-{:; Drive A: OptionaI3.5"FDD External 5.25"FDD
-{:; Drive B: External 5.25FDD" Optional 3.5"FDD
Used to set FDD assignment. When the expansion FDD is not
connected, the option FDD is assigned to Drive A regardless
of
this setting.
'" Drive C: Internal HDD ROM disk
-{:; Drive D: None Internal HDD
Used to set the internal
HOD and ROM disk assignment and to
set the booting drive assignmentwhen FD is not inserted.
o 1/0 configuration
Used to set hardware
1/0 port.
-{:; Parallel Port: PORT1/PORT2/DISABLE
Used to set port address of the internal parallel port.
-{:; Internal SIO Port: PORT1/PORT2/DISABLE
'" Optional SIO Port: PORT1/PORT2IDISABLE
Used to set SIO port address.
-{:; ROM disk 1/0 port: 1?BH -1?BH (?:O-F)
Used to set 1/0 port address used by the ROM disk.
ROM disk port address is effective even though ROM disk is
set to NONE.
ROM disk
110 port address may be changed to pr~vent butting
when a card is inserted into the expansion box.
-{:; EMS 1/0 port: 2?BH -2?BH (?: either of 0, 1,4, 5, 6, A, B, E)
EMS 1/0 port is effective even though EMS is not used.
EMS port address may be changed to prevent butting when a
card is inserted into the expansion box.
-7-
10 Memory configuration -
PC-6220
For memory setting, commercially available memory can be used for
the expansion box. Therefore, the user must register the size of
internal memory connected currently.
-{:; Internal memory size: XX MB 1 - 3MB
The user must register the total size of Sharp memory.
Each memory capacity is assigned
and displayed according to
this total memory.
-{:; Boundary address: XXXXXXXH
Used to set boundary of releasing memory address to the
expansion box. According to this -value,- the sizes
of 1 Mb
memory and EMS memoryare determined.
-{:; With the above items, the following items are displayed.
o Main memory: 640KB
Main memory capacity is displayed. It is fixed to 640KB.
o Extended memory: XXXXXX KB (XX.x MB)
The memory capacity
over 1 MB is displayed. Memory in the
expansion box is not displayed. Only Sharp memory is dis-
played.
o Expandedmemory: XXXXXX KB (XX.X MB)
EMS memory capacity is displayed. Memory in the expansion
box is not displayed. Only Sharp memory is displayed.
o Disabled memory: XXXXX KB
Depending on the memory boundary
set value, 256KB
memory maybe disabled.
4) Others
4-1) Default values of hardware installation and setup
To reset parameters of hardware installation and setup to the default
values, press CTRL + SPACE keys. Then the displayed parameters
will
be reset to their default values. To reset all the parameters, press
CTRL + SPACE keys for each of hardware installation and setup
screens. Data and Time, however, will
not be reset to the default
values.
4-2) Starting ROM disk
Press CTRL + ALT + SETUP keys and periorm setup. While setup is
executed, press CTRL + ALT +SETUP keys again,
the set goes into
hardware installation.
Then set drive C to ROM disk, and drive D to hard disk, and start the
set again.
4-3) When the screen is not clear on starting
The PC-6220 stores the pallet value on power off. Therefore, some
pallet value setting just before power off may result in unclear screen.
In this case, press Fn +SETUP.

-
,~EC~&229=
1-4. BIOS POST (Power On SelfTest)check
.Error.d·et!3cth~m and report
When the system is started, BIOS POST program is executed.
In POST, .operations .of the system :RAM ihterruptidn and- various
devices includir:lg peripheral ,devices - are- checked. The operation
checks are classified into" two groups according to 'error report.
1) Error report by VO port 80h (MFG port) and beep souna
?} Error report by ~essage displayed on the screen
-For:-the-tests-whicttcuse-thErVe-porr801r(MF~rand- beep
sounds, the test items and the, output data to the port BOh are shown
in the foIJo~i~g table.
For the test item with "NONE" in the colutTIn of Beep sound, the
system does not stop. Fgr -the: other te~ items, when any error oc-
curs, beep sound is generated and the system is stopped. '
.. " , -- " .
(Note) Figures jlJ the ooliJm~ ,9f b~ep' so~nd;'show,s, the -~umber of
be~p. For eX<;I.mple, "1-3-4",shows "l heep sound,' pause, 3
beep sounds; pause, and 4 beep sound." '
Hardware installation
SHARP PERFONAL COMPUTER HARDWARE INSTALLATION
--------------------------------DisplayConfiguration--------------------------------
Display Mode: VGA Mode
Display Adaptor: Internal VGA
----------------------------------1/0 Configuration-----------------------------------
Internal Serial Port: Port 1
Optional Serial Port: Port 2
Internal Parallel Port: Port 1
ROM Disk I/O Port:
EMS 1/0 Port: 1C8h-1CBh
218h-21Bh
1. Position Cursor using cursor keypad
Test items
PORT 80li
Beep "ound
CPU register test'
01h
None
RTC RAM readlwrite test 02h 1-1-3
BIOS ROM check s.~m lest 03h 1-1-4
system timer (82S4) test 04h
1-2-1
DMAC initializing test
OSh 1-2-2
DMA pags-'register test
06h 1-2-3
RAM refresh test
08h 1'3-1
First 64KB sy-siemBAM test start
Q9b.
.Noru;L.
First 64KB RAM plural data fiDes error OAh
1-1-1
First 64KB RAM contror logic error
OBh
t-3-4
First 64KB RAM address line error oth
1-4-1
First 64KB RAM parity test
ODh
1-4-2
First 64KB RAM data line error
(BITO) 10h 2-1-1
Rrst 64KB
RAM data line error (BIT1) . i1h·
2-1-2
Firsl64KBRAM data line error (BIT2)· 12h 2-1-3
First 64KB RAM data line error (BIT3) 13h 2-1-4
First 64KB RAM data line error (BIT4) 14h 2-2-1
Rrst 64KB
RAM data line error (BITS) 1Sh
2'2-2
First 64KB RAM data line error (BIT6) 16h 2-2,3
First 64KB RAM data.!ine error (BIT7) 17h 2-2-4
First 64KBRAMaata line error (BIT8) 18h 2-3-1
First 64KB RAM data line error (BIT9) 19h 2-3-2
Rrst 64KB RAM data line error (BITA) 1Ah 2-3-3
Rrst 64KB
RAM data line error (BITB) 1Bh 2-3-4
First 64KB
RAM data line error (BITC) 1Ch
2-4-1
First 64KB RAM data line error (BITO) 1Dh 2-4-2
First 64KB RAM data line error (BITE) 1Eh 2-4-3
Rrst.64KB
RAM data line error (BITF) 1Fh 2-4-4
Slave DM.!IC register test 20h
3-1-1
Master DMAC register test 21h 3-1-2
Master interrupt mask register test 22h 3-1-3
Slave interrupt mask register test 23h 3-1-4
Interrupt vector setting 2Sh
None
Keyboard controller test
27h 3-2-4
RTC RAM power check sum test
28h None
RTC RAM content validation test 29h
None
Display memory (VRAM) test 2Bh 3-3-4
Display initialization test 2Ch
3-4-1
Display line signal test
2Dh 3-4-2
Display ROM searching 2Eh
None
Display test complete
30h None
Monochrome display allowed to use 31h
None
Color display (40 columns) allowed to use
32h None
Color display (80 columns) allowed to use'
33h None
----------------------------------Drive Assignment---------------------------------
Drive A: External 3.5" FDD
Drive B:
Drive C:
Drive D:
External S,2S" FDD
Internal HOD
None
-----------------------------Memory Configuration--------------------------------
Internal memory Size: 1 MB
Boundary Address: 110000h
... Main Memory:
• Extended Memory:
... Expanded Memory:
... Disabled memory:
2. Press Space Bar
640KB
64KB
320KB
OKB
3. Press Set-Up Key to exit
Fig. 1-7
8-

CHAPTER 2. Disassembly and
assembly
2-1. Precautions
Before disassembly, remove the AC adaptor and the built-in Ni + cad
battery. A precise screwdriver is required for disassembly.
Since some screws and component parts are very small, tidy up the
work t8.ble- and be sure not to -lose the components~- - - - - -
2-2. Keyboard section
Disassembly
1) With the LCD section closed, remove the two black screws at the
bottom. (Fig. 2-1) (Screw: a)
2) Open the LCD section, pull the function keys side of the keyboard
towards you, unlock the connector of keyboard on the main P,W.s.
keyboard and remove the FPC.
a b",!
b 9 \ ~
1 1 ~
a
b
Fig. 2-1
Fig. 2-2
-9-
Assembly -
PG-6220
') Attach the keyboard to the set by reversing the disassembly pro-
cedure. Be sure to fully insert the FPC cable of the keyboard and
lock the connector.
2-3. Upper/lower cabinet disassembly
Disassembly
1) Remove the keyboard_ accordin~ to procedure 2-2.
2) Remove screw which are fixing the upper cabinet and the main
PWB. (Fig. 2-3) (Screw: c)
c
\\
Fig. 2-3
3) Remove the connector covers. (4 covers: Key pad, battery, expan~
sian bus, parallel)
Keep the RS-232C cover open.
4) Close the LCD section and place the set upside down.
5) Remove the four rubber cushions fixed to the bottom by duplex
tape. Then remove the four screws which are fixing the lower
cabinet and the upper cabinet. (Fig. 2-1) (Screw: b)
6) Remove the screw atthe back. (Fig. 2-4)

-
"R","-tr~2(}~- .
7) Remove the engagement section of the upper and IOWi3:f cabinets.
S_ince _the ,upper ,and lower cabinets are connected ,with ,u:5o
'cables', '8tC'.',' praae: the set as' sryown'· in' Fig._ 2-5 and -remove' the
'corineCtors."" ''', . -, ">"' -, • '"' -,.-.
Fig. 2-5
Assembly
1) Assemble the upper and lower cabinets by reversing the disas-
sembly procedures.
2) Attach the keyboard to the set.
2·4. Hard disk replacement
Since the hard disk is ,8 precision device, be careful handling it.
Especially when it is removed from the set, it is easily susceptible to
electrostatics and vibrations.
Disassembly
1) Remove the keyboard.
2) Separate the uppercabinet from the lower cabinet.
3) Remove the three
scre~s (H) which are fixing the hard disk unit.
Fig. 2-6
4) Unlock the connector of hard disk on the main P.W.B. and careful-
ly remove the FPC.
Handle the power cable with care. If disassembly is difficult be-
cause of the power cable, remove the power unit and disas-
semble.
-10-
Installation
.. _J' .' - __ ::,:, ' __ .oJ ; ___ ", __ ,
1) Install the hard disk by reversing the disassembly procedure.
2) The fixing screw of the hard disk may be easily dam-aged by
excessive tightening. So, slowly turn it until it stops and carefully
tighten it.
3) Attach the upper and lower cabinets to
the set
4) Attachthe keyboard to the set.
~5;-Power unit
Disassembly
1) Remove the keyboard.
2} Separate the upper cabinet from the lower cabinet.
3} Remove the screw (P) which is fixing the power untt,-then remove
,the power unit.
Remove the two connectors. (Fig. 2-6)
When it is difficult to remove the connectors, remove the hard disk
first. '
Installation
1) Install the power unit by reversi~g the disassembly procedure.
2} Attach the upper and lower cabinet to the set.
3) Attach the keyboard to the set.
2·6. Main PWB
Disassembly
1) Remove the keyboard.
2) Separate the upper cabinet from the lower cabinet.
3} Remove the hard diskunitand the power unit.
4) Remove the
ROM PWB.
5) Remove the buzzer connector.
6) Remove the four screws (M).
Fig. 2-7

7) With the main PWB hanging in the air, unlock the connector of the
key pad on the soldering suriace of the PWB, and remove the
FPC.
Note: When treating the main PWB, be careful to electrostatics.
When soldering is periormed,
be sure to clean and remove
soldering dust from the PWB
suriaC6. Then install the PWB.
Installation
1) Install the PWB by reversing the disassembly procedure.
The flxing screw of the lower cabinet may be easily damaged by
excessive tightening.
So, slowly turn it until it stops and carefully
tighten it.
2) [nstall the hard disk unit and the power unit.
3) Attach the ROM PWB.
4) Attach the upper and lower cabinets.
S) Attach the keyboard to the set.
2·7. LCD section and upper cabinet
Disassembly
<Caution>
For
disassembly of the LCD unit, be sure to follow the procedure
below. If not, the cabinet may be damaged.
1) Remove the keyboard (See procedure 2·2.)
2) Separate the upper cabinet from the lower cabinet. (See proce-
dure 2·3.)
3) Remove the four screws which are fixing the tilt mechanism.
Fig. 2·8
4) Move a tilt mechanism to the center with a screwdriver, and
remove it upwards.
Then remove the other tilt mechanism
in the same manner.
Fig. 2-9
-11-
-
PG-6220
5) Operate the LCD release lever, unfix the upper cabinet and the
LCD section, and separate the upper cabinet from the LCD sec-
tion.
In this case, be careful not to damage two LCD cables. Though
this procedure can be periormed without removing the open sen-
sor switch in the LCD section, it is advisable to remove it in
advance
to protect the cable from being damaged.
Installation
1) Install the upper cabinet and the LCD section by reversing the
disassembly procedure.
When installing the tilt mechanism, set the shaft horizontally in
parallel to the angie bottom and insert into the LCD section. (Fig.
2-10)
Fig.2-10
2) Attach the upper and lower cabinets to the set.
3) Attach the keyboard to the set.
2·8. LCD section
Disassembly
<Caution>
For disassembly of the LCD unit, be sure to follow the procedure
below. If not, the cabinet may be damaged.
1) Remove the keyboard. (See procedure 2-2.)
2) Separate the upper cabinet from the lower cabinet. (See proce-
dure 2-3.)
3) Remove the upper cabinet. (See procedure 2-7.)
4) Remove the four rubber cushions fixed with duplex tape on the
LCD section, and remove the four screws which were covered by
the four rubber cushions. (Fig. 2-11)
Rg.2-11

-
c~I?k~220=c~_
5) Remove :the fron~ _and: rear'eabinets of the LCD section_ ,The 'pawl
which is-fixing the cabinetsis'sh6wn: with (_.)In.Fig __ ,Z--11.
,6) ~~_movf3.the fj)£~lJre which fixes the LCD section an~ the body.
7) Remov~ _~h8 .r~fl~9tiofl plat~ ofthe ~acklig~t:
8) , RemoVe the -ffxing sCreWs and the; conn'e'ctors o-f the iIlumiilation
control
PWB and'the backlight convertor PWB',' and remove the
PW8's.
Assemllly,
1) Assemble the LCD unit by reversing the· disassembly procedure.
Carefully checK that ffiere IS ,lid finaenJtinf. on, the-LCD s.edLoo..Jf
-i-there is; 'clean with a cloth 'and,alcohbl. The cloth must be fine and
smooth, such as glass wiper cloth.
2) Attach the upper cabinet to the set.
3) Attach the lower cabinet to the set.
4) Attach the keyboard 10 the set.
CHAPTER 3. System block diagram
1J'~JS_ f'_~8!,\_"!I_Q?~?
; - ~ ---- _. -- -- -- ~ :
L _il
20MB
Fixed Disk
82C455
VGA Controller
Connector
-Portable FDD
U"t
• Expansion Unit
Card Connector
:-~Extend SID Card
: • Modem Card
i
~~~lil~~~~~~:~==~=~~ ~_:CRT I/F Card
Video/LCD
Signal
: Ten kay
: Unit Des's
Note) Dot line indicatt:e:s~o:p:ti:on:a:I-. ---t~t~~~fTIlliii~-rr;;;~~l-~~~~
Control
-12-
lCO
Power
Power
Supply
Unit
External ConnedorPower
.""i------ -------.----.
~j __ ~~~~~ _~~t~~~ ___ :;
ACAda~
Jack AC
Addaptor

~
'"I
~ MainPWB
! I ~~~'~"',=, 0='=' .=-=, C=C'-" -~.-.-'---C--:-O-'-O~-:':=~' C~C;:=, C=.=~. ~. : "",J:."'~
'" ' I' n~-'1"nr""nn""nnnr."'r.'1[Jn-H"":lf ~""'1n [ "",,,,~
01 • • -r~--~n[J,~---,-~---""r---n-~ ~ •.
, I I r - ',' I l n - n n '"") ----- I - - -, -n "; ,~ I I
~i!);;~ii~;~~,;~~ .,' m[~H:I:
If=== O~OCCONV'~1 1'1
0
:; ~". ~:~':;.I
o Generation.5V III II -----; _ _!lI.,,, .... ,_~_<:>-" _.
q Fmm+5V 11 ~" ---- =;., " .. " :1
U
~~0 C .;<.' II
! ~ _~ .~~ ~,,~,,~-~~ 1
o I ~. ,. '-'.'ft: ....• ;=;;:; I
f? "~~ 00., II
)1. I .. , . ~l ......... I
}(~. 'JO". __ 0.....::Jl~]""")O ':10."10_0 fJ'1
I '1 I ¢. 1') ". -- , '
, • JlI'WI'i:'I,n;I:T "'II '1111 " .,'. 1·
. ·~\':1~;;;;;,." ... ;:::.; .. ~. ~;
!",;;o-o;.-", <l('O'0N.-- ,' •• '=:-,
VGA (Chips)
80C42G
, ,_ • <~ "'i~~!'II~~;:II;F~~;I~I:'I~'-I'iI~,il;' ;~-;;:
KeYCOntroller,IIOPort~lr",- __ i: __ :: II '.' '
i'I!"'--~
V-RAM (256K8)
n~ng 'j -
gng~=-_-~
n
f1
nC
nOnG -- '0,'
n~ng.
SC9889B (Super Integrated)
ATfXT oompalible system oonlroller
82C59A X 2 for interrupt
82C54 X 1 (Timer)
82C50 X1 (UARn
C·MOS RAM (2K8)
RAM control oircuit
80C286 interlace 1
! ~ •;j
i:;' , ',',2 ~ ,_ ';:'( __
h_ ! ~ I ;'i--;~':'-:--1 ill i"F
"""'-"',:' ....... 'r
t.-nnl ,~':.~, !liir'~
l;:;j _~ "ji:::~ ~\;".,,~
I~- IIi H_,~n;;~;' 1111 i .~.
[I ,"C'" """,,,
. - ""~I
o 0 Q ) Lt] (} 0 C'~:=::====·=-=·i''==:=:::=::=F:=:::=::=?
~ j
ATC
ROMPWB
" ('>",.., ,., ,., (\ " ,., (\ " "
O.,,.,O")f'0r,00r-OO
~;:rr~"q:~,r,
V
I
1
"
::'::.s\~l::~I~li::i :
HH;ii;;;;;;i~u tf1'J
l\ lO,
OPTION 80C287 (CO·PROCESSOR) sakel.
12MHz C·MOS version used.
(40 pin dip type)
Name: Inle180G287-12
DOS ROM n
8Mbit mask ROM
SC9871 (DMAC)
-,
,
<
8237 X 2+0MAC peripheral circuit are inclUded.
, It .~ . ___ ~_----.. r I
'-' J) " ~"-----"'I' " '...,
,--',.'-_f "
"
"T~~-~~-:---l
0:
(>" ,,~. J,.,:l 'l
.,iI
", -.., ~
.. ~.., "
:: : t;' ~
'-, ,,<1
,--0'"
,- ~:;
.-, 0
r~ >
r,0
•
~ ;
v
"
c\
,
~
oil
Standard
RAM
512K8yle
rrhere are 512 K8yle"in Ihesolder side
tOlal:
1MByle
f'~- 0 .. 11
-A ,,~; !i Keyboard
1" ,-, "'" i I trIntroller
]j~~:
'W1~. '" .... ~':Iii ~: ~f3 ~~n
:c .. c ,,:~:,>,:: f~,; f\; ~ '''' eO,
•• _ ••• ,;'.,'.1.:
CPU eoC286
~
LZ95H22
printer/ROM
Controller (With S·RAM) 12MHz
G--MOS VersIon
~I
l:l

--
cI'e"'C622(f
-14-
o
o
o
o~

CHAPTER 4. Theory of operation
4-1. Processor
4·1-1. CPU
This unit employs 12MHz version of 80C286 as the CPU, which
operates at three speeds: 6MHz, 7.16MHz, and 12MHz. Its selection
is possible at any tLme by writing Ll1tQ th~ 2QIT QY 1h~ pr9gra!1l~
One period from falling to next falling of a clock which is inputted to
the CPU is called as "phase." There are two phases: phase 1 ($1)
and phase 2 (~2). The CPU recognizes the next phase to the rising of
a reset signal
as phase $2, and repeats phase 1 and phase 2 alter-
nately until
the reset signal rises again.
The combination of $1 and $2 is called as "state." There are four
states: status state (Ts), command state (Tc), idle state (TI), and hold
state (Th). Ts shows the cycle where the CPU is trying to make status
signal
(%80, *81) active. Te shows the cycle where command signals
(~MEMW, ~MEMR, ~IOW, ~IOR, ~INTA) are made active to perform
data transmission.
(The signals, however, are not always made ac-
tive.) When the CPU make access to a device, a continuous state
composed of one Ts called cycle and one or more Tc's. One cycle is
executed by
repeating the following steps.
CD First, the CPU generates address.
CZl Then the CPU generales status signal which shows the cycle to
be executed. (TS)
@ The system control LSI (SC9889A1E» decodes address and status
and outputs the necessary control signals (command signal,
select signal
of memory and each device). (TC)
@ The SC9889B controls each buffer according to data transmission
direction,
and transmits data from the CPU/device to the
device/CPU. (Tc)
® After completion of transmission, the SC98B9B returns the ready
signal to the CPU and completes the cycle. (The last Tc)
Fig. 4-1 shows the outline of the cycle.
PRCLK . . .
: $1 :$2:
: TS ' TC
Te Te Te
A23·AO =:J==~'.~;'~"~"~'"~"C=X==~========~==
SO.S1 ='
Command !._ ... ~. ___ ~I ________ --,'-
READY
_
____ ~'="~m=m'=oo=d="=Y ______ ~~ _ __1
r
• 80C286 Description
Features
Fig. 4·1
Compatible with NMOS 80286
Static CMOS Design for Low Power Operation
~ ICCSB = SmA Maximum
~ Iceop = 220mA Maximum (80C286·t2)
3 wait
High Periormance Processor (Up to 12 TImes the 8086 Through·
put)
·l-arge-Address Spaeec-- .
~ 16 Megabytes Physical
~ 1 Gigabyte Virtual per Task
Integrated Memory Management, Four-Level Memory Protection
and Support for Virtual Memory and Operating Systems
Two 80C86 Upward Compatible Operating Modes:
-1S-
~ 80C286 Real Address Mode
110- Protected Virtual Address Mode
-
PC-6220
Compatible with B0287 Numeric Data Co-processor
Wide Range of Clock Rates:
~ DCto 12.SMHz (80C286·12)
High Bandwidth Bus Interface (16 Megabyte/Sec)
Available in 68 Pin PGA (Pin Grid Array) and PLCC (Plastic
Leaded Chip carrier) Packages
Description
The Harris 80C286 is a static CMOS version of the NMOS 80286
microprocessor. The BOC286 is an advanced, high-performance
microprocessor
with specially optimized capabilities for multiple user
and multi-tasking systems. The BOC286 has built-in memory protec-
tion that supports operating system and task isolation as well as
program and data privacy within tasks. A 12.5MHz BOC286 provides
nine times or more throughput than the standard 5MHz B086. The
80C286 includes memory management capabilities that map 230 (one
gigabyte) of virtual address space per task into 224 bytes (16
megabytes) of physical memory.
The 80C286 is upwardly compatible with 80C86 and 80C88 software
(the BOC2B6 instruction set is a suparset of the 30C86/BOC88 instruc-
tion
set). Using the 80C286 real address mode, the 80C286 is object
code compatible with existing 80CB6 and 80CBB software. In
protected virtual address mode, the BOC2B6 is source code com-
patible with 80G86 and BOC8B software but may require upgrading to
use virtual address as supported by the 80C286's integrated memory
management and protection mechanism. Both modes operate at full
BOC286 performance and execute a superset of the 80C86 and
80C8B instructions.
The BOC286 provides special operations to support the efficient im-
plementation and execution of operating systems. For example, one
instruction can end execution of one task, save its state, switch to a
new task, load its state, and start execution of the new task. The
80C286 also supports virtual memory systems by providing a seg-
ment-not-present exception and restartable instructions.
f-
" w
'"
"'
0
0
;;:
N
~
" w
"'
"'
" >
a:
v
~
vss 35
Do 36
08 37
01
14
13 A18
02 12
A19
010
11 A20
03 10
A21
011
04
012
05
013
06
48
014 49
07 50
015 51
Top view

';-,--
---, ' ,
........................................ -.: J
' , ., ,
...._------------------- .. _......_ .. _-- -_ .. _--- ............. _._-_ ..... _._-._ ..... -
j ADDRE..<:S UNIT (AU)
. ,
./1
I
I
..
Table 4-1 80C286 Pin description
$igrjal
PinNa.
1/0
. Name and Function
.,Vee
30,62 I ;System power. +5V power supply.
, Vss
9,35,60,
" I ' System
gro~nd: oV
RESET 29 I System Reset clears the internal logic of
t,he 80C286 and is active HIGH, The CPU may be
reinitialized
at anytime with a LOW to I:iIGH transition on RESET .-which remains active for more than
16
sys~em clock cycles, During RESET remains active, the output pins of the CPU enter the state
shown-below:
" ' ,
80C286 Pin State During Reset
,pin yalue Pin Names
1 (HIGH)
SO, S1, PEACK, A23 - AO, BHE, lOCK
o (LOW) MilO, COO/INTA,
HlOA
3'state OFF
015- DO
Operation of the 80C286 begins after a HIGH to LOW transition of RESET. The HIGH to lOW
transition of RESET must be synchronous to the system clock. Approximately 50 system clock cycles
are required
by' the CPU for internal initializations before the first bus cycle to fetch a code from the
power-on execution address
is performed.
A LOW to HIGH
tri3,nsition of RESET synchronous to the system clock will end a processor cycle at
the second HIGH
to lOW transition of the clock, The lOW to HIGH transition of RESET may be
asynchronous
to the system clock; however, in this case it cannot be predetermined which phase of
the processor clock will occur during the next system clock period. Synchronous LOW to HIGH
transitions of RESET are required only for systems where the processor clock must be phase
synchronous to
anot~er clock.
ClK 31
I System Clock provides the fundamental timing for 80L286 systems. It
is divioed by two inside the
CPU to generate'the,processor clock. The 'internal divide-by two,circuitry can be synchronized to an
external clock generator by a LOW to HIGH transition on the
RES~ input.
015-00 51 -36
110
Data Bus inputs data during memory, 1/0, and interrupt acknowledge read cycles; outputs data
during memory and
1/0 write cycles. The data bus is active HIGH and floats to 3_RSt~t~ _OFF ~uri~g
bus hold acknowledge.
!\23-AO
7,8, a Address bus
output~ physical memory and 110 port addresses. AO is LOW when data is to be
10-28
transferred pins D7:00:'A2.3
R
A16 are LOW during
1/0 transfers. The address bus IS, active HIGH'and
32-34 floats to 3--state OFF'during bus hold acknowledge.
BHE 1 a Bus High Enable indicates transfer
of data on the upper bYtes of the data bus, 015-08. Eight-bit
oriented devices
aSSigned to the upper bytes of the data bU_S would normally use SHE to condition
chip select
functioris~ SHE is active LOW and floats to 3R state OFF during b;us hold acknowledge.
BHE and
AO Encodings
BHE'valu AOValue Fuaetion
l l Word transfer
l H Byte transferon upper half of data bus
(015 - 08)
H l Byte transfer on lower half of data bus (07 - ~O)
H H Reserved
16-

-
PC--£220
Signal
Pin No. 1/0
Name and Function
S1,SO
4,5 0 Bus Cycle status indicates initiation of a bus cycle and, along with
MilO and COD/INTA, defines the
type of bus cycle. The bus is a
Ts state whenever one or both are LOW. 81 and SO are active LOW
and float to 3-state OFF during bus hold acknowledge.
aOC286 Bus Cycle Definition
COD/INTA MilO
S1
SO Bus Cycle Initiated
L L L L Interrupt acknowledge
L L L H Reserved
L L H L Reserved
L L H H None;
not a status cycle
L H L L If
Ai = 1 then halt; else shutdown
L H L H Memory
data read
L H H L Memory data write
L H H H None;
not a status cycle
H L L L Reserved
H L L H
1/0 read
H L H L
lIO write
H L H H None;
not a status cycle
H H L L Reserved
H H L H Memory instruction read
H H H L Reserved
H H H H
None; not a status cycle
MilO
67 0 Memory-I/O Select distinguishes memory access from
110 access. If HIGH during Ts, a memory
cycle or a halt/shutdown cycle
is in progress. If LOW, an I/O cycle or an interrupt acknowledge cycle
is in progress. MilO floats to 3-state OFF during bus hold acknowledge.
CODIINTA
66 0 Code/Interrupt Acknowledge distinguishes instruction fetch cycles from memory
data read cycles.
Also distinguishes interrupt acknowledge cycles from I/O cycles. COD/INTA floats
to 3-state OFF
during bus hold acknowledge. Its timing is the same as M/IO.
LOCK
68 0 Bus Lock indicates that other system bus masters are not to gain control of the system bus following
the current bus cycle. The LOCK signal may be activated explicitly by the "LOCK" instruction prefix
or automatically
by 80C286 hardware during memory XCHG instructions, interrupt acknowledge, or
descriptor table access. LOCK is active LOW and floats to 3-state OFF during bus hold acknow-
ledge.
READY
63 0 Bus Ready terminates a bus cycle. Bus cycles are extended without limit until terminated by READY
LOW. READY is an active LOW synchronous input requiring setup and hold times relative to the
system clock be met for correct operation. READY is ignored during bus hold acknowledge.
HOLD
64 I Bus Hold Request and Hold Acknowledge control ownership of the 80C286 local bus. The HOLD
HLDA
65
0 input allows another local bus master to request control of the local bus. When control
is granted, the
80L286 will float its bus drivers to 3-state OFF and then activate HLDA, thus entering the bus hold
acknowledge condition. The local bus will remain granted to the requesting master until HOLD
becomes inactive which results in the 80C286 deactivating HLDA and regaining control of the local
bus. This terminates the bus hold acknowledge condition. HOLD may
be asynchronous to the
system clock. These signals are active HIGH.
INTR
57
I Interrupt Request requests the 8DC286 to suspend its current program execution and service a
pending external request. Interrupt requests are masked whenever the interrupt enable
bit in the flag
word is cleared. When the 80C286 responds to an interrupt request, it performs two interrupt
acknowledge bus cycles to read
an 8-bit interrupt vector that identifies the source of the interrupt. To
assure program interruption, INTR must remain active until the first interrupt acknowledge cycle is
completed. INTR is sampled at the beginning of each processor cycle and must
be active HIGH at
least two processor cycles before the current instruction ends in order to interrupt before the next
instruction. INTR is level sensitive, active HIGH, and may
be asynchronous to the system clock.
NMI 59
I Non-Maskable Interrupt Request interrupts the 80C286 with an internally supplied vector value of 2.
No interrupt acknowledge cycles are performed. The interrupt enable bit in the 80286 flag word does
not affect this input. The NMI input is active HIGH, may be asynchronous to the system clock, and is
edge triggered after internal synchronization. For proper recognition, the input must have been
previously LOW for
at least four system clock cycles and remain HIGH for at least four system clock
cycles.
PEREO 61 I Processor Extension Operand Request and Acknowledge extend the memory management and
PEACK 6 0 protection capabilities of the 80C286 to processor extensions. The input requests the 80C286 to
perform a data operand transfer for a processor extension. The PEACK output signals the processor
extension when the requested operand is being transferred. PEREQ is active HIGH and floats to
3-state OFF during bus hold acknowledge. PEACK may
be asynchronous to the system clock.
PEACK is ac1ive LOW.
BUSY 54 I Processor Extension Busy and Error
indicate--th-e -operating condition of a processor exfensTon to the
ERROR 53 I 80L286.
An active BUSY input stops 80C286 program execution on WAIT and some ESC instruc-
tions until BUSY becomes inactive {HIGH}. The 80C286 may
be interrupted while waiting for BUSY
to become inactive. An active ERROR input causes the 80C286 to perform a processor extension
interrupt when execution WAIT or some ESC instructions. These inputs are active LOW and may be
asynchronous to the system clock.
-17 -

4-1-2: Numerical calculation processor(OPTION)
This unit cah connect with-the optiorialBOC287 numerical calculation
processor (NP-X). The NPX operates on 12MHz. The NPX is an ex-
pansion of the 80C286 CPU architecture. The CPU regards the
NPX
as ail 1/0 device occupying OF8h - OFFh. The NPX itself has no bus
control function. When, therefors, the NPX requires data, PEREQ
signal is made active to request the CPU to transmit data. The CPU
makes *PEREQ active to inform the NPX that it has accepted the
request. then the CPU executes data transmisfiliQn. For the NPX, data
are transmitted as the form of lOR/lOW.
- -When--the--ePtFrn:ee~command401herNP-XiESe-cot IIII ralld irra
certain format) during decoding; it info,rms the NPX of it as lOW.
puring the execution of this command) the,NPX makes ;:BUSY signal
active to control the CPU not tq transmit ESQ, command any more. If
there is any erroneous calculation during proqessing, the NPX makes
;:ERROR signal and ;:BUSY signal low simultaneously to show the
error. The
SC9889NB LSI latches the '.BUSY signal and informs the
CPU, which stops processJng of the, commands following the error.
The error is transmitted through interruption level 13 (IRQ13) to the
CPU. The error treatment-by. ,the;CPU :differs from different application
program, and the following two ports are used.
Address Data
Operation
OFOh (lOW)
No niElaJiirig
Clears latched "BUSY signal.
OF1h (lOW)
No meaning
Hard reset the NPX in addition
to the above.
The port is not effective when reading.
·NDBUSY
*NDERROR
'"BUSY
PEREQ
*PEACK
n
u
Fig. 4-2
-18-